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UPD780058GC-067(IC601):CPU
1.Terminal layout
2.Block diagram
TO0/P30
TI00/INTP0/P00
EVENT COUNTER1
TI01/INTP1/P01
TO1/P31
TI1/P33
EVENT COUNTER1
TO2/P32
TI2/P34
EVENT COUNTER2
WATCDOG TIMER
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
S12/RXD/P70
SO2/TXD/P71
SCK2/ASCK/72
ANI0/P10-
ANI7/P17
A/D CONVERTER
AV
33
AV
REF0
ANO0/P130
ANO1/P131
D/A CONVERTER
AVss
AV
REF1
INTP0/P00-
INTPS/P05
BUZ/P36
BUZZER OUTPUT
CLOCK OUTPUT
PCL/P35
1‑28
80
61
60
1
41
20
21
40
16-bit TIMER/
8-bit TIMER/
8-bit TIMER/
WATCH TIMER
SERIAL
INTERFACE0
SERIAL
INTERFACE1
SERIAL
INTERFACE2
INTERRUPT
CONTROL
CONTROL
78K/0
ROM
CPU CORE
RAM
V00 Vss IC
P00
PORT0
P01-P06
P07
PORT1
P10-P17
PORT2
P20-P27
P30-P37
PORT3
PORT4
P40-P47
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT12
P120-P127
PORT13
P130-P131
REAL-TIME
RTP0/P120-
OUTPUT PORT
RTP7/P127
RTP0/P120-
RTP7/P127
A8/P50-
EXTERNAL
A15/P57
ACCESS
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
SYSTEM
X2
CONTROL
XT1/P07
XT2
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