Chipset Features Option - ECS P5SD-B Plus Manual

Chipset Features Option

This option displays a table of items that define critical timing parameters of the
mainboard components including the CPU, the memory, and the system logic.
As a general rule, you should leave the items on this page at their default values unless
you are very familiar with the technical specifications of your system hardware. If you
change the values, or load the optimum settings, you may introduce fatal errors or
recurring instability into your system. The item list below shows only the default
values for some items.
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
These items define the timing parameters for Fast Page-mode and EDO RAM. We
recommend that you leave these items at the default values. The default value ensures
reliability if slower memory is used.
SDRAM Cycle Length
This item sets the number of CPU cycles between SDRAM refresh. If insufficient time is
allowed, refresh may be incomplete and data can be lost. We recommend that you leave
this item at the default value.
DRAM Read Pipeline
When this item is enabled, the performance of the DRAM bus speed is faster. We
recommend that you leave this item at the default value enabled.
Cache Rd+CPU Wt Pipeline
When this item is enabled, the transfer speed from cache to RAM is faster. We recommend
that you leave this item at the default value enabled.
Default: FP/EDO 70ns
Default: FP/EDO 70ns
Default: FP/EDO 70ns
Default: 3
Default: Enabled
Default: Enabled
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