Bose BUILT-INvisible TA-1 Service Manual page 12

Digital Signal Processor (DSP) PCB (continued)
Microcontroller (continued)
6. Other ADC ports are used for the following functions:
• To monitor the gross DC offset on the five satellite speaker channels. Excessive DC offset is
assumed to be an indication of a serious problem and the microcontroller will respond to this
by shutting off the power to the amplifier.
• To detect the presence or absence of a digital S/PDIF signal. The codec cannot be set up for
an analog input and a digital S/PDIF input simultaneously and it cannot be reprogrammed
from analog to digital (or vice versa) without interrupting the audio signal.
To sequence the mute line. As with the Series I, there are three so-called "speaker modes",
•
2-channel (bass, left, right); 3-channel (bass, left, right and center) and 5-channel (bass, plus
all 5 satellites). Unused output channels are muted, not only at the DSP but also at the power
amplifier. The mute inputs to the power amplifiers are 5V logic-level outputs from the
microcontroller.
• The microcontroller is in charge of booting the DSPs at power-up in the following
sequence:
- Boots the codec and establishes the correct output signals from the codec (bit_clock,
frame_clock, and data).
- Enables the 3.3V power supply, and verifies the correct voltage from it.
- Releases the DSP reset line and waits for the DSPs to boot and acknowledge.
The microcontroller is always engaged in dialogue with both DSPs. If the DSPs should fail to
respond within a certain time-out, it is assumed that the DSPs have "crashed" and the DSPs are
rebooted. The microcontroller must pass some of the nonvolatile information in the EEPROM
over to the DSPs at boot time, e.g.: speaker eq, system volume (all volume control in is done in
the DSPs), center and surround volume and bass and treble pot position. The microcontroller
itself can be reset in two ways, by a hardware reset signal, which is generated by U200 when
the 5V supply drops below 4.75V and by the microcontoller itself, once it has already booted
successfully (it can pull its own reset line if the 8 MHz clock is running).
Codec
The codec U100 [sheet 1, C4] is a highly integrated device which includes the following
functions:
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• An I C interface for control and status information.
• Three channels of 20-bit ACD; only two are used, one for the left analog input and one for
the right. The ADCs will input signal levels in excess of 1 Vrms.
• Six channels of output DAC; all six are used. Maximum output signal level is 1 Vrms.
• A crystal oscillator which establishes the ADC/DAC sampling rate, in this case, it is
11.2896 MHz / 256 = 44.1 kHz.
• A S/PDIF receiver. "S/PDIF" stands for Sony/Philips Digital Interface Format. Essentially, for
every pair of 20-bit audio samples, another 24 bits of status, parity-checking and general
housekeeping bits are sent along for the ride. The data is encoded in such a way that:
a) there is no net DC content to the bit steam, allowing transformer or AC coupling and
b) the bit clock can be recovered from the bit steam.
THEORY OF OPERATION
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