Fixed-Cycle Timer Interrupt Interval (Example); Fixed-Cycle Timer Start Timing - Epson RA8804 CE Applications Manual

Real time clock module
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RA8804 CE

8.3.3. Fixed-cycle timer interrupt interval (example)

Preset Value
4096 Hz
TSEL1,0 = 0,0
0
1
2
41
82
128
192
205
320
410
640
820
1229
1280
1920
2048
2560
3200
3840
4095
16777215

8.3.4. Fixed-cycle timer start timing

Counting down of the fixed-cycle timer value starts at the rising edge of the SCL signal that occurs when the TE
value is changed from 0 to "1"(after bit "0" is transferred).
SCL
SDA
TIMER
/ INT
64 Hz
TSEL1,0 = 0,1
244.14 s
488.28 s
10.010 ms
20.020 ms
31.250 ms
46.875 ms
50.049 ms
78.125 ms
100.10 ms
156.25 ms
200.20 ms
300.05 ms
312.50 ms
468.75 ms
500.00 ms
625.00 ms
0.7813 s
0.9375 s
0.9998 s
4096 sec.
3 days,49 min.4 sec.
Address 0Dh
TE
FSEL1
FSEL0 TSEL1
A
Source clock
"Second" update
TSEL1,0 = 1,0
15.625 ms
31.25 ms
640.63 ms
1.281 s
2.000 s
3.000 s
3.203 s
5.000 s
6.406 s
10.000 s
12.813 s
19.203 s
20.000 s
30.000 s
32.000 s
40.000 s
50.000 s
60.000 s
63.984 s
194 days
TSEL0
ACK
n n-1 n-2 n-3 , , 2 1 n n-1 n-2
Operation of timer
Page - 18
"Minute" update
TSEL1,0 = 1,1
1 s
2 s
41 s
41 min
82 s
82 min
128 s
128 min
192 s
192 min
205 s
205 min
320 s
320 min
410 s
410 min
640 s
640 min
820 s
820 min
1229 s
1229 min
1280 s
1280 min
1920 s
1920 min
2048 s
2048 min
2560 s
2560 min
3200 s
3200 min
3840 s
3840 min
4095 s
4095 min
32 years
n = Preset Value
ETM60E-02
1 min
2 min

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