Clock Ratios And Operating Frequencies; Ppc60X Originated - Motorola MVME2401-1 Installation And Use Manual

Clock Ratios and Operating Frequencies

Performance is based on the appropriate clock ratio and corresponding
operating frequency:'
Table 3-8. Clock Ratios and Operating Frequencies
Ratio
5:2
3:2
3:1
2:1
1:1

PPC60x Originated

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PPC60x Clock PCI Clock
(MHz)
83
100
100
66
66
Count represents number of PPC60x bus clock cycles.
Assumes write posting FIFO is initially empty.
Does not include time taken to obtain grant for PPC60x bus. The
count starts on the same clock period that TS_ is asserted.
PPC60x bus is idle at the time of the start of the transaction. (i.e., no
pipelining effects).
Cache aligned transfer, not critical word first.
PCI medium responder with no zero states.
One clock request/one clock grant PCI arbitration.
Write posting enabled.
Default FIFO threshold settings
Single beat writes are aligned 32-bit transfer, always executed aws
32-bit PCI.
SDRAM Speed
(MHz) (ns)
33 8
66 8
33 8
33 10
66 10
Block Diagram
3
3-13