Motorola MVME2401-1 Installation And Use Manual page 57

Table 3-4. PCI Originated Bandwidth Matrix
First 2
Cache Lines
Transaction
Clks
64-bit Writes 10
64-bit Reads 16
32-bit Writes 18
32-bit Reads 24
64-bit Writes 10
64-bit Reads 19
32-bit Writes 18
32-bit Reads 28
64-bit Writes 10
64-bit Reads 16
32-bit Writes 18
32-bit Reads 24
64-bit Writes 10
64-bit Reads 18
32-bit Writes 18
32-bit Reads 26
64-bit Writes 10
64-bit Reads 23
32-bit Writes 18
32-bit Reads 31
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First 4
Cache Lines
MBytes MBytes
Clks
sec sec
213 18 237
133 24 178
118 34 125
89 40 107
427 18 474
225 27 316
237 34 251
152 44 194
213 18 237
133 24 178
118 34 125
89 40 107
213 18 237
118 26 164
118 34 125
82 42 102
427 18 474
186 34 251
237 34 251
138 47 182
First 6
Continuous
Cache Lines
MBytes Clks/
Clks
sec Line
26 246 4
32 200 4
50 128 8
56 114 8
26 492 4
37 346 4
50 256 8
60 213 8
26 246 4
32 200 4
50 128 8
56 114 8
26 246 4
34 188 4
50 128 8
58 110 8
30 427 5
46 278 5.5
50 256 8
63 203 8
Block Diagram
3
Clock
Ratio
MBytes
sec
266 5:2
266
133
133
533 3:2
533
267
267
266 3:1
266
133
133
266 2:1
266
133
133
427 1:1
388
267
267
3-9