Hardware Configuration; Figure 4-6. Host Connection Concept - Texas Instruments BQ76952EVM User Manual

BQ76952 Circuit Module Use
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4.8 Hardware Configuration

4.8.1 Configuration Jumpers
Certain features on the BQ76952EVM may be configured by jumpers or shunts on headers. See
details of the header pins. Not all configurations are compatible with all register settings, the user should set pins
appropriately for the register settings planned. For example pins must not be pulled above REG18 when used as
thermistor inputs. Pull up to REG1 is not acceptable when registers configure a pin as a thermistor input.
Multi-function pins must be connected to compatible signal levels before programming registers to
avoid device damage.
The cell simulator headers and I2C configuration are discussed with board connection diagrams.
J6 and J11 select the connection of the DFETOFF and CFETOFF pins. Pins may be pulled low or high to REG1.
J7 selects the connection of TS2. It may be taken to a terminal block for connection of an external wake or
thermistor. It may also be pulled to VSS. The 10k R29 simulates a nominal temperature.
J20 and J21 select the connection of ALERT. It may be connected to the on-board interface for HDQ or pulled up
to REG1.
4.8.2 Unused Components
The EVM contains a number of component patterns which may be useful for evaluation. Unpopulated headers at
the MCU may provide future signal access. Parallel FET configuration is possible by changing the component
population in the FET area. See the FET schematic in
22 BQ76952 Evaluation Module
Install cell
simulator shunts

Figure 4-6. Host Connection Concept

CAUTION
Figure 5-11.
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MCU
Evaluation Board
Add shunts for pull-ups if pull-ups
not provided on MCU board
SLUUC33A – NOVEMBER 2019 – REVISED OCTOBER 2020
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SDA
SCL
Section 5.4 for