rtd FPGA35S6 Series User Manual
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rtd FPGA35S6 Series User Manual

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FPGA35S6046HR
FPGA35S6101HR
FPGA Module
User's Manual
BDM-610010048 Rev. D
RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified

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  • Page 1 FPGA35S6046HR FPGA35S6101HR FPGA Module User’s Manual BDM-610010048 Rev. D RTD Embedded Technologies, Inc. AS9100 and ISO 9001 Certified...
  • Page 2 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com...
  • Page 3 Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.

  • Page 4: Table Of Contents

    JP1: Embedded Programmer Enable JP8: User ID Jumper 4.3.3 Solder Jumper B2: Pull up Voltage Steps for Installing ..................................23 Functional Description Configuration Flash ................................... 24 Oscillator ....................................24 EEPROM ....................................24 | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 5 R_COM3_OUT (Read/Write) 6.2.23 R_COM3_IN (Read) 6.2.24 R_COM4_OUT (Read/Write) 6.2.25 R_COM4_IN (Read) Troubleshooting Additional Information PC/104 Specifications ................................35 PCI and PCI Express Specification ............................35 Serial Port Transceivers ................................35 Limited Warranty | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 6 Table 17: JP8 – User ID Jumper .................................... 22 Table 18: B2 Pull up Voltage ....................................22 Table 19: Transceiver Configuration..................................26 Table 20: Identifying the FPGA35S6 ..................................27 Table 21: FPGA Example Register Map................................. 27 | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 7: Introduction

    Product Overview The FPGA35S6 series of FPGA boards are designed to provide a platform to create any digital I/O that is required for your application. It interfaces with the PCIe bus and features a Xilinx Spartan 6 FPGA with a 27 MHz oscillator and 1Gb of DDR2 SDRAM.
  • Page 8 PCI Express Bus: PCIe/104 Universal Board ▪ Interfaces with Type 1 or Type 2 bus ▪ No re-population Provides 2.5 Gbps in each direction In-band interrupts and messages Message Signaled Interrupt (MSI) support | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 9: Ordering Information

    PCIe/104 Spartan-6 XC6SLX100T User Programmable FPGA Module in IDAN enclosure A Starter Kit is available for any of the options, which includes the appropriate programming cable. Contact RTD Sales for more information. The FPGA35S6 is a general use FPGA module, allowing you to design your own FPGA. It has support for custom oscillator and larger Xilinx Spartan 6 FPGAs.

  • Page 10: Specifications

    = 12mA CN8,CN9 5V Output CN8,CN9 DDR2 Interface Access Rate Mb/s (1): Typical power consumption based on RTD’s FPGA example. Note: (2): Proving by design, not production tested. For additionally electrical characteristic of the Spartan 6 I/O refer to http://www.xilinx.com | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual...

  • Page 11: Board Connection

    Physical Characteristics • Weight: Approximately 63.5 g (0.14 lbs.) • Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W) Figure 1: Board Dimensions | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 12: Connectors And Jumpers

    Connector CN3 provides a connection to the Xilinx JTAG programming header. The pin assignment for CN3 is shown below. This connector header mates with the Xilinx OEM programming cable. Table 4: CN3 Programming Header 3.3V VRef | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 13: Cn8: High Speed Digital I/O Connector

    Port2_p[4] Port2_n[5] Port2_p[5] Port2_n[6] Port2_p[6] Port2_n[7] Port2_p[7] Port2_n[8] Port2_p[8] Port2_n[9] Port2_p[9] Port2_n[10] Port2_p[10] Port2_n[11] Port2_p[11] Port2_n[12] Port2_p[12] Port2_n[13] Port2_p[13] Port2_n[14] Port2_p[14] Port2_n[15] Port2_p[15] Port2_n[16] Port2_p[16] Port2_n[17] Port2_p[17] Port2_n[18] Port2_p[18] Port2_n[19] Port2_p[19] | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 14: Cn9: Digital I/O Connector

    These signals are attached to Bank 2 of the FPGA, and should be configured as LVCMOS33. Table 7: CN10, CN11, CN12, CN13 I/O Pin Assignments com?_dsr (RX) com?_dcd (RX) com?_rtd (TX) com?_rxd (RX) com?_cts (RX) com?_txd (TX) com?_ri (RX) com?_dtr (TX) | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 15: Bus Connectors

    Solder jumper B2 is used to set the pull up voltage for JP4, JP5 and JP6. Table 11: B2 Pull up Voltage Setting Description Sets Pull up voltage to 3.3V Sets Pull up voltage to 5V | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 16: Steps For Installing

    10. Attach any necessary cables to the PC/104 stack. 11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 3: Example 104™Stack | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 17: Idan Connections

    Weight: Approximately 0.42 Kg (0.92 lbs.) • Dimensions: 152mm L x 130mm W x 34mm H (5.983" L x 5.117" W x 1.339" H) 1.339” [34mm] Front 5.983” [152mm] 5.117” [130mm] Back Figure 4: IDAN Dimensions | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 18: Connectors And Jumpers

    Connector P3 provides 24 digital I/O lines, along with a +5V pin and ground pins. All I/O have pull up/pull down resistors that are controlled by jumper options, also shown in the table. These signals are 5V tolerant. The signal names reflect the signal names I n the Xilinx UCF file with the device pin out. | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 19: Table 13: P3 Pin Assignments

    Jmpr C9 Pin port1_p[0] port1_n[0] port1_p[1] port1_n[1] port1_p[2] port1_n[2] port1_p[3] port1_n[3] port1_p[4] port1_n[4] port1_p[5] port1_n[5] port1_p[6] port1_n[6] port1_p[7] port1_n[7] port1_p[8] port1_n[8] port1_p[9] port1_n[9] port1_p[10] port1_n[10] port1_p[11] port1_n[11] Reserved jtag_vref CN3.2 CN3.3 | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 20: P4: High Speed Digital I/O Connector

    Signal C8 Pin Port2_p[0] Port2_n[0] Port2_p[1] Port2_n[1] Port2_p[2] Port2_n[2] Port2_p[3] Port2_n[3] Port2_p[4] Port2_n[4] Port2_p[5] Port2_n[5] Port2_p[6] Port2_n[6] Port2_p[7] Port2_n[7] Port2_p[8] Port2_n[8] Port2_p[9] Port2_n[9] Port2_p[10] Port2_n[10] Port2_p[11] Port2_n[11] Port2_p[12] Port2_n[12] Port2_p[13] Port2_n[13] | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 21 Row 2 Row 3 Signal C8 Pin Port2_p[14] Port2_n[14] Port2_p[15] Port2_n[15] Port2_p[16] Port2_n[16] Port2_p[17] Port2_n[17] Port2_p[18] Port2_n[18] Port2_p[19] Port2_n[19] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 22: Bus Connectors

    Solder jumper B2 is used to set the pull up voltage for JP4, JP5 and JP6. Table 18: B2 Pull up Voltage Setting Description Sets Pull up voltage to 3.3V Sets Pull up voltage to 5V | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 23: Steps For Installing

    10. Attach any necessary cables to the IDAN system. 11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 5: Example IDAN System | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 24: Functional Description

    The FPGA35S6 features a 1Gb DDR2 SRAM, MT47H64M16HR 25E. This is interface to the Spartan 6 FPGA using Xilinx Memory Interface Generators (MIG) core. The example FPGA code has demonstrated how to use this core in a FPGA design. | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 25: Figure 7: Cn9 Digital I/O Circuitry

    The transceivers are highly configurable from the FPGA fabric. The Figure below shows the connections between the FPGA signals, the Exar SP338 transceiver, and the connector. Figure 8: Serial Port Transceiver | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.

  • Page 26: Table 19: Transceiver Configuration

    JP1 is installed. The embedded programmer has a user string of “RTD” followed by the serial number of the board. This can be used to differentiate the programmers if there are multiple boards in the system.

  • Page 27: Table 20: Identifying The Fpga35S6

    0x78 R_COM2_OUT 0x7C R_COM2_IN 0x80 R_COM3_OUT 0x84 R_COM3_IN 0x88 R_COM4_OUT 0x8C R_COM4_IN 6.2.1 R_ID (R This is a register that identifies the board. 0x12345678 is the identification of the example code | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 28 This is the input register for the port2 high, port2_[16]…port2_[19]. This reads the current value the I/O. 6.2.12 R_PORT2H_OUT (W RITE This is the output register for the port2 high, port2_[16]…port2_[19]. The value to be output, direction must be set to output. | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 29 A read is performed by writing address to R_DDR_ADDR. 6.2.15 R_DDR_WR_DATA (R RITE Writes data in registry to location R_DDR_ADDR of the DDR2 SRAM 6.2.16 R_DDR_ADDR (R RITE Address pointer of the DDR2 SRAM. | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 30 This register sets the configuration and outputs of CN10 RS-232/422/485 transceivers. B0: com1_txd B1: com1_rts B2: com1_dtr B8: com1_enable B9: com1_mode0 B10: com1_mode1 B11: com1_mode2 B12: com1_dir1 B13: com1_dir2 B14: com1_slew B15: com1_term | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 31 B11: com2_mode2 B12: com2_dir1 B13: com2_dir2 B14: com2_slew B15: com2_term 6.2.21 R_COM2_IN (R This register reads the inputs of CN11 RS-232/422/485 transceivers. B0: com2_rxd B1: com2_cts B2: com2_dsr B3: com2_dcd B7: com2_ri | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 32 B11: com3_mode2 B12: com3_dir1 B13: com3_dir2 B14: com3_slew B15: com3_term 6.2.23 R_COM3_IN (R This register reads the inputs of CN12 RS-232/422/485 transceivers. B0: com3_rxd B1: com3_cts B2: com3_dsr B3: com3_dcd B7: com3_ri | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 33 B11: com4_mode2 B12: com4_dir1 B13: com4_dir2 B14: com4_slew B15: com4_term 6.2.25 R_COM4_IN (R This register reads the inputs of CN13 RS-232/422/485 transceivers. B0: com4_rxd B1: com4_cts B2: com4_dsr B3: com4_dcd B7: com4_ri | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 34 If problems persist, or you have questions about configuring this product, contact RTD Embedded Technologies via the following methods: Phone: +1-814-234-8087 E-Mail: techsupport@rtd.com Be sure to check the RTD web site (http://www.rtd.com) frequently for product updates, including newer versions of the board manual and application software. | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 35 A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group: www.pcisig.com Serial Port Transceivers Detailed information on the Exar SP338 serial port transceivers is available on the Exar website: www.exar.com/connectivity/transceiver/multiprotocol/sp338 | www.rtd.com FPGA35S6046/FPGA35S6101 User’s Manual RTD Embedded Technologies, Inc.
  • Page 36 During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded Technologies.
  • Page 37 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com Copyright 2021 by RTD Embedded Technologies, Inc. All rights reserved.

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