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rtd DM35820HR User Manual

Versatile high speed digital i/o
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DM35820HR
DM9820HR
DM8820HR
DM7820HR
Versatile High Speed Digital I/O
User's Manual
BDM-610010036 Rev. E
RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified

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Summary of Contents for rtd DM35820HR

  • Page 1 DM35820HR DM9820HR DM8820HR DM7820HR Versatile High Speed Digital I/O User’s Manual BDM-610010036 Rev. E RTD Embedded Technologies, Inc. AS9100 and ISO 9001 Certified...
  • Page 2 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com...
  • Page 3 Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.

  • Page 4: Table Of Contents

    Connectors and Jumpers ................................12 3.3.1 DM7820HR and DM8820HR ..........................12 3.3.1 DM35820HR and DM9820HR ........................... 13 3.3.2 External I/O Connectors............................. 13 Connector CN10 – Digital Input / Output ........................13 Connector CN11 – Digital Input / Output ........................14 3.3.3...
  • Page 5 Control Word and Count Value Program ........................61 Mode definition ................................62 Reading Counter Values .............................. 66 PLX Registers ................................... 70 6.4.1 Memory Map Overview ............................70 6.4.2 DMA Register Description ..........................70 DMAMODEn ................................. 70 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 6 INTCSR ..................................76 Troubleshooting Additional Information PC/104 Specifications ................................80 PCI and PCI Express Specification ............................80 PLX PCI9056 .................................... 80 82C54 Timer/Counter Programming............................80 Interrupt Programming ................................80 Limited Warranty | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 7 Table 14: Mode M[2:0]: Operation waveform mode setting............................ 61 Table 15: BCD: Operation count mode setting ............................... 62 Table 16: PLX DMx820HR Memory Map ................................70 Table 17: DMA Threshold Nybble Values................................75 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 8: Introduction

    Can be started and stopped by an interrupt or another clock Continuous or One-Shot Operation Can be cascaded • 82C54 Timer/Counters Six Timer/Counter Channels Fully programmable Input clock and gate driven from internal or external source 10 MHz maximum input | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 9: Ordering Information

    The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus High Reliability Intelligent Data Acquisition Node.

  • Page 10: Specifications

    DIO pins may be driven to - 2.0V or + 7.0V provided these voltages last no longer than 11ns with a forcing current no greater than 100mA. Inputs are terminated with 33Ω resistors and protection diodes. DIO inputs should not be tied to voltages when the board is not powered. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 11: Board Connection

    Physical Characteristics • Weight: Approximately 100 g (0.22 lbs.) • Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W) Figure 1: Board Dimensions (DM9820HR shown) | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 12: Connectors And Jumpers

    PC/104-Plus Connector PCI Master Control Force Three Master CN11 CN10 Digital I/O Digital I/O PC/104 Connector Slot Selection (DM7820 Only) Figure 2: DM7820HR and DM8820HR Connectors and Jumpers | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 13: Dm35820Hr And Dm9820Hr

    Connector CN10 provides 24 digital input/output lines, along with a +5V pin and ground pins. The pin assignments for CN10 are shown in Table 1. Table 4: CN10 Pin Assignments Signal Signal P2[7] Strobe2 P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 14: Connector Cn11 - Digital Input / Output

    P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] +5V, 2A max See Table 10 on page 43Table 10 and Table 11 on page 55 for peripheral pin assignments. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 15: Bus Connectors

    Slot 2 If JP2 Slot 3 If JP2 Jumper JP2 – Bus Master Control Install JP2 to enable bus mastering when in Slot 2 or Slot 3 in three bus master mode. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 16: Pc/104 Isa Connectors (Dm7820Hr Only)

    The PC/104 connectors carry the signals of the PC/104-Plus ISA bus. Refer to PC/104-Plus Specification Revision 1.0 for the pinout of this connector. This is a pass-through connector. The DM7820HR connects to the power and ground pins only, and does not use any of the signals. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 17: Steps For Installing

    14. Attach any necessary cables to the PC/104 stack. 15. Re-connect the power cord and apply power to the stack. 16. Boot the system and verify that all of the hardware is working properly. Figure 4: Example 104™Stack | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 18: Idan Connections

    Dimensions: 151.972 mm L x 129.978 mm W x 33.934 mm H (5.983 in L x 5.117 in W x 1.339 in H) 1.339” 5.983” 5.117” 62 pin High Density “D”: female Module Part #: Adam Tech HDT62SD Mating Part #: Adam Tech HDT62PD Figure 5: IDAN Dimensions | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 19: 62D - Connectors

    P1.7 P0.6 P1.6 P0.5 P1.5 P0.4 P1.4 P0.3 P1.3 P0.2 P1.2 P0.1 P1.1 P0.0 P1.0 5 VOLTS 5 VOLTS * Pins 51 to 62 of the IDAN connector are not connected. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 20: 68S - Physical Characteristics

    Dimensions: 151.972 mm L x 129.978 mm W x 16.993 mm H (5.983 in L x 5.117 in W x 0.669 in H) Front 1.339” 5.983” 5.117” 68 pin Female Module Part #: Amphenol 5390378-7 Mating Part #: Amphenol 786090-7 Back Figure 6: IDAN Dimensions | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 21: 68S - Connectors

    P1.7 P0.6 P1.6 P0.5 P1.5 P0.4 P1.4 P0.3 P1.3 P0.2 P1.2 P0.1 P1.1 P0.0 P1.0 5 VOLTS 5 VOLTS * Pins 51 to 68 of the IDAN connector are not connected. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 22: Bus Connectors

    The PC/104 connectors carry the signals of the PC/104-Plus ISA bus. Refer to PC/104-Plus Specification Revision 1.0 for the pinout of this connector. This is a pass-through connector. The DM7820HR connects to the power and ground pins only, and does not use any of the signals. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 23: Steps For Installing

    10. Attach any necessary cables to the IDAN system. 11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 7: Example IDAN System | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 24: Functional Description

    Below is a block diagram of the DMx820HR. Primary board components are in bold, while external I/O connections and jumpers are italicized. 48 Digital I/O SDRAM Digital I/O 25 MHz Clock FPGA 82C54 Timer/Counters PCI9056 or PEX8311 PCI or PCIe Bus Figure 8: DMx820HR Block Diagram | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 25: Internal Architecture

    3.75 M-words per second. When a FIFO is looped, the data must be read and written. The table below shows examples of configurations and their maximum data rate. Note that for uniform sampling (samples are taken at uniform sampling intervals) the data rate must be an integer divisor of the 25 MHz overall clock. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 26: Board Interrupts

    Set to event desired During the Interrupt Service Routine… Change FIFO output clock to PCI Read Start DMA transfers Prog Clock 0 - Sample Input Clock Period = sample period Master Clock = any | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 27 Data In = any Data in clock = Prog Clock 0 Data out clock = Prog Clock 2 (before AdvInt0) Data out clock = PCI Read (after Adv Int0) DReq0 = Read Ready | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 28: Board Operation And Programming

    Generally, the registers are 16 bits wide. However, they can be read and written as 8, 16, or 32 bits. (There are a few exceptions as noted in the memory map.) 6.2.1 EMORY VERVIEW Table 9 shows the memory map of the DMx820HR digital I/O registers. These are found at the offset from BAR2. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 29: Table 9: Dmx820Hr Memory Map

    Port0[3]_Periph_Select b[5:4] Port0[2]_Periph_Select b[3:2] Port0[2]_Periph_Select b[1:0] Port0[0]_Periph_Select PORT0_PERIPH_SEL_H b[15:14] Port0[15]_Periph_Select 0x0062 b[13:12] Port0[14]_Periph_Select b[11:10] Port0[13]_Periph_Select b[9:8] Port0[12]_Periph_Select b[7:6] Port0[11]_Periph_Select b[5:4] Port0[10]_Periph_Select b[3:2] Port0[9]_Periph_Select b[1:0] Port0[8]_Periph_Select 0x0064 PORT1_PERIPH_SEL_L 0x0066 PORT1_PERIPH_SEL_H 0x0068 PORT2_PERIPH_SEL_L | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 30 30 = PCI Read 29-16 = Interrupts[13-0] 15-0 = Clock_Bus [15-0] FIFO0_OUT_CLK b[15:5] Reserved 0x00C6 b[4:0] Input Clock Select 31 = PCI Write 30 = PCI Read 29-16 = Interrupts[13-0] 15-0 = Clock_Bus [15-0] | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 31 = Not Full = Write Request = Not Empty = Read Request b[7:4] Reserved b[3:0] Input Data Select = Incremental Encoder B1 = Incremental Encoder B0 = Port 1 = PCI Data | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 32 Reserved b[12:8] Stop Clock 31-16 = Interrupt_Bus[15-0] 15-1 = Clock_Bus [15-1] = No Stop Clock b[7:5] Reserved b[4:0] Start Trigger 31-16 = Interrupt_Bus[15-0] 15-1 = Clock_Bus [15-1] = Start Immediate | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 33 = No Stop Clock b[7:5] Reserved b[4:0] Start Trigger 31-16 = Interrupt_Bus[15-0] 15-1 = Clock_Bus [15-1] = Start Immediate 0x01C8 PRGCLK3_PERIOD b[15:0] Period of Clock Output frequency is: Master Clock Frequency  PERIOD | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 34 [15:0] Port 0 Compare – Value used for interrupt on match. 0x0250 ADVINT1_PORT0_CMP b [15:0] Port 1 Compare – Value used for interrupt on match. ADVINT1_PORT1_CMP 0x0252 b [15:0] Port 2 Compare – Value used for interrupt on match. 0x0254 ADVINT1_PORT2_CMP | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 35 Interrupt Enable – ‘1’ = Interrupt is enabled, ‘0’ = disabled b[3:0] Interrupt source are: Encoder B Negative Rollover Encoder B Positive Rollover Encoder A Negative Rollover Encoder A Positive Rollover INCENC1_CLOCK b[3:0] Master Clock Source 0x02C4 15-0 = Clock_Bus [15-0] | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 36 0x0346 Reserved PWM1_PERIOD b[15:0] Period of PWM Cycle is: 0x0348 Width Clock Frequency  PWMx PERIOD Reserved 0x034A- 0x034E 0x0350 PWM1_WIDTHA b[15:0] Width of output A pulse in Period Clock cycles | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 37: Detailed Register Description

    0x10 = Standard FPGA VERSION FPGA Version Identifier SVN_VERSION This register provides the source code revision control version. It is updated every time the FPGA is compiled. VERSION R,+xxxx xxxx xxxx xxxx | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 38: Board_Reset

    AdvInt1 Interrupt from Advance Interrupt block at 0x0240 ’0’ = Interrupt Disabled ’1’ = Interrupt Enabled 82C54 Interrupt 82C54 Timer/Counter block at 0x0080 ’0’ = Interrupt Disabled ’1’ = Interrupt Enabled | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 39: Int_Status

    ’1’ = Interrupt has occurred. Write ‘1’ to clear. IncEnc0 Interrupt from Incremental Encoder block at 0x0280 ’0’ = Interrupt has not occurred ’1’ = Interrupt has occurred. Write ‘1’ to clear. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 40: Standard I/O

    A diagram of the standard I/O is shown in Figure 11. Each digital I/O pin can be an input, output, or peripheral output. The peripheral outputs are the Pulse Width Modulators, FIFO, Timer/Counters, etc. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 41: Portx_Output

    Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 Field Description Px_[15:0] Current pin value ’0’ = Pin is Low ’1’ = Pin is High | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 42: Portx_Tristate

    This register selects the peripheral for Port 0, Port 1, or Port 2 when it is a peripheral output (i.e. PORTx_MODE[] = ‘1’). This register selects the peripheral for bits [15:8]. Px_15 Px_14 Px_13 Px_12 RW,+00 RW,+00 RW,+00 RW,+00 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 43: Strobe_Status

    FIFO1_Out[14] Port2[15] PWM1_D- Strobe2_neg FIFO0_Out[15] FIFO1_Out[15] STROBE_STATUS This register can be used to check the status of the strobe signals, as well as configure the strobes as outputs. Reserved STR2_TRI STR1_TRI | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 44: 82C54 Timer Counter Control

    INT_ENA[5:0] R,+00 RC,+0 R,+00 RW,+0 Field Description Interrupt Status – ‘1’ = Interrupt condition has occurred. INT_STAT[5:0] Write ‘1’ to clear. Interrupts are asserted on the positive edge of the clock. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 45: Tc_Xy_Control

    10 Prog. Clock 2 Prog. Clock 1 Prog. Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC B0 82C54 TC A2 82C54 TC A1 82C54 TC A0 Reserved 5 MHz | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 46: Fifo Channel N

    31 PCI Write to FIFOn_RW_PORT 30 PCI Read from FIFOn_RW_PORT 29 Prog. Clock 3 Interrupt 28 Prog. Clock 2 Interrupt 27 Prog. Clock 1 Interrupt 26 Prog. Clock 0 Interrupt | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 47: Fifon_Out_Clk

    17 Advanced Interrupt 1 Interrupt 16 Advanced Interrupt 0 Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog. Clock 3 10 Prog. Clock 2 Prog. Clock 1 Prog. Clock 0 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 48: Fifon_In_Data_Dreq

    128 words, which provides for efficient communication over the PCI bus, and robustly guards against over-run and under-run conditions. However, it does not allow for the FIFO to be completely filled of emptied. Reserved WRITE_REQ READ_REQ Reserved R,+0 R,+x R,+0 R,+0 RW,+0 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 49: Fifon_Rw_Port

    PROGCLKn_ID ID register to identify a Programmable Clock Block. ID_Register Field Description ID_Register15:0] Value of 0x1000 indicates Programmable Clock PROGCLKn_MODE Selects the mode that the Programmable Clock. Reserved MODE RW,+0 RW,+00 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 50: Prgclkn_Clk

    Stop Trigger. After the clock has stopped, it must be disabled and re-enabled for it to start again if in Continuous mode. The clock should be disabled before modifying this register. Reserved STOP _TRG[4:0] Reserved START _TRG[4:0] R,+0 RW,+0 R,+0 RW,+0 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 51 10 Prog. Clock 2 Prog. Clock 1 Prog. Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC B0 82C54 TC A2 82C54 TC A1 82C54 TC A0 Reserved Start Immediate | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 52: Progclkn_Period

    The current value of the clock counter. COUNT[15:0] RW,+0 Field Description The current value of the clock counter. This starts at a value of COUNT[15:0] PERIOD, and counts down to 0. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 53: Advanced Interrupt N

    25 MHz clock always serves as the sampling clock. Reserved CLOCK_SEL[3:0] R,+0 RW,+0 Field Description CLOCK_SEL[3:0] Selects the master clock. Value definitions are: 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 54: Advintn_Portx_Mask

    The Capture register latches the input ports when an interrupt is generated. All values are latched, regardless of the Mask register, or if the port is an input or output. Px_15 Px_14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 R,+0 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 55: Dual Incremental Encoder N

    Port0[1] Port0[9] Port1[1] Port1[9] Port0[2] Port0[10] Port1[2] Port1[10] Port0[3] Port0[11] Port1[3] Port1[11] Index + Port0[4] Port0[12] Port1[4] Port1[12] Index - Port0[5] Port0[13] Port1[5] Port1[13] INCENCn_ID ID register to identify this block. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 56: Incencn_Int

    ’0’ = Interrupt is disabled ’1’ = Interrupt is enabled. ENA_A_POS Enables interrupt when channel A transitions from 0xFFFF to 0x0000. (Positive rollover) ’0’ = Interrupt is disabled ’1’ = Interrupt is enabled. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 57: Incencn_Clk

    ’0’ = Transition will change counter ’1’ = Transition will not change counter. The bit assignments for the transitions are: Previous Current Direction State [B:A] State [B:A] Down Down Down Down | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 58: Incencn_Valuey

    This register can only be written to when INCENCx_MODE[ENA] = 0. This allows the counter to be pre-loaded with a known position value. VALUE[15:0] R(W),+0 Field Description VALUE[15:0] The current value of this incremental encoder channel. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 59: Quad Pulse Width Modulator N

    This register is used to enable and disable the Pulse Width Modulator. When disabled, all non-inverted outputs are low, and all inverted outputs are high, and interrupts are not generated. Reserved R,+0 RW,+0 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 60: Pwmn_Clk

    Note that with PWMn_PERIOD set to the maximum value, and the period clock and width clock set to the same source, a 100% duty cycle is not possible. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 61: 82C54 Timer Counter N

    Set Contents Min Count Max Count Value Value Mode 0 (Interrupt on Terminal Count) Mode 1 (Programmable One-Shot) Mode 2 (Rate Generator) Mode 3 (Square Wave Generator) Mode 4 (Software Triggered Strobe) | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 62: Mode Definition

    Gate function: The gate signal setting to “L” level after the gate trigger does not affect the output. When it is set to “H” level again from “L” level, gate retriggering occurs, the CR count value is loaded again, and counting continues. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 63 The clock pulse does not decrement the initial count value. If the initial count value is N, the strobe is not output unless N+1 clock pulses are input after the initial count value is written, | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 64 CE at the falling edge of the next clock pulse, and counting continues using the new count value. The various roles of the gate input signals in the above modes are summarized in the following table. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 65 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 66: Reading Counter Values

    Count value (LSB) reading New count value (LSB) writing Count value (MSB) reading New count value (MSB) writing An example of a counter latching program is given below. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 67 The status of a certain counter is read when the counter is read. The counter status format is as follows: Bits D5 to D0 indicate the mode programmed by the most recently written control word. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 68 STATUS bits, to 00. This is functionally the same as writing two separate read back commands at the same time. If counter/status latching is carried out multiple times before each reading, other than the first one is ignored here again. The example is shown below. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 69 If both the count and status are latched, the status latched in the first counter read operation is read. The order of count latching and status latching is irrelevant. The count(s) of the next one or two reading operations is or are read. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 70: Plx Registers

    00b = 8 bit 01b = 16 bit 10b or 11b = 32 bit Internal Wait State Counter (Address-to-Data; Data-to- Data; 0 to 15 Wait States). | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 71 Scatter/Gather descriptor when the corresponding DMA transfer is complete. Interrupt Select. Writing 1 routes the interrupt to the PCI interrupt (INTA#). Writing 0 routes the interrupt to the Local interrupt output (LINTo#). | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 72: Dmapadrn

    Description Read Write Value Value after to Use Reset 31:0 DMA Channel Local Address. Indicates from where in Local Memory space DMA transfers (reads or writes) start. DMASIZn DMA Transfer Size | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 73: Dmaprn

    DMA transfer, and if in the process of transferring data, suspends the transfer (pause). Start. Writing 1 causes the channel to start Yes/ transferring data if the channel is enabled. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 74: Dmaarb

    (C0LPAF). Number of full (Lword x 2) entries (plus 1, times 2) in the FIFO before requesting the PCI Bus for writes. Nybble values 0h through Eh may be used. (Refer to Table 17.) | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 75: Table 17: Dma Threshold Nybble Values

    Setting 4 Lwords 24 Lwords 44 Lwords 8 Lwords 28 Lwords 48 Lwords 12 Lwords 32 Lwords 52 Lwords 16 Lwords 38 Lwords 58 Lwords 20 Lwords 40 Lwords 60 Lwords | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 76: Dmadan

    PCI 9056 has detected a Local data parity check error, even if Parity Check Error is disabled (INTCSR[6]=0). Writing 1 clears this bit to 0. PCI Interrupt Enable. Writing 1 enables PCI interrupts (INTA#). | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 77 The BIST interrupt is enabled by writing 1 to the PCI Built-In Self-Test Interrupt Enable bit (PCIBISTR[6]=1). Clearing the Enable bit (PCIBISTR[6]=0) also clears the interrupt. Note: Refer to the PCIBISTR register for a description of the self-test. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.
  • Page 78 MBOX2. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). Reading 1 indicates that the PCI Bus wrote data to MBOX3. Enabled only if the Mailbox Interrupt Enable bit is set (INTCSR[3]=1). | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 79: Troubleshooting

    If problems persist, or you have questions about configuring this product, contact RTD Embedded Technologies via the following methods: Phone: +1-814-234-8087 E-Mail: techsupport@rtd.com Be sure to check the RTD web site (http://www.rtd.com) frequently for product updates, including newer versions of the board manual and application software. | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 80: Additional Information

    For more information about programming the MSM82C54 Timer/Counter Chips, contact Oki Semiconductor at: www2.okisemi.com Interrupt Programming For more information about interrupts and writing interrupt service routines, refer to the following book: Interrupt-Driven PC System Design by Joseph McGivern ISBN: 0929392507 | www.rtd.com DMx820 User’s Manual RTD Embedded Technologies, Inc.

  • Page 81: Limited Warranty

    During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded Technologies.
  • Page 82 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com Copyright 2018 by RTD Embedded Technologies, Inc. All rights reserved.

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