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rtd DM34216HR User Manual

1-25mhz a/d digitizer
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DM34216HR
1-25MHz A/D Digitizer
User's Manual
BDM-610010056 Rev A
RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified

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  • Page 1 DM34216HR 1-25MHz A/D Digitizer User’s Manual BDM-610010056 Rev A RTD Embedded Technologies, Inc. AS9100 and ISO 9001 Certified...
  • Page 2 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 3 Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not by persons qualified to service electronic equipment.

  • Page 4: Table Of Contents

    Capture Window ..................................26 Advanced Digital I/O ................................. 26 5.6.1 Quad Pulse Width Modulator 5.6.2 Incremental Encoder 5.6.3 External Clocking Temperature Sensor ................................. 29 Analog input ....................................29 DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 5 INT_STAT (Read/Clear) 6.4.13 CLK_BUSn 6.4.14 AD_CONFIG (Maskable Read/Write) 6.4.15 FRONT_END_CONFIG (Maskable Read/Write) 6.4.16 FIFO_DATA_CNT (Read) 6.4.17 MAX_FIFO_SIZE (Read) 6.4.18 FILTER (Read/Write) 6.4.19 INT_STAT(Read/Clear) 6.4.20 INT_ENA (Read/Write) 6.4.21 THRESH_LOW (Read/Write) DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 6 SAMPLE_CNT (Read Only) 6.2.11 INT_ENA (Maskable Read/Write) 6.2.12 INT_STAT (Read/Clear) 6.2.13 CLK_BUSn 6.2.14 MODE_CONFIG (MASKABLE READ/WRITE) 6.2.15 FIFO_DATA_CNT (Read) 6.2.16 MAX_FIFO_SIZE (Read) 6.2.17 THRESH_LOW (Read/Write) 6.2.18 THRESH_HIGH (Read/Write) DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 7 COUNT (Read Only) 6.8.9 INT_ENA (Maskable Read/Write) 6.8.10 INT_STAT (Read/Clear) 6.8.11 CLK_BUSn 6.8.12 MODE_CONFIG (MASKABLE READ/WRITE) 6.8.13 CHn_FIFO_DATA_CNT (Read) 6.8.14 CHn_MAX_FIFO_SIZE (Read) 6.8.15 INTERVAL_CLK_DIV (Read/Write) 6.8.16 LAST_INTERVAL_COUNT (Read-Only) DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 8 6.8.17 CHn_FIFO_ACCESS (Read/Write) Troubleshooting Additional Information PC/104 Specifications ................................74 PCI and PCI Express Specification ............................74 Limited Warranty viii DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 9 Figure 5: Example 104™Stack ....................................19 Figure 6: IDAN Dimensions ....................................20 Figure 7: Example IDAN System .................................... 23 Figure 8: DM34216HR Block Diagram ................................... 24 Figure 9: Incremental Encoder Signals................................... 27 Figure 10: Analog Front End ....................................30 Figure 11:High Impedance Bipolar Example ................................31 Figure 12:High Impedance Unipolar Example ................................

  • Page 10: Introduction

    1 Introduction Product Overview The DM34216HR dataModule is a rugged high-speed data acquisition (DAQ) module in the PCIe/104 format which boasts four 16-bit 25 MHz A/D converters. This module provides 4 single-ended analog input channels with software-selectable input ranges and input impedances. Each input channel has a dedicated ADC, permitting simultaneous sampling of the inputs.

  • Page 11: Ordering Information

    If you are having problems with your system, please try the steps in the Troubleshooting section of this manual on page 57. For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the following methods: Phone: 1-814-234-8087 Monday through Friday, 8:00am to 5:00pm (EST).

  • Page 12: Specifications

    Input Frequency Digital I/O (LVTTL) Input High Voltage Input Low Voltage -0.5 Output Low Voltage =-12mA Output High Voltage = -12mA 5V Output SyncBus (LVDS) Differential Input Voltage DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 13: Functional Characteristics

    In Figure 1, a coherent 250kHz sine wave signal was attached to input Channel 0-3 in the +/-2.5V, 50Ω mode. The FFT was generated using 500000 samples. Figure 1: Gain of 1 FFT DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 14: Figure 2: Gain Of 6 Fft

    In Figure 2, a coherent 250kHz sine wave signal was attached to input Channel 0-3 in the +/-0.4167V, 50Ω mode. The FFT was generated using 500000 samples. Figure 2: Gain of 6 FFT DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 15: Board Connection

    When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware. Physical Characteristics STEP model is available upon request; contact RTD Tech Support for more information. • Weight: Approximately 99.8 g (0.22 lbs) with heatsink •...

  • Page 16: Connectors And Jumpers

    PC/104 Specifications on page 58) The DM34216HR is a Type 2 board, and can only connect to either Type 2 PCIe/104 connector. CN16(Top) & CN17(Bottom): Two Bank Connector The Two Bank connector is a high-speed board to board interconnect. Currently the only feature the two bank provides is an independent SyncBus connection.

  • Page 17: External I/O Connectors

    The SyncBus Connector is a 2 x 8, 0.1” spacing right-angle connector. The pin assignments are shown in Table below. A typical mating connector is a FCI 65043-029LF. Pin 1 is indicated by a square solder pad. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 18: Jumpers

    A red LED means that there was an issue the clock generator. Try performing a global board reset (GBC_BRD_RST). If this doesn’t fix the issue, the module will need to be power cycled. ADCn Enable LED This LED is green when a ADC channel is enabled. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 19: Steps For Installing

    11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 5: Example 104™Stack DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 20: Idan Connections

    • Dimensions: 152 mm L x 130 mm W x 24.5 mm H (5.98 in L x 5.12 in W x 0.97 in H) Figure 6: IDAN Dimensions DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 21: Connectors

    Example Mating Connector: TYCO 1658608-1 Table 8: IDAN- DM34216 37-Pin High Density "D" Connector DM34216 Pin # IDAN Pin# Signal DIO0.0 DIO0.2 DIO0.4 DIO0.6 DIO0.8 DIO0.10 DIO0.12 DIO0.14 DIO0.16 DIO0.18 DIO0.20 DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 22: Bus Connectors

    The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express Specification. (See PC/104 Specifications on page 58) The DM34216HR is a Type 2 board, and can only connect to either Type 2 PCIe/104 connector. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc.

  • Page 23: Steps For Installing

    11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 7: Example IDAN System DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 24: Functional Description

    Functional Description Block Diagram The Figure below shows the functional block diagram of the DM34216HR. The various parts of the block diagram are discussed in the following sections. Gain PCIe x4 Channel 0 Impendence Input control Offset Control Logic and DMA...

  • Page 25: Syncbus

    5.4.1 LOCK ENERATOR The DM34216HR provides a method to synchronize the clock generator on multiple DM34216HR modules using the syncbus. This allows the ADC on multiple modules to be synchronize within one System Clock cycle. This process should be performed once all ADC frequencies have been set.

  • Page 26: Capture Window

    32-bits. Advanced Interrupts The DM34216HR has an advanced interrupt block that can generate an interrupt on a match, event or strobe. The interrupts are across all 32- digital input of the function block. The bits can be individually selected.

  • Page 27: Incremental Encoder

    NCREMENTAL NCODER The DM34216HR features a 32-bit incremental encoder functional block with DMA. An Incremental Encoder is used to detect the relative position of a shaft or linear actuator. A typical implementation is a slotted wheel with two optical sensors positioned such that when one sensor is positioned over a slot, the other is positioned between slots. The output of the optical sensors is shown in Figure 9, with one sensor named “A,”...

  • Page 28: External Clocking

    LOCKING The DM34216HR features an external clocking function block. This feature allows the user to input a clock to drive a CLK_BUSn signal or output a CLK_BUSn signal. The CLK_SRCn are used to drive the CLK_BUSn signal which are part of the most FPGA function blocks. The CLK_BUSn signals are used as either sample clocks for function blocks or triggers for starting and stopping them.

  • Page 29: Temperature Sensor

    Each ADC converter supports a 1023 sample FIFO for DMA. Each sample packed into a 32-bit word. Full-Scale Input Range The DM34216HR has a programmable gain input per channel. This gain can be programed for 0.5, 0.75, 1, 1.5, 2, 3, 4, 6 to achieve input ranges ±5V, ±3.3V, ±2.5V, ±1.667V, ±1.25V, ±0.833V, ±0.625V, ±0.416V.

  • Page 30: Figure 10: Analog Front End

    IMPLIFIED BLOCK DIAGRAM OF ANALOG INPUT The following figure shows the front end circuit for the DM34216HR. It also shows the names of the FPGA registers in bold and the different ways the front-end can be configured for different modes of operation.

  • Page 31: Figure 11:High Impedance Bipolar Example

    3.3V Analog OpAmp Input 1.6V CHn_Front_End_Config [IMPED] = 0 To Diff Gain Control Diff Amp 1.667V CHn_Front_End_Config [GAIN] = 1 +1.667V OpAmp -1.667V Figure 12:High Impedance Unipolar Example DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 32: Table 11: Function Block Mapping

    ‘0’. This is typically used for interrupt status registers. • Read Only: This register can only be read. NOTE: Writing to Read-Only registers may have unexpected results. Function Block Mapping Below is the Function Block slot mapping for the DM34216HR. Table 11: Function Block Mapping Slot Description Connector...

  • Page 33: Table 12: Base Functional Block

    Write a value of 0xAA to this register to reset the board. 6.1.4 GBC_PDP (R This register contains the PDP number for this board in decimal. 6.1.5 GBC_BUILD (R Unique 32-bit build number for every FPGA build. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 34: Gbc_Eoi (Read/Clear)

    _DMA (R FFSET This is the offset from the beginning of the Functional Block section (typically the offset in BAR2) that the Functional Block DMA Registers resides in. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 35: Table 13: Dma Registers

    Used_Desc bit (below) if the next buffer has the Used bit set. However, it will not generate an interrupt, and will not PAUSE the DMA engine. Examples are continuous output from a DAC, or very large Pre-trigger buffering using system memory. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 36 This is the size in bytes of the buffer for DMA Channel m, buffer n. It must be an integer number of double-words (i.e. b[1:0] are reserved). The actual size is FB_DMAm_SIZEn + 4 Bytes. The maximum buffer size is 16MB. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 37: Table 14: Functional Block Header

    NOTE: This register is not implemented on every function block. You must check each function block’s register map to see if this register is defined. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 38: Table 15: High Speed A/D Functional Block

    0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 39: Start_Trig (Read/Write)

    This register is used to set a delay relative to the ADC’s distribution clock. This delay will only be noticeable affect the ADC output clocks have been synchronized by using the …. register of the Clock Generator function block. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 40: Clk_Ready

    B4: Stop Trigger B5: Post-Stop Buffer Filled B6: Sampling has completed, and the FIFO is empty (all data transferred to host) B7: Pacer – The pacer clock has ticked. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 41: Clk_Busn

    This register shows the current sample count that is available in the ADC’s FIFO. 6.4.17 MAX_FIFO_SIZE (R This register shows the max number of samples that the ADC’s FIFO can hold. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 42: Figure 13: Filter Response With Each Order Value

    This is the interrupts enable for the threshold detection. Bit defines are above. An interrupt is generated (if not already generated) each time a sample is taken and the value is above the high threshold or below the low threshold. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 43 This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 44: Table 16: Advance Dio Functional Block

    (FB_CHANNEL_SIZE * 0x04 * n) Note: n in the offset stands for channel number. Channel 0 is Digital In, Channel 1 is Digital Out, Channel 2 is Pin Direction DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 45: Clk_Src (Read/Write)

    Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger, unless PRE_START_COUNT is non-zero in which case CLK_DIV will start counting immediately. Refer to CLK_SRC (Read/Write) section above, for list of valid values. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 46: Clk_Busn

    A function block can drive multiple different Clock Buses. However, a Clock Bus N should not be driven by more than one function block at the same time or the clock signal will be undefined. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 47 The Capture register latches the input ports when an interrupt is generated. All values are latched, regardless of the ADV_INT_MASK register, or DIO_DIRECTION. This register can be written to when ADV_INT_MODE is set to Disabled. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 48: Mode_Config (Maskable Read/Write)

    This register shows the current sample count in Digital I/O channel FIFO. 6.5.21 CH _MAX_FIFO_SIZE (R This register shows the max number of samples that the Digital I/O channel FIFO can hold. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 49 This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 50: Table 17:Pwm Functional Block

    0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 51: Clk_Src (Read/Write)

    6.1.8 PERIOD_COUNT (R Total number of periods executed. This does not increment in while in the “Waiting For Start Trigger” state. It also continues counting after a Re-Arm. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 52: Clk_Busn

    This register shows the current sample count that is available in the interval counter FIFO. 6.1.13 CH _MAX_FIFO_SIZE (R This register shows the max number of samples that the interval counter FIFO can hold. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 53 This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 54: Table 18: Incremental Encoder Functional Block

    0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 55: Clk_Src (Read/Write)

    Number of samples to collect before the Start Trigger. The length is limited by the FIFO size – writing a value larger than the FIFO size will have indeterminate results. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 56: Clk_Busn

    0x8B: Low threshold crossed. 6.2.14 MODE_CONFIG (MASKABLE READ/WRITE) This register provides configuration for Incremental Encoder. B[12]: Differential: Selects single-ended or differential mode ’0’ = Single Ended. Only “+” inputs are used DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 57 “Pause.” Each register access advances to the next sample. If the MODE_CONFIG[HOLD] = 1, the last value before HOLD was enable will be written to the FIFO on each clock pulse, until HOLD is disabled. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 58: Table 19:External Clocking Functional Block

    All pins default to inputs at power-up. 6.3.5 EXT_CLK_EDGE (R RITE Selects which edge detect to trigger on. This is a bit settable register. 0= Rising Edge Detect, 1= Fall Edge Detect. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 59 0x82: Clock Gated (Low): CLK_BUSn will be inputted when the EXT_CLK_GATEn corresponding gate value is low, this doesn’t affect when outputting a clock. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 60: Table 20: Temperature Sensor Functional Block

    0x01: External Reference Clock (CN5) o 0x02: SyncBus Reference Clock, (SyncBus3 of CN11) o 0x03: Reserved 6.5.3 PLL_STATUS (R This register indicates the status of the PLL of clock generator. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 61 B0: for reads, 0 = Busy, 1 = Synchronization is ready. Write 0x01 to start the synchronization process. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 62: Table 22: Capture Window Functional Block

    0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 63: Clk_Src (Read/Write)

    Each bit corresponds to an interrupt source. A value of ‘1’ enables the source, and a value of ‘0’ disables it. See below for a description of the sources. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 64: Clk_Busn

    0x80: Capture Window – Indicates state of window, high when during capture and low when during delay o 0x81: Reserved o 0x82: Reserved o 0x83: Start Trigger o 0x84: Reserved o 0x85: Reserved o 0x86: Reserved DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 65 Sets the width of delay counter n. Delay Counter = (DELAY_COUNTER_n) / (Pacer Clock). 6.6.13 CAPTURE_COUNTER_ RITE Sets the width of capture counter n. Capture Counter = (CAPTURE_COUNTER_n) / (Pacer Clock). DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 66: Table 23: Syncbus Functional Block

    Select if the SyncBus driver is enable. When the SyncBus driver is disabled, the transceiver is powered down and SyncBus will not receive or transmit. This bit must be enabled in order to use the SyncBus. B0: Enable SyncBus driver, 0 = disabled (low power), 1 = enabled. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 67: Clk_Busn

    6.7.8 CLK_BUS Selects the source to drive onto Clock Bus signal N. Values are: B[7:0] Clock Source Select 0x00: Disable Clock Source 0x80: CLK_EVENT_SYNCBUS_0 0x81: CLK_EVENT_SYNCBUS_1 0x82: CLK_EVENT_SYNCBUS_2 DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 68 B[1]: Data be to driven on SYNC1p/n when the SyncBus is configured for GPIO mode and SYNC_OUT_EN is set. • B[0]: Data be to driven on SYNC0p/n when the SyncBus is configured for GPIO mode and SYNC_OUT_EN is set. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 69: Table 24: Programmable Clock Functional Block

    0x00: Stopped – The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require initialization. 0x01: Reserved 0x02: Waiting for start trigger 0x03: Running/Waiting for stop trigger 0x04: Reserved 0x05: Reserved 0x07: Done capturing DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 70: Clk_Src (Read/Write)

    Each bit corresponds to an interrupt source. A value of ‘1’ enables the source, and a value of ‘0’ disables it. See below for a description of the sources. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...

  • Page 71: Clk_Busn

    LAST_INTERVAL_COUNT and generate an interval counter interrupt. 6.8.16 LAST_INTERVAL_COUNT (R The last count value taken from the COUNT register. This is the same value that is written to the DMA FIFO. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 72 This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 73 If problems persist, or you have questions about configuring this product, contact RTD Embedded Technologies via the following methods: Phone: +1-814-234-8087 E-Mail: techsupport@rtd.com Be sure to check the RTD web site (http://www.rtd.com) frequently for product updates, including newer versions of the board manual and application software. DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc.
  • Page 74 PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group: www.pcisig.com DM34216HR | www.rtd.com User’s Manual RTD Embedded Technologies, Inc. BDM-610010056 Rev A...
  • Page 75 During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded Technologies.
  • Page 76 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com Copyright 2018 by RTD Embedded Technologies, Inc. All rights reserved.

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