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Multichannel CODEC with S/PDIF Transceiver
DESCRIPTION
The WM8580 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8580 is ideal for DVD and surround
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
Integrated into the device is a stereo 24-bit multi-bit sigma
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
Also included are three stereo 24-bit multi-bit sigma delta
DACs,
each
with a dedicated oversampling digital
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
The S/PDIF transceiver is IEC-60958-3 compatible and
supports frame rates from 32k/s to 192k/s. It has four
multiplexed inputs and one output. Status and error
monitoring is built-in and results can reported over the serial
interface or via GPO pins. S/PDIF Channel Block
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
The device is available in a 48-lead TQFP package.
WOLFSON MICROELECTRONICS plc
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FEATURES
•
Mutli-channel CODEC with 3 Stereo DACs and 1 Stereo
ADC
•
Integrated S/PDIF / IEC-60958-3 transceiver
•
Audio Performance
−
103dB SNR ('A' weighted @ 48kHz) DAC
−
-90dB THD (48kHz) DAC
−
100dB SNR ('A' weighted @ 48kHz) ADC
−
-90dB THD (48kHz) ADC
•
DAC Sampling Frequency: 8kHz – 192kHz
•
ADC Sampling Frequency: 8kHz – 192kHz
•
Independent ADC and DAC Sample Rates
•
2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
•
GPO pins allow visibility of user selected status flags
•
Programmable Audio Data Interface Modes
−
2
I
S, Left, Right Justified or DSP
−
16/20/24/32 bit Word Lengths
•
Three Independent Stereo DAC Outputs with Digital
Volume Controls
•
Two Independent Master or Slave Audio Data Interfaces
•
Flexible Digital Interface Routing with Clock Selection
Control
•
2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
•
48-lead TQFP Package
APPLICATIONS
•
Digital TV
•
DVD Players and Receivers
•
Surround Sound AV Processors and Hi-Fi systems
•
Automotive Audio
Product Preview, March 2006, Rev 1.0
Copyright 2006 Wolfson Microelectronics plc
WM8580
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Table of Contents
Related Manuals for Wolfson WM8580
Summary of Contents for Wolfson WM8580
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Page 1: Description
DESCRIPTION FEATURES • Mutli-channel CODEC with 3 Stereo DACs and 1 Stereo The WM8580 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8580 is ideal for DVD and surround • sound processing applications for home hi-fi, automotive Integrated S/PDIF / IEC-60958-3 transceiver and other audiovisual equipment. -
Page 2: Block Diagram
WM8580 Product Preview BLOCK DIAGRAM PP Rev 1.0 March 2006... -
Page 3: Table Of Contents
WM8580 Product Preview TABLE OF CONTENTS DESCRIPTION ..................................1 FEATURES ..................................1 APPLICATIONS ................................... 1 BLOCK DIAGRAM ................................2 TABLE OF CONTENTS................................ 3 PIN CONFIGURATION................................. 4 ORDERING INFORMATION..............................4 PIN DESCRIPTION ................................5 MULTI-FUNCTION PINS..............................6 ABSOLUTE MAXIMUM RATINGS ............................7 RECOMMENDED OPERATING CONDITIONS ........................ -
Page 4: Pin Configuration
WM8580 Product Preview PIN CONFIGURATION ORDERING INFORMATION PEAK TEMPERATURE MOISTURE DEVICE PACKAGE SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE 48-lead TQFP WM8580GEFT/V -25 to +85 MSL1 260°C (Pb-free) 48-lead TQFP WM8580GEFT/RV -25 to +85 MSL1 260°C (Pb-free, tape and reel) Note: Reel quantity = 2,200... -
Page 5: Pin Description
WM8580 Product Preview PIN DESCRIPTION NAME TYPE DESCRIPTION PGND Supply PLL ground PVDD Supply PLL positive supply Digital Input Crystal or CMOS clock input Digital Output Crystal output MFP10 Digital Output Multi-Function Pin (MFP) 10. See Table 1 for details of all MFP pins. -
Page 6: Multi-Function Pins
In hardware control mode, pin 31 is used for NON_AUDIO flag output. MULTI-FUNCTION PINS The WM8580 has 8 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins are configured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs have the function shown in column 1 of Table 1. -
Page 7: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. The WM8580 has been classified as MSL1, which has an unlimited floor life at <30 C / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags. -
Page 8: Recommended Operating Conditions
WM8580 Product Preview RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS UNIT Digital supply range DVDD Analogue supply range AVDD, PVDD Ground AGND, VREFN, DGND. PGND Difference DGND to -0.3 +0.3 AGND/PGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. - Page 9 WM8580 Product Preview Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated.
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Page 10: Terminology
WM8580 Product Preview Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated. -
Page 11: Master Clock Timing
WM8580 Product Preview MASTER CLOCK TIMING MCLKL ADCMCLK/ MCLK MCLKH MCLKY Figure 1 Master Clock Timing Requirements Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 PARAMETER SYMBOL... -
Page 12: Digital Audio Interface - Master Mode
WM8580 Product Preview DIGITAL AUDIO INTERFACE – MASTER MODE Figure 2 Digital Audio Data Timing – Master Mode Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, PGND, DGND = 0V, T = +25 C, Master Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. -
Page 13: Digital Audio Interface - Slave Mode
WM8580 Product Preview DIGITAL AUDIO INTERFACE – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. -
Page 14: Control Interface Timing - 3-Wire Mode
WM8580 Product Preview CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 SPI Compatible Control Interface Input Timing Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless... -
Page 15: Control Interface Timing - 2-Wire Mode
WM8580 Product Preview CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless... -
Page 16: Device Description
The serial control interface is controlled by pins CSB, SCLK, and SDIN, which are 5V tolerant with TTL input thresholds, allowing the WM8580 to be used with DVDD = 3.3V and be controlled by a controller with 5V output. SDO allows status registers to be read back over the serial interface (SDO is not 5V tolerant). -
Page 17: Control Interface Operation
Product Preview CONTROL INTERFACE OPERATION Control of the WM8580 is implemented either in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. - Page 18 WM8580 Product Preview REGISTER ADDRESS LABEL DEFAULT DESCRIPTION READMUX Determines which status register is to be read back: READBACK [2:0] 000 = Error Register 001 = Channel Status Register 1 010 = Channel Status Register 2 011 = Channel Status Register 3...
- Page 19 Once the WM8580 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8580 register address plus the first bit of register data). The WM8580 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e.
- Page 20 Product Preview REGISTER READBACK The WM8580 allows readback of certain registers in 2-wire mode, with data output on the SDO pin. As in 3-wire mode, there are two methods of reading back data: continuous and non-continuous readback. Continuous readback is set by writing to the Readback Control register (see Table 9) to set READEN and CONTREAD to 1, and to set the READMUX bits to select the register to be read back.
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Page 21: Digital Audio Interfaces
SOFTWARE REGISTER RESET Writing to register R53 will cause a register reset, resetting all register bits to their default values. Note that the WM8580 is powered down by default so writing to this register will power down the device. REGISTER... - Page 22 WM8580 Product Preview Figure 13 Master Mode REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRX PAIF Receiver Master/Slave Mode Select: PAIF 1 0 = Slave Mode 1 = Master Mode PAIFTX PAIF Transmitter Master/Slave Mode Select: PAIF 2 0 = Slave Mode...
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Page 23: Audio Data Formats
LEFT JUSTIFIED MODE In Left Justified mode, the MSB of the input data is sampled by the WM8580 on the first rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the same falling edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. - Page 24 WM8580 Product Preview Figure 14 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In Right Justified mode, the LSB of input data is sampled on the rising edge of BCLK preceding a LRCLK transition. The LSB of the output data changes on the falling edge of BCLK preceding a LRCLK transition, and may be sampled on the next rising edge of BCLK.
- Page 25 WM8580 Product Preview DSP MODE A In DSP Mode A, the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 and 3 follow as shown in Figure 17.
- Page 26 WM8580 Product Preview DSP MODE B In DSP Mode B, the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 and 3 follow as shown in Figure 20.
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Page 27: Audio Interface Control
WM8580 Product Preview AUDIO INTERFACE CONTROL The register bits controlling the audio interfaces are summarized below. Dynamically changing the audio data format may cause erroneous operation, and is not recommended. Interface timing is such that the input data and LRCLK are sampled on the rising edge of the interface BCLK. - Page 28 WM8580 Product Preview PAIFTXBCP PAIF Receiver BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted SAIFFMT SAIF Audio Data Format Select SAIF 2 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified SAIFWL...
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Page 29: Dac Features
WM8580 Product Preview DAC FEATURES DAC INPUT CONTROL The Primary Audio Interface Receiver has a separate input pin for each stereo DAC. Any input pin can be routed to any DAC using the DACSEL register bits. REGISTER ADDRESS LABEL DEFAULT... - Page 30 WM8580 Product Preview DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio interface are applied to the left and right DACs: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PL[3:0] 1001 PL[3:0] Left O/P...
- Page 31 WM8580 Product Preview INFINITE ZERO DETECT Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Infinite zero detection circuit control and automute control DAC CONTROL 2 0 = Infinite zero detect automute...
- Page 32 1 = Apply gain and update attenuation on all channels. Table 22 Digital Attenuation Registers Note: The volume update circuit of the WM8580 has two sets of registers; LDAx and RDAx. These can be accessed individually, or simultaneously by writing to MASTDA - Master Digital Attenuation.
- Page 33 Product Preview MUTE MODES The WM8580 has individual mutes for each of the three DAC channels. Setting DMUTE for a channel will apply a ‘soft-mute’ to the input of the digital filters for that channel. DMUTE[0] mutes DAC1 channel, DMUTE[1] mutes DAC2 channel and DMUTE[2] mutes DAC3 channel. Setting the MUTEALL register bit will apply a 'soft-mute’...
- Page 34 WM8580 Product Preview Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards V with a time constant of approximately 64 input samples.
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Page 35: Adc Features
WM8580 Product Preview ADC FEATURES ADC HIGH-PASS FILTER DISABLE The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled. -
Page 36: Digital Routing Options
Product Preview DIGITAL ROUTING OPTIONS The WM8580 has extremely flexible digital interface routing options, which are illustrated in Figure 24. It has S/PDIF Receiver, S/PDIF Transmitter, 3 Stereo DACs, a Stereo ADC, a Primary Audio Interface and a Secondary Audio Interface. - Page 37 WM8580 Product Preview The registers described below configure the digital routing options. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DAC_SRC DAC1 Source: PAIF 3 [1:0] 00 = S/PDIF received data. 10 = SAIF Receiver data 11 = PAIF Receiver data Note: When DAC_SRC = 00, DAC2/3 may be turned off, depending on RX2DAC_MODE.
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Page 38: Clock Selection
Product Preview CLOCK SELECTION To accompany the flexible digital routing options, the WM8580 offers a clock configuration scheme for each interface. The user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or PLLBCLK. For some interfaces, the rate can be controlled either by external LRCLK (slave mode), internal LRCLK (master mode) or by control register. - Page 39 WM8580 Product Preview ADC INTERFACE The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. However, if the S/PDIF receiver is active, PLLACLK and PLLBCLK are invalid for ADC operation, so the choice is limited to ADCMCLK (default) or MCLK.
- Page 40 WM8580 Product Preview S/PDIF INTERFACES The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK, but both PLLACLK and PLLBCLK are unavailable in user mode when the S/PDIF receiver is active. If the digital routing has been configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected.
- Page 41 The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 21.
- Page 42 The PAIF Transmitter requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Generator module. The control of this module is described on page 21.
- Page 43 BCLK. These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 21.
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Page 44: Phase-Locked Loops And S/Pdif Clocking (Software Mode)
The oscillator circuit contains a bias generator within the WM8580 and hence an external bias resistor is not required. Crystal frequencies between 10 and 14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT must be powered up using the OSCPD bit. - Page 45 Table 38 Oscillator Control PHASE-LOCKED LOOP (PLL) The WM8580 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can be used to: •...
- Page 46 WM8580 Product Preview • PLL User Mode (Selected if S/PDIF Receiver Disabled) In user mode, the user has full control over the function and operation of both PLLA and PLLB. In this mode, the user can accurately specify the PLL N and K multiplier values and the pre and post- scale divider values and can hence fully control the generated clock frequencies.
- Page 47 WM8580 Product Preview PLL CONFIGURATION The PLLs perform a configurable frequency multiplication of the input clock signal (f ). The multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f ÷...
- Page 48 WM8580 Product Preview FREQMODE_x[1:0] TO PLLxCLK DIVISION FACTOR POSTSCALE_x ÷2 ÷4 ÷4 ÷8 ÷8 ÷16 ÷12 ÷24 Table 43 PLL User Mode Clock Divider Configuration POSTSCALE_A PLLACLK FREQUENCY 256fs 128fs Table 44 PLL S/PDIF Receiver Mode Clock Divider Configuration PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required PLLBCLK frequency is 12.288MHz.
- Page 49 CLKOUT signal are shown in Table 46. The MCLK pin can be configured as an input or output – the WM8580 should be powered down when switching MCLK between an input and an output. As an output, MCLK can be sourced from OSCCLK, PLLACLK or PLLBCLK.
- Page 50 WM8580 Product Preview S/PDIF RECEIVE MODE CLOCKING In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream.
- Page 51 WM8580 Product Preview PRE- S/PDIF RECEIVER PLLB_N PLLB_K COMMENT SCALE_X SAMPLE RATE(S) (kHz) (MHz) (MHz) (Hex) (Hex) (MHz) 11.2896 32 / 44.1 / 48 / 88.2 / 96 11.2896 94.3104 8.3537 16A3B3 Set N, K 11.2896 11.2896 98.304 8.7075 2D4766 Set N, K 32 / 44.1 / 48 / 88.2 / 96...
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Page 52: Phase-Locked Loops And S/Pdif Clocking (Hardware Mode)
WM8580 Product Preview PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE) In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and S/PDIF receiver control is fully automatic. -
Page 53: S/Pdif Transceiver
DSP (via the Digital Audio Interfaces), or if the data is audio PCM, it can route the stereo recovered data to DAC1. The recovered clock may be routed out of the WM8580 onto a pin for external use, and may be used to clock the internal DAC as required. - Page 54 S/PDIF input stream by the S/PDIF receiver. User Data Set to 0 as User Data configuration is not supported in the WM8580 – if TXSRC=00 (S/PDIF receiver) User Data is the value recovered from the S/PDIF input stream by the S/PDIF receiver.
- Page 55 The Channel Status bits form a 192-frame block - transmitted at 1 bit per sub-frame. Each sub-frame forms its own 192-frame block. The WM8580 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8580 is stereo, so the channel status data is duplicated for both channels.
- Page 56 WM8580 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS SRCNUM 19:16 0000 Source Number. No definitions are attached to data. [3:0] SPDTXCHAN 3 CHNUM1[1:0] 23:20 Channel Number for Subframe 1 CHNUM1 Channel Status Bits[23:20] 0000 = Do not use channel...
- Page 57 WM8580 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS BIT MAXWL Maximum Audio sample word length 0 = 20 bits SPDTXCHAN 5 1 = 24 bits TXWL[2:0] 35:33 Audio Sample Word Length. 000 = Word Length Not Indicated TXWL[2:0]...
- Page 58 DAC1. The WM8580 can detect when the data is in a non-compressed audio format and will automatically mute the DAC. See Non-Audio Detection for more detail.
- Page 59 WM8580 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS CATCODE 15:8 Category Code. Refer to S/PDIF specification IEC60958-3 for details. [7:0] SPDRXCHAN 2 00h indicates “general” mode. (read-only) Table 56 S/PDIF Receiver Channel Status Register 2 REGISTER LABEL CHANNEL...
- Page 60 WM8580 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS MAXWL Maximum Audio sample word length 0 = 20 bits SPDRXCHAN 5 1 = 24 bits (read-only) RXWL[2:0] 35:33 Audio Sample Word Length. 000: Word Length Not Indicated RXWL[2:0] MAXWL==1...
- Page 61 WM8580 Product Preview STATUS FLAGS There are several status flags generated by the S/PDIF Receiver, described below. FLAG DESCRIPTION VISIBILITY UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked, or the S/PDIF Status incoming S/PDIF signal is not present.
- Page 62 WM8580 Product Preview INTERRUPT GENERATION (INTB) The hardware interrupot INTB flag (active low) indicates that an event has occurred on UNLOCK, INVALID, TRANS_ERR, NON_AUDIO, CPY_N, DEEMPH, CSUD or REC_FREQ. To determine which flag caused the interrupt, the Interrupt Status Register should be read when INTB is asserted.
- Page 63 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUDIO_N Recovered Channel Status bit-1. SPDSTAT 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. (read-only) PCM_N Indicates that non-audio code (defined in IEC-61937) has been detected.
- Page 64 Should a TRANS_ERR or INVALID flag be asserted, it is assumed the recovered S/PDIF sub-frame is corrupted or invalid. If either flag is masked using the mask register, the WM8580 will overwrite the recovered frame (i.e. both sub-frames) with either all-zeros or the last valid data sample; depending on how FILLMODE has been set.
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Page 65: Powerdown Modes
Table 66 GPO Control Registers POWERDOWN MODES The WM8580 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use. - Page 66 WM8580 Product Preview REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PWDN Master powerdown (overrides all powerdown registers) PWRDN 1 0 = All digital circuits running, outputs are active 1 = All digital circuits in power down mode, outputs muted ADCPD ADC powerdown...
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Page 67: Internal Power On Reset Circuit
INTERNAL POWER ON RESET CIRCUIT Figure 33 Internal Power On Reset Circuit Schematic The WM8580 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a default state after power up. Figure 33 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. - Page 68 WM8580 Product Preview Figure 34 Typical Power up sequence where DVDD is powered before AVDD Figure 35 Typical Power up sequence where AVDD is powered before DVDD SYMBOL UNIT pora porr pora_off pord_off Table 68 Typical POR Operation In a real application, the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD.
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Page 69: Hardware Control Mode
Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. In Hardware Control Mode the user has limited control over the features of the WM8580. Most of the features will assume their default settings but some can be modified using external pins. - Page 70 WM8580 Product Preview S/PDIF TRANSMITTER DATA SOURCE S/PDIF received data ADC digital output data SAIF receiver data PAIF receiver data Table 71 DR3 / DR4 Operation The Secondary Audio Interface (SAIF) is not operational in Hardware Mode. STATUS PINS In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag information.
- Page 71 WM8580 Product Preview DESCRIPTION MUTE Normal Operation Mute DAC channels Floating MUTE is an output to indicate when Zero Detection occurs on all DACs (ZFLAG). H = detected, L = not detected. Table 74 MUTE Pin Control Options PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary Audio Interface transmitter.
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Page 72: Register Map
REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8580 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER... - Page 73 WM8580 Product Preview GPO3 GPO6OP[3:0] GPO5OP[3:0] 001010100 GPO4 GPO8OP[3:0] GPO70P[3:0] 001110110 GPO5 GPO10OP[3:0] GPO9OP[3:0] 010011000 INTSTAT Error Flag Interupt Status Register SPDRXCHAN 1 Channel Status Register 1 SPDRXCHAN 2 Channel Status Register 2 SPDRXCHAN 3 Channel Status Register 3 SPDRXCHAN 4...
- Page 74 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PRESCALE_B 0 = no pre-scale PLLB 4 1 = divide MCLK by 2 prior to PLLB POSTSCALE_B 0 = no post scale 1= divide MCLK by 2 after PLLB FRACEN_B 0 = Integer N PLLB...
- Page 75 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRXMS PAIF Receiver Master/Slave Mode Select 0 = Slave Mode 1 = Master Mode PAIFRXMS_ PAIF Receiver Master Mode clock source CLKSEL 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK...
- Page 76 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRXFMT PAIF Receiver Audio Data Format Select PAIF 3 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified PAIFRXWL PAIF Receiver Audio Data Word Length [1:0] 11: 32 bits (see Note)
- Page 77 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SAIFFMT SAIF Audio Data Format Select SAIF 2 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified SAIFWL SAIF Audio Data Word Length [1:0] 11: 32 bits (see Note)
- Page 78 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PL[3:0] 1001 PL[3:0] Left O/P Right O/P 0000 Mute Mute CONTROL 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left...
- Page 79 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACATC Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations MPDENB MUTE pin decode enable 0 = MUTE activates soft-mute on DAC selected by DZFM...
- Page 80 0 = SPDIFOP pin sources output of S/PDIF Transmitter 1 = SPDIFOP pins sources output of S/PDIF IN Mux CON/PRO 0 = Consumer Mode 1 = Professional Mode (not supported by WM8580) SPDTXCHAN 1 AUDIO_N 0 = S/PDIF transmitted data is audio PCM.
- Page 81 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 0000 = Do not use channel number CHNUM2[1:0] Channel Number for Subframe 2 CHNUM2 Channel Status Bits[23:20] 0000 = Do not use channel number 0001 = Send to Left Channel 0010 = Send to Right Channel...
- Page 82 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPO1 GPO2OP[3:0] 0001 0001 = V 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = REC_FREQ192 1010 = ZFLAG...
- Page 83 CON/PRO 0 = Consumer Mode 1 = Professional Mode SPDRXCHAN 1 The WM8580 is a consumer mode device. Detection of professional mode may give erroneous behaviour. AUDIO_N Recovered S/PDIF Channel status bit 1. 0 = Data word represents audio PCM samples.
- Page 84 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SRCNUM Indicates number of S/PDIF source. [3:0] SPDRXCHAN 3 CHNUM1[3:0] Channel number for channel 1. 0000 = Take no account of channel number (channel 1 defaults to left DAC) 0001 = channel 1 to left channel...
- Page 85 WM8580 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked or that the input S/PDIF signal is not present. 0 = Locked onto incoming S/PDIF stream. 1 = Not locked to the incoming S/PDIF stream or the incoming S/PDIF stream is not present.
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Page 86: Digital Filter Characteristics
WM8580 Product Preview DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter ±0.01 dB Passband 0.4535fs -6dB 0.5fs ±0.01 Passband ripple Stopband 0.5465fs Stopband Attenuation f > 0.5465fs DAC Filter ±0.05 dB Passband 0.444fs -3dB 0.487fs ±0.05 Passband ripple Stopband 0.555fs... -
Page 87: Digital De-Emphasis Characteristics
WM8580 Product Preview DIGITAL DE-EMPHASIS CHARACTERISTICS -0.5 -1.5 -2.5 Frequency (kHz) Frequency (kHz) Figure 40 De-Emphasis Frequency Response (32kHz) Figure 41 De-Emphasis Error (32KHz) -0.1 -0.2 -0.3 -0.4 Frequency (kHz) Frequency (kHz) Figure 42 De-Emphasis Frequency Response (44.1KHz) Figure 43 De-Emphasis Error (44.1KHz) -0.2... -
Page 88: Adc Filter Responses
Figure 46 ADC Digital Filter Frequency Response Figure 47 ADC Digital Filter Ripple ADC HIGH PASS FILTER The WM8580 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. 1 - z H(z) = 1 - 0.9995z... -
Page 89: Recommended External Components
WM8580 Product Preview RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components PP Rev 1.0 March 2006... - Page 90 WM8580 Product Preview Figure 50 Recommended External Components PP Rev 1.0 March 2006...
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Page 91: Package Dimensions
WM8580 Product Preview PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C Θ Θ Θ Θ A A2 SEATING PLANE ccc C Dimensions Symbols (mm) ----- ----- 1.20 0.05 ----- 0.15 0.95 1.00 1.05 0.17 0.22 0.27... -
Page 92: Important Notice
Product Preview IMPORTANT NOTICE Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current.
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