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Wolfson WM8976 Manual

Stereo codec with speaker driver
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DESCRIPTION
The WM8976 is a low power, high quality CODEC designed
for portable applications such as multimedia phone, digital
still camera or digital camcorder.
The device integrates a preamp for differential microphone,
and
includes
drivers
for
differential or stereo line output. External component
requirements are reduced as no separate microphone or
headphone amplifiers are required.
Advanced on-chip digital signal processing includes a 5-
band equaliser, a mixed signal Automatic Level Control for
the microphone or line input through the ADC as well as a
purely digital limiter function for record or playback.
Additional digital filtering options are available in the ADC
path, to cater for application filtering such as 'wind noise
reduction'.
The WM8976 digital audio interface can operate as a master
or a slave. An internal PLL can generate all required audio
clocks for the CODEC from common reference clock
frequencies, such as 12MHz and 13MHz.
The WM8976 operates at analogue supply voltages from
2.5V to 3.3V, although the digital core can operate at
voltages down to 1.71V to save power. The speaker outputs
and OUT3/4 line outputs can run from a 5V supply if
increased output power is required. Individual sections of
the chip can also be powered down under software control.
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up
Stereo CODEC with Speaker Driver
speakers,
headphone
at
http://www.wolfsonmicro.com/enews
FEATURES
Stereo CODEC:
DAC SNR 98dB, THD -84dB ('A' weighted @ 48kHz)
ADC SNR 95dB, THD -84dB ('A' weighted @ 48kHz)
On-chip Headphone Driver with 'capless' option
-
40mW per channel into 16 / 3.3V SPKVDD
and
1W output power into 8 BTL speaker / 5V SPKVDD
-
Capable of driving piezo speakers
-
Stereo speaker drive configuration
Mic Preamps:
Differential or single-ended microphone interfaces
-
Programmable preamp gain
-
Pseudo differential input with common mode rejection
-
Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphone
Other Features:
Enhanced 3-D function for improved stereo separation
Digital playback limiter
5-band Equaliser (record or playback)
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
Aux inputs for stereo analogue input signals or 'beep'
On-chip PLL supporting 12, 13, 19.2MHz and other clocks
Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz
sample rates
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
5x5mm 32-lead QFN package
APPLICATIONS
Stereo Camcorder or DSC
Multimedia Phone
WM8976
Production Data, November 2011, Rev 4.5
Copyright 2011 Wolfson Microelectronics plc

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  • Page 1 WM8976 Stereo CODEC with Speaker Driver DESCRIPTION FEATURES Stereo CODEC: The WM8976 is a low power, high quality CODEC designed  DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz) for portable applications such as multimedia phone, digital  ADC SNR 95dB, THD -84dB (‘A’ weighted @ 48kHz) still camera or digital camcorder.

  • Page 2: Table Of Contents

    WM8976 Production Data TABLE OF CONTENTS TABLE OF CONTENTS ..................2   PIN CONFIGURATION ..................4   ORDERING INFORMATION .................. 4   PIN DESCRIPTION ....................5   ABSOLUTE MAXIMUM RATINGS ................ 6   RECOMMENDED OPERATING CONDITIONS ............. 6   ELECTRICAL CHARACTERISTICS ..............7  ...
  • Page 3 WM8976 Production Data APPLICATION INFORMATION ................. 111   RECOMMENDED EXTERNAL COMPONENTS ............111  PACKAGE DIAGRAM ..................112   IMPORTANT NOTICE ..................113   ADDRESS ........................113  REVISION HISTORY ..................114   PD, Rev 4.5, November 2011...

  • Page 4: Pin Configuration

    WM8976 Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE PEAK SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE WM8976CGEFL/V -25C to +85C 32-lead QFN (5 x 5 mm) MSL3 (Pb-free) WM8976CGEFL/RV -25C to +85C 32-lead QFN (5 x 5 mm)

  • Page 5: Pin Description

    WM8976 Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION Analogue input Mic Pre-amp positive input Analogue input Mic Pre-amp negative input Analogue input Line input/secondary mic pre-amp positive input/GPIO2 pin L2/GPIO2 Do not connect Leave this pin floating Do not connect...

  • Page 6: Absolute Maximum Ratings

    Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity.

  • Page 7: Electrical Characteristics

    WM8976 Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Preamp Inputs (LIP, LIN) Full-scale Input Signal Level –...
  • Page 8 WM8976 Production Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 6) A-weighted, 0dB gain...

  • Page 9: Terminology

    WM8976 Production Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT OUT3/OUT4 outputs (with 10k / 50pF load) Full-scale output voltage, 0dB OUT3BOOST=0/ SPKVDD/3.3...

  • Page 10: Speaker Output Thd Versus Power

    WM8976 Production Data SPEAKER OUTPUT THD VERSUS POWER Speaker Power vs THD+N (8Ohm BTL Load) AVDD=SPKVDD=DBVDD=3.3, DCVDD=1.8 -100 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00 Output Power (mW) Speaker Power vs THD+N (8Ohm BTL Load) AVDD=DBVDD=3.3V, SPKVDD=5V, DCVDD=1.8V -100 0.00...

  • Page 11: Power Consumption

    WM8976 Production Data POWER CONSUMPTION Typical current consumption for various scenarios is shown below. AVDD DCVDD DBVDD TOTAL MODE (3.0V) (1.8V) (3.0V) POWER (mA) (mA) (mA) (mW) 0.04 0.0008 <0.0001 0.12 Sleep (VREF maintained, no clocks) 0.04 0.0008 <0.0001 0.12 MIC Record (8kHz) 0.001...
  • Page 12 WM8976 Production Data REGISTER BIT AVDD CURRENT (mA) AVDD=3.3V BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN 1.2 (with clocks applied) MICBEN BIASEN BUFIOEN VMIDSEL 5KΩ = >0.3, less than 0.1 for 75KΩ 300KΩ settings ROUT1EN LOUT1EN BOOSTENL INPPGAENL ADCENL 2.6 (x64, ADCOSR=0) 4.9 ( x128, ADCOSR=1)

  • Page 13: Audio Paths Overview

    WM8976 Production Data AUDIO PATHS OVERVIEW Figure 1 WM8976 Audio Signal Paths PD, Rev 4.5, November 2011...

  • Page 14: Signal Timing Requirements

    WM8976 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY MCLK cycle time...

  • Page 15: Audio Interface Timing - Slave Mode

    WM8976 Production Data Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, =+25 Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge...

  • Page 16: Control Interface Timing - 3-Wire Mode

    WM8976 Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T =+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

  • Page 17: Control Interface Timing - 2-Wire Mode

    WM8976 Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, =+25 Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL...

  • Page 18: Internal Power On Reset Circuit

    WM8976 Production Data INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8980 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD.
  • Page 19 WM8976 Production Data Figure 9 Typical Power up Sequence where DVDD is Powered before AVDD Figure 9 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold,...

  • Page 20: Device Description

    DEVICE DESCRIPTION INTRODUCTION The WM8976 is a low power audio CODEC combining a high quality stereo audio DAC and mono ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, digital camcorders, and digital still cameras with record and playback capability.
  • Page 21 CONTROL INTERFACES To allow full software control over all features, the WM8976 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.

  • Page 22: Input Signal Path

    WM8976, and the stereo signal listened to via headphones. INPUT SIGNAL PATH The WM8976 has flexible analogue inputs. An input PGA stage is followed by a boost/mix stage which drives into the hi-fi ADC. The input path has three input pins which can be configured in a variety of ways to accommodate single-ended or differential microphones.
  • Page 23 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIP2INPPGA Connect LIP pin to input PGA amplifier positive terminal. Input Control 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input...
  • Page 24 WM8976 Production Data VOLUME UPDATES Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAUPDATE bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 11.
  • Page 25 WM8976 Production Data Figure 13 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8980 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAUPDATE bit is set as shown in Figure 14.
  • Page 26 WM8976 Production Data AUXILIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs. The AUXL input can be used as a line input to the input BOOST stage which has gain adjust of -12dB to +6dB in 3dB steps (plus off).
  • Page 27 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUXL2BOOSTVOL Controls the auxiliary amplifier to the input boost stage: Input BOOST control 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage...

  • Page 28: Analogue To Digital Converter (Adc)

    Figure 16 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8976 uses a multi-bit, oversampled sigma-delta ADC. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD.
  • Page 29 WM8976 Production Data The polarity of the output signal can also be changed under software control using the ADCLPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
  • Page 30 WM8976 Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. The coefficients must be entered in 2’s complement notation. A0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
  • Page 31 WM8976 Production Data NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth. Fc = 1000 Hz fb = 100 Hz fs = 48000 Hz ...

  • Page 32: Input Limiter / Automatic Level Control (Alc)

    Production Data INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8976 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal.
  • Page 33 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCHLD 0000 ALC hold time before gain is increased. [3:0] (0ms) 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s...
  • Page 34 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 0010 90.8us 726us 5.23ms … (time doubles with every step) 1010 23.2ms 186ms 1.34s higher Table 18 ALC Control Registers WHEN THE ALC IS DISABLED, THE INPUT PGA REMAINS AT THE LAST CONTROLLED VALUE OF THE ALC.
  • Page 35 WM8976 Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode.
  • Page 36 WM8976 Production Data ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing.
  • Page 37 WM8976 Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) Attack Time (s) ALCATK ATKLIM ATKLIM6dB ATKLIM90% 0000 22.7µs 182µs 1.31ms 0001 45.4µS 363µs 2.62ms 0010 90.8µS 726µs 5.23ms 0011 182µS 1.45ms 10.5ms 0100 363µS 2.91ms 20.9ms 0101 726µS 5.81ms 41.8ms...
  • Page 38 WM8976 Production Data MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
  • Page 39 WM8976 Production Data ALCMIN Minimum Gain (dB) Table 23 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range.
  • Page 40 WM8976 Production Data Figure 21 ALCLVL PD, Rev 4.5, November 2011...
  • Page 41 WM8976 Production Data Figure 22 ALC Hold Time ALCHLD HOLD 0000 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 25 ALC Hold Time Values PD, Rev 4.5, November 2011...
  • Page 42 When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8976 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH.
  • Page 43 WM8976 Production Data Figure 23 ALC Operation Above Noise Gate Threshold PD, Rev 4.5, November 2011...

  • Page 44: Output Signal Path

    WM8976, irrespective of whether the DACs are enabled or not. The WM8976 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: ...
  • Page 45 DIGITAL PLAYBACK (DAC) PATH Digital data is passed to the WM8976 via the flexible audio interface and is then passed through a variety of advanced digital filters (as shown in Figure 25) to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits.
  • Page 46 DAC DIGITAL OUTPUT LIMITER The WM8976 has a digital output limiter function. The operation of this is shown in Figure 26. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
  • Page 47 WM8976 Production Data Figure 26 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 26, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter.
  • Page 48 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMATK 0010 Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note DAC digital that these will scale proportionally with limiter control sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms...
  • Page 49 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMLVL Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Table 30 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit.
  • Page 50 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS EQ3G 01100 Band 3 Gain Control. See Table 37 for details. EQ Band 3 (0dB) Control EQ3C Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz EQ3BW Band 3 Bandwidth Control 0=narrow bandwidth...

  • Page 51: 3D Stereo Enhancement

    Production Data 3D STEREO ENHANCEMENT The WM8976 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled.
  • Page 52 WM8976 Production Data Figure 27 Left/Right Output Channel Mixers PD, Rev 4.5, November 2011...
  • Page 53 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACR2LMIX Right DAC output to left output mixer Output mixer 0 = not selected control 1 = selected DACL2RMIX Left DAC output to right output mixer 0 = not selected 1 = selected...
  • Page 54 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACR2RMIX Right DAC output to right output mixer Right channel output mixer 0 = not selected control 1 = selected BYPRMIXVOL Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB …...
  • Page 55 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUT1ZC Headphone volume zero cross enable: LOUT1 1 = Change gain on zero cross only Volume control 0 = Change gain immediately LOUT1MUTE Left headphone output mute: 0 = Normal operation 1 = Mute...
  • Page 56 WM8976 Production Data In the DC coupled configuration, the headphone “ground” is connected to the VMID pin. The OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required.
  • Page 57 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUT2ZC Speaker volume zero cross enable: LOUT2 (SPK) 1 = Change gain on zero cross only Volume 0 = Change gain immediately control LOUT2MUTE Left speaker output mute: 0 = Normal operation...
  • Page 58 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPKBOOST 0 = speaker gain = -1; Output control DC = AVDD / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD / 2 BUFDCOPEN Dedicated buffer for DC level shifting output stages when in 1.5x gain...
  • Page 59 WM8976 Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 31.
  • Page 60 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT3MUTE 0 = Output stage outputs OUT3 mixer OUT3 mixer 1 = Output stage muted – drives out control VMID. Can be used as VMID buffer in this mode. OUT4_2OUT3 OUT4 mixer output to OUT3...
  • Page 61 WM8976 Production Data Figure 32 Outputs OUT3 and OUT4 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT3BOOST 0 = OUT3 output gain = -1; Output control DC = AVDD / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD / 2 OUT4BOOST 0 = OUT4 output gain = -1;...
  • Page 62 WM8976 Production Data OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. Mixer configuration: The polarity of the signal will depend upon the route through the mixer path.
  • Page 63 WM8976 Production Data Table 49 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings, output enables etc are not shown).
  • Page 64 Production Data ENABLING THE OUTPUTS Each analogue output of the WM8976 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8976 should remain disabled.
  • Page 65 WM8976 Production Data A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 34. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled.

  • Page 66: Digital Audio Interfaces

     BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be outputs when the WM8976 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: ...
  • Page 67 WM8976 Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
  • Page 68 WM8976 Production Data In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
  • Page 69 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACMONO Selects between stereo and mono DAC operation: Audio Interface 0=Stereo device operation Control 1=Mono device operation. DAC data appears in ‘left’ phase of LRC ADCLRSWAP Controls whether ADC data appears in ‘right’...
  • Page 70 BCLK Clock Generation 0=BCLK and LRC clock are inputs Control 1=BCLK and LRC clock are outputs generated by the WM8976 (MASTER) BCLKDIV Configures the BCLK output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=SYSCLK)

  • Page 71: Audio Sample Rates

    Production Data AUDIO SAMPLE RATES The WM8976 sample rates for the ADC and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate.
  • Page 72 WM8976 Production Data Figure 40 PLL and Clock Select Circuit The PLL frequency ratio R = f (see Figure 40) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (2 (R-PLLN)) Note: The PLL is designed to operate with best performance (shortest lock time and optimum stability) when f is between 90 and 100MHz and PLL_N is 8.

  • Page 73: Companding

    ADC audio interface is fed directly into the DAC data input. COMPANDING The WM8976 supports A-law and -law and companding and linear mode on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
  • Page 74 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOOPBACK Digital loopback function Companding 0=No loopback Control 1=Loopback enabled, ADC data output is fed directly into left DAC data input. ADC_COMP ADC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law DAC_COMP DAC companding...

  • Page 75: General Purpose Input/Output

    Figure 41 u-Law Companding A-law Companding Normalised Input Figure 42 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT The WM8976 has two dual purpose input/output pins.  CSB/GPIO1: CSB / GPIO pin  L2/GPIO2: Line input / headphone detection input The GPIO2 function is provided for use as a jack detection input.

  • Page 76: Output Switching (Jack Detect)

    WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPIO1SEL CSB/GPIO1 pin function select: GPIO 000= input (CSB/jack detection: depending on MODE setting) Control 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 0 111=logic 1 GPIO1POL GPIO1 Polarity invert...

  • Page 77: Control Interface

    2 or 3 wire mode as shown in Table 64. The WM8976 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed.

  • Page 78: Resetting The Chip

    During a write, once the WM8976 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8976 register address plus the first bit of register data). The WM8976 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e.

  • Page 79: Power Supplies

    WM8976 Production Data POWER SUPPLIES The WM8976 can use up to four separate power supplies:  AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone).

  • Page 80: Recommended Power Up/Down Sequence

    Production Data RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8976 device is powered up and down using one of the following sequences: Power-up when NOT using the output 1.5x boost stage: Turn on external power supplies.
  • Page 81 WM8976 Production Data Notes: This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2).
  • Page 82 WM8976 Production Data Notes: The analogue input pin charge time, t is determined by the VMID pin charge time. This midrail_on, time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time.
  • Page 83 WM8976 Production Data SYMBOL TYPICAL UNIT line_midrail_on line_midrail_off hp_midrail_on hp__midrail_off 2/fs n/fs dacint DAC Group Delay 29/fs n/fs Table 66 Typical POR Operation (typical values, not tested) Notes: The lineout charge time, t is mainly determined by the VMID pin charge time. This time...

  • Page 84: Power Management

    WM8976 Production Data POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device.

  • Page 85: Register Map

    WM8976 Production Data REGISTER MAP REGISTER DEF’T ADDR NAME B[15:9] DEC HEX (HEX) Software Reset Software reset Power manage’t 1 BUFDCOP OUT4MIX OUT3MIX PLLEN MICBEN BIASEN BUFIOEN VMIDSEL Power manage’t 2 ROUT1EN LOUT1EN SLEEP BOOST INPPGA ADCENL Power manage’t 3...
  • Page 86 MUTE OUT3 mixer ctrl OUT3 OUT4_ BYPL2 LMIX2 LDAC2 MUTE 2OUT3 OUT3 OUT3 OUT3 OUT4 (MONO) OUT4 HALFSIG LMIX2 LDAC2 RMIX2 RDAC2 mixer ctrl MUTE OUT4 OUT4 OUT4 OUT4 Table 70 WM8976 Register Map PD, Rev 4.5, November 2011...

  • Page 87: Register Bits By Address

    WM8976 Production Data REGISTER BITS BY ADDRESS Notes 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER LABEL DEFAULT...
  • Page 88 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS Reserved ADCENL Enable ADC: Analogue to Digital 0 = ADC disabled Converter 1 = ADC enabled (ADC) 3 (03h) OUT4EN OUT4 enable Power Management 0 = disabled 1 = enabled...
  • Page 89 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS DACLRSWAP Controls whether DAC data appears in ‘right’ or Digital Audio ‘left’ phases of LRC clock: Interfaces 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC ADCLRSWAP Controls whether ADC data appears in ‘right’...
  • Page 90 Sets the chip to be master over LRC and BCLK Digital Audio Interfaces 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8976 (MASTER) 7 (07h) 00000 Reserved Approximate sample rate (configures the Audio Sample...
  • Page 91 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS JD_EN Jack Detection Enable Output Switching 0=disabled (Jack Detect) 1=enabled Reserved JD_SEL Pin selected as jack detection input Output Switching 0 = GPIO1 (Jack Detect) 1 = GPIO2 Reserved 10 (0Ah)
  • Page 92 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS JD_EN1 0000 Output enabled when selected jack detection input Output is logic 1 Switching (Jack Detect) [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 JD_EN0 0000 Output enabled when selected jack detection input Output is logic 0.
  • Page 93 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 19 (13h) EQ2BW EQ Band 2 Bandwidth Control Output Signal Path 0=narrow bandwidth 1=wide bandwidth Reserved EQ2C EQ Band 2 Centre Frequency: Output Signal Path 00=230Hz 01=300Hz 10=385Hz 11=500Hz EQ2G 01100 EQ Band 2 Gain Control.
  • Page 94 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS LIMDCY 0011 Output Signal DAC Limiter Decay time (per 6dB gain change) for Path 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms...
  • Page 95 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS NFEN Analogue to Notch filter enable: Digital 0=Disabled Converter 1=Enabled (ADC) NFA0[13:7] 0000000 Notch Filter a0 coefficient, bits [13:7] Analogue to Digital Converter (ADC) 28 (1Ch) Notch filter update. The notch filter values used...
  • Page 96 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS ALCMINGAIN Set minimum gain of PGA Input Limiter/ Automatic 000=-12dB Level Control 001=-6dB (ALC) 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB 33 (21h) Reserved ALCHLD 0000 ALC hold time before gain is increased.
  • Page 97 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS … (time doubles with every step) 1010 or 106ms 852ms 6.13s higher 0010 ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182us 1.31ms...
  • Page 98 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS MUTERPGA Mute input to INVROUT2 mixer Analogue Outputs 2INV INVROUT2 Mute input to INVROUT2 mixer Analogue Outputs BEEPVOL AUXR input to ROUT2 inverter gain Analogue Outputs 000 = -15dB 111 = +6dB...
  • Page 99 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS L2_2 Controls the L2 pin to the input boost stage: Input Signal Path BOOSTVOL 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage...
  • Page 100 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS BYPLMIX Bypass volume contol to left output channel mixer: Analogue Outputs 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB BYPL2L Bypass path (from the input boost output) to left...
  • Page 101 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS ROUT1VOL 111001 Right headphone output volume: Analogue Outputs 000000 = -57dB 111001 = 0dB 111111 = +6dB 54 (36h) SPKVU LOUT2 and ROUT2 volumes do not update until a Analogue...
  • Page 102 WM8976 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS OUT4MUTE 0 = Output stage outputs OUT4 mixer Analogue Outputs 1 = Output stage muted – drives out VMID. Can be used as VMID buffer in this mode. HALFSIG 0=OUT4 normal output...

  • Page 103: Digital Filter Characteristics

    WM8976 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner...

  • Page 104: Dac Filter Responses

    WM8976 Production Data DAC FILTER RESPONSES 3.05 2.95 2.85 2.75 -100 -120 2.65 -140 -160 0.05 0.15 0.25 0.35 0.45 Frequency (fs) Frequency (fs) Figure 47 DAC Digital Filter Frequency Response Figure 48 DAC Digital Filter Ripple (128xOSR) (128xOSR) 3.05 2.95...

  • Page 105: Highpass Filter

    Production Data HIGHPASS FILTER The WM8976 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2 order high pass filter with a selectable cut-off frequency.

  • Page 106: 5-Band Equaliser

    Production Data 5-BAND EQUALISER The WM8976 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 57 to Figure 70 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and...
  • Page 107 WM8976 Production Data Frequency (Hz) Frequency (Hz) Figure 57 EQ Band 1 Low Frequency Shelf Filter Cut-offs Figure 58 EQ Band 1 Gains for Lowest Cut-off Frequency Frequency (Hz) Frequency (Hz) Figure 59 EQ Band 2 – Peak Filter Centre Frequencies, Figure 60 EQ Band 2 –...
  • Page 108 WM8976 Production Data Frequency (Hz) Frequency (Hz) Figure 62 EQ Band 3 – Peak Filter Centre Frequencies, EQ3B Figure 63 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 Frequency (Hz) Figure 64 EQ Band 3 – EQ3BW=0, EQ3BW=1...
  • Page 109 WM8976 Production Data Frequency (Hz) Frequency (Hz) Figure 65 EQ Band 4 – Peak Filter Centre Frequencies, EQ3B Figure 66 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 Frequency (Hz) Figure 67 EQ Band 4 – EQ3BW=0, EQ3BW=1...
  • Page 110 WM8976 Production Data Figure 70 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.

  • Page 111: Application Information

    WM8976 Production Data APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 71 Recommended External Component Diagram PD, Rev 4.5, November 2011...

  • Page 112: Package Diagram

    WM8976 Production Data PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE 5 0.9 mm BODY, 0.50 mm LEAD PITCH DM101.A DETAIL 1 INDEX AREA EXPOSED (D/2 X E/2) GROUND PADDLE TOP VIEW BOTTOM VIEW 0.08 SIDE VIEW SEATING PLANE 45°...

  • Page 113: Important Notice

    Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

  • Page 114: Revision History

    WM8976 Production Data REVISION HISTORY DATE ORIGINATOR CHANGES 29/09/11 JMacD Order codes changed from WM8976GEFL/V and WM8976GEFL/RV to WM8976CGEFL/V and WM8976CGEFL/RV to reflect change to copper wire bonding. 29/09/11 JMacD Package Diagram changed to DM101.A PD, Rev 4.5, November 2011...
  • Page 115 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic WM8976-6160-FL32-M WM8976-6160-FL32-M-S WM8976CGEFL/V WM8976CGEFL/RV...

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