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Wolfson WM8978 Manual

Stereo codec with speaker driver
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DESCRIPTION

The WM8978 is a low power, high quality stereo CODEC
designed for portable applications such as multimedia phone,
digital still camera or digital camcorder.
The device integrates preamps for stereo differential mics, and
includes drivers for speakers, headphone and differential or
stereo line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as 'wind noise reduction'.
The WM8978 digital audio interface can operate as a master or
a slave. An internal PLL can generate all required audio clocks
for the CODEC from common reference clock frequencies, such
as 12MHz and 13MHz.
The WM8978 operates at analogue supply voltages from 2.5V
to 3.3V, although the digital core can operate at voltages down
to 1.71V to save power. The speaker outputs and OUT3/4 line
outputs can run from a 5V supply if increased output power is
required. Individual sections of the chip can also be powered
down under software control.

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc
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Stereo CODEC With Speaker Driver
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FEATURES

Stereo CODEC:
•
DAC SNR 98dB, THD -84dB ('A' weighted @ 48kHz)
•
ADC SNR 95dB, THD -80dB ('A' weighted @ 48kHz)
•
On-chip Headphone Driver with 'capless' option
-
40mW per channel into 16Ω / 3.3V SPKVDD
•
0.9W output power into 8Ω BTL speaker / 5V SPKVDD
-
Capable of driving piezo speakers
-
Stereo speaker drive configuration
Mic Preamps:
•
Stereo Differential or mono microphone Interfaces
-
Programmable preamp gain
-
Psuedo differential inputs with common mode
rejection
-
Programmable ALC / Noise Gate in ADC path
•
Low-noise bias supplied for electret microphones
Other Features:
•
Enhanced 3-D function for improved stereo separation
•
Digital playback limiter
•
5-band Equaliser (record or playback)
•
Programmable ADC High Pass Filter (wind noise
reduction)
•
Programmable ADC Notch Filter
•
Aux inputs for stereo analog input signals or 'beep'
•
On-chip PLL supporting 12, 13, 19.2MHz and other clocks
•
Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and
48kHz sample rates
•
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
•
5x5mm 32-lead QFN package

APPLICATIONS

•
Stereo Camcorder or DSC
•
Multimedia Phone
Preliminary Technical Data, November 2005, Rev 2.6
Copyright 2005 Wolfson Microelectronics plc
WM8978

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Summary of Contents for Wolfson WM8978

  • Page 1: Description

    ‘wind noise reduction’. Other Features: • The WM8978 digital audio interface can operate as a master or Enhanced 3-D function for improved stereo separation • a slave. An internal PLL can generate all required audio clocks Digital playback limiter •...

  • Page 2: Table Of Contents

    WM8978 Preliminary Technical Data TABLE OF CONTENTS DESCRIPTION .......................1 BLOCK DIAGRAM ....................1 FEATURES......................1 APPLICATIONS .....................1 TABLE OF CONTENTS ..................2 PIN CONFIGURATION...................4 ORDERING INFORMATION ..................4 PIN DESCRIPTION ....................5 RECOMMENDED OPERATING CONDITIONS .............6 ELECTRICAL CHARACTERISTICS ..............7 TERMINOLOGY ......................10 SPEAKER OUTPUT THD VERSUS POWER ............11 AUDIO PATHS OVERVIEW .................14...
  • Page 3 WM8978 Preliminary Technical Data APPLICATION INFORMATION................106 RECOMMENDED EXTERNAL COMPONENTS ............106 PACKAGE DIAGRAM ..................107 IMPORTANT NOTICE ..................108 ADDRESS: ........................ 108 PTD Rev 2.6 November 2005...

  • Page 4: Pin Configuration

    WM8978 Preliminary Technical Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE PEAK SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE WM8978GEFL/V -25°C to +85°C 32-lead QFN (5 x 5 mm) MSL3 (Pb-free) WM8978GEFL/RV -25°C to +85°C 32-lead QFN (5 x 5 mm)

  • Page 5: Pin Description

    WM8978 Preliminary Technical Data PIN DESCRIPTION NAME TYPE DESCRIPTION Analogue input Left Mic Pre-amp positive input Analogue input Left Mic Pre-amp negative input L2/GPIO2 Analogue input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin Analogue input Right Mic Pre-amp positive input...

  • Page 6: Recommended Operating Conditions

    Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity.

  • Page 7: Electrical Characteristics

    WM8978 Preliminary Technical Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2) Full-scale Input Signal Level –...
  • Page 8 WM8978 Preliminary Technical Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Automatic Level Control (ALC) Target Record Level -22.5 -1.5 Programmable gain 35.25...
  • Page 9 WM8978 Preliminary Technical Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Speaker Output (LOUT2, ROUT2 with 8Ω Ω Ω Ω bridge tied load, INVROUT2=1)

  • Page 10: Terminology

    WM8978 Preliminary Technical Data TERMINOLOGY Input level to RIP and LIP is limited to a maximum of -3dB or THD+N performance will be reduced. Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances.

  • Page 11: Speaker Output Thd Versus Power

    WM8978 Preliminary Technical Data SPEAKER OUTPUT THD VERSUS POWER PTD Rev 2.6 November 2005...

  • Page 12: Power Consumption

    WM8978 Preliminary Technical Data POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE AVDD DCVDD DBVDD TOTAL (3.0V) (1.8V) (3.0V) POWER (mA) (mA) (mA) (mW) 0.04 0.0008 <0.0001 0.12 Sleep (VREF maintained, no clocks) 0.04 0.0008 <0.0001 0.12...
  • Page 13 WM8978 Preliminary Technical Data REGISTER BIT AVDD CURRENT (mA) AVDD=3.3V BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN 1.2 (with clocks applied) MICBEN BIASEN BUFIOEN VMIDSEL 0.3 (5k VMID) <0.1 (75k or 300k VMID) ROUT1EN LOUT1EN BOOSTENR BOOSTENL INPPGAENR INPPGAENL ADCENR 2.6 (x64, ADCOSR=0) 4.9 ( x128, ADCOSR=1)

  • Page 14: Audio Paths Overview

    WM8978 Preliminary Technical Data AUDIO PATHS OVERVIEW PTD Rev 2.6 November 2005...

  • Page 15: Signal Timing Requirements

    WM8978 Preliminary Technical Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY...

  • Page 16: Audio Interface Timing - Slave Mode

    WM8978 Preliminary Technical Data Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, =+25 Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge...

  • Page 17: Control Interface Timing - 3-Wire Mode

    WM8978 Preliminary Technical Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T...

  • Page 18: Control Interface Timing - 2-Wire Mode

    WM8978 Preliminary Technical Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, =+25 Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER...

  • Page 19: Internal Power On Reset Circuit

    Figure 6 Internal Power on Reset Circuit Schematic The WM8978 includes an internal Power-On-Reset Circuit (POR), as shown in Figure 6, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD.
  • Page 20 WM8978 Preliminary Technical Data Figure 8 Typical Power up Sequence where DVDD is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold,...

  • Page 21: Recommended Power Up/Down Sequence

    Preliminary Technical Data RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8978 device is powered up and down using one of the following sequences: Power-up when NOT using the output 1.5x boost stage: Turn on external power supplies.
  • Page 22 WM8978 Preliminary Technical Data Notes: This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2).
  • Page 23 WM8978 Preliminary Technical Data Notes: The analogue input pin charge time, t is determined by the VMID pin charge time. This midrail_on, time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time.
  • Page 24 WM8978 Preliminary Technical Data SYMBOL TYPICAL UNIT line_midrail_on line_midrail_off hp_midrail_on hp__midrail_off 2/fs n/fs dacint DAC Group Delay 29/fs n/fs Table 5 Typical POR Operation (typical values, not tested) Notes: The lineout charge time, t is mainly determined by the VMID pin charge time. This...

  • Page 25: Device Description

    DEVICE DESCRIPTION INTRODUCTION The WM8978 is a low power audio CODEC combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, stereo digital camcorders, and digital still cameras with either mono or stereo record and playback capability.
  • Page 26 CONTROL INTERFACES To allow full software control over all features, the WM8978 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.

  • Page 27: Input Signal Path

    WM8978, and the stereo signal listened to via headphones, or recorded, simultaneously if required. INPUT SIGNAL PATH The WM8978 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC.
  • Page 28 WM8978 Preliminary Technical Data The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS INPPGAENL Left channel input PGA enable Power 0 = disabled Management 1 = enabled INPPGAENR Right channel input PGA enable 0 = disabled...
  • Page 29 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS INPPGAVOLL 010000 Left channel input PGA volume Left channel 000000 = -12dB input PGA 000001 = -11.25db volume control 010000 = 0dB 111111 = 35.25dB INPPGAMUTEL Mute control for left channel input PGA:...
  • Page 30 WM8978 Preliminary Technical Data Figure 12 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 13. Figure 13 Click Noise During Volume Update In order to prevent this click noise, a zero cross function is provided.
  • Page 31 Preliminary Technical Data Figure 14 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8978 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAUPDATE bit is set as shown in Figure 15.
  • Page 32 WM8978 Preliminary Technical Data AUXILLIARY INPUTS There are two auxilliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs.
  • Page 33 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUXL2BOOSTVOL Controls the auxilliary amplifer to the left channel input boost stage: Left channel Input BOOST 000=Path disabled (disconnected) control 001=-12dB gain through boost stage 010=-9dB gain through boost stage …...

  • Page 34: Analogue To Digital Converter (Adc)

    Figure 17 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8978 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0V Any voltage greater than full scale may overload the ADC and cause distortion.
  • Page 35 WM8978 Preliminary Technical Data Figure 18 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCENL Enable ADC left channel: Power 0 = ADC disabled management 2 1 = ADC enabled...
  • Page 36 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS HPFEN High Pass Filter Enable ADC Control 0=disabled 1=enabled HPFAPP Select audio mode or application mode 0=Audio mode (1 order, fc = ~3.7Hz) 1=Application mode (2 order, fc = HPFCUT) HPFCUT Application mode cut-off frequency See Table 17 for details.
  • Page 37 WM8978 Preliminary Technical Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.

  • Page 38: Input Limiter / Automatic Level Control (Alc)

    Table 19 ADC Digital Volume Control INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8978 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC.
  • Page 39 WM8978 Preliminary Technical Data In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
  • Page 40 WM8978 Preliminary Technical Data The hold, decay and attack times given in Table 20 are constant across sample rates so long as the SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 20 will only be correct if the SR bits are set to 000 (48kHz).
  • Page 41 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCMODE Determines the ALC mode of operation: ALC Control 0=ALC mode 1=Limiter mode ALCDCY 0011 Decay (gain ramp-up) time [3:0] (13ms/6dB) (ALCMODE ==0) 90% of step range 0000 410us 3.3ms 24ms...

  • Page 42: Output Signal Path

    When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8978 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH.
  • Page 43 DIGITAL PLAYBACK (DAC) PATH Digital data is passed to the WM8978 via the flexible audio interface and is then passed through a variety of advanced digital filters (as shown in Figure 21) to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits.
  • Page 44 See the 3-D STEREO ENHANCEMENT section for further details on this feature. DAC DIGITAL OUTPUT LIMITER The WM8978 has a digital output limiter function. The operation of this is shown in Figure 22. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
  • Page 45 WM8978 Preliminary Technical Data Figure 22 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 22, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter.
  • Page 46 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMATK 0010 Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note DAC digital that these will scale proportionally with limiter control sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms...
  • Page 47 WM8978 Preliminary Technical Data LIMLVL Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Table 25 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit.
  • Page 48 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS EQ3G 01100 Band 3 Gain Control. See Table 32 for details. EQ Band 3 (0dB) Control EQ3C Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz EQ3BW Band 3 Bandwidth Control 0=narrow bandwidth...

  • Page 49: 3D Stereo Enhancement

    EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8978 control interface will only allow EQ3DMODE to be changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and DACENR = 0).
  • Page 50 WM8978 Preliminary Technical Data Figure 23 Left/Right Output Channel Mixers PTD Rev 2.6 November 2005...
  • Page 51 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACR2LMIX Right DAC output to left output mixer Output mixer control 0 = not selected 1 = selected DACL2RMIX Left DAC output to right output mixer 0 = not selected 1 = selected...
  • Page 52 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUXR2RMIX Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected AUXRMIXVOL Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB …...
  • Page 53 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUT1ZC Headphone volume zero cross enable: LOUT1 1 = Change gain on zero cross only Volume control 0 = Change gain immediately LOUT1MUTE Left headphone output mute: 0 = Normal operation...
  • Page 54 WM8978 Preliminary Technical Data Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output: Figure 25 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f .
  • Page 55 WM8978 Preliminary Technical Data Figure 26 Speaker Outputs LOUT2 and ROUT2 PTD Rev 2.6 November 2005...
  • Page 56 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUT2ZC Speaker volume zero cross enable: LOUT2 (SPK) 1 = Change gain on zero cross only Volume 0 = Change gain immediately control LOUT2MUTE Left speaker output mute: 0 = Normal operation...
  • Page 57 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPKBOOST 0 = speaker gain = -1; Output control DC = AVDD / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD / 2 BUFDCOPEN Dedicated buffer for DC level shifting output stages when in 1.5x gain...
  • Page 58 WM8978 Preliminary Technical Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 28.
  • Page 59 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT3MUTE 0 = Output stage outputs OUT3 mixer OUT3 mixer 1 = Output stage muted – drives out control VMID. Can be used as VMID buffer in this mode. OUT4_2OUT3 OUT4 mixer output to OUT3...
  • Page 60 WM8978 Preliminary Technical Data Figure 30 Outputs OUT3 and OUT4 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT3BOOST 0 = OUT3 output gain = -1; Output control DC = AVDD / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD / 2 OUT4BOOST 0 = OUT4 output gain = -1;...
  • Page 61 WM8978 Preliminary Technical Data OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: 1. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal will depend upon the route through the mixer path.
  • Page 62 WM8978 Preliminary Technical Data Table 44 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings, output enables etc are not shown).
  • Page 63 Preliminary Technical Data ENABLING THE OUTPUTS Each analogue output of the WM8978 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8978 should remain disabled.
  • Page 64 WM8978 Preliminary Technical Data A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 32. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled.

  • Page 65: Digital Audio Interfaces

    • BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be outputs when the WM8978 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: •...
  • Page 66 WM8978 Preliminary Technical Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
  • Page 67 WM8978 Preliminary Technical Data In DSP/PCM mode, the left channel MSB is available on either the 1 (mode B) or 2 (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
  • Page 68 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MONO Selects between stereo and mono device operation: Audio Interface 0=Stereo device operation Control 1=Mono device operation. Data appears in ‘left’ phase of LRC ADCLRSWAP Controls whether ADC data appears in ‘right’...
  • Page 69 ADC audio interface is fed directly into the DAC data input. COMPANDING The WM8978 supports A-law and µ-law and companding and linear mode on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
  • Page 70 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOOPBACK Digital loopback function Companding 0=No loopback Control 1=Loopback enabled, ADC data output is fed directly into DAC data input. ADC_COMP ADC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law DAC_COMP DAC companding...
  • Page 71 WM8978 Preliminary Technical Data u-law Companding Normalised Input Figure 38 u-Law Companding A-law Companding Normalised Input Figure 39 A-Law Companding PTD Rev 2.6 November 2005...

  • Page 72: Audio Sample Rates

    Preliminary Technical Data AUDIO SAMPLE RATES The WM8978 sample rates for the ADCs and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate.
  • Page 73 WM8978 Preliminary Technical Data Figure 40 PLL and Clock Select Circuit The PLL frequency ratio R = f (see Figure 40) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (2 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz.

  • Page 74: General Purpose Input/Output

    12.288 98.304 7.281778 482296 Table 56 PLL Frequency Examples GENERAL PURPOSE INPUT/OUTPUT The WM8978 has three dual purpose input/output pins. • CSB/GPIO1: CSB / GPIO pin • L2/GPIO2: Left channel line input / headphone detection input • R2/GPIO3: Right channel line input / headphone detection input The GPIO2 and GPIO3 functions are provided for use as jack detection inputs.

  • Page 75: Output Switching (Jack Detect)

    WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPIO1SEL CSB/GPIO1 pin function select: GPIO 000= input (CSB/jack detection: depending on MODE setting) Control 001= reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=logic 0 111=logic 1 GPIO1POL...
  • Page 76 WM8978 Preliminary Technical Data The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings.

  • Page 77: Control Interface

    During a write, once the WM8978 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8978 register address plus the first bit of register data). The WM8978 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e.

  • Page 78: Resetting The Chip

    RESETTING THE CHIP The WM8978 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.

  • Page 79: Power Management

    WM8978 Preliminary Technical Data POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device.

  • Page 80: Register Map

    WM8978 Preliminary Technical Data REGISTER MAP REGISTER DEF’T ADDR NAME B[15:9] DEC HEX (HEX) Software Reset Software reset Power manage’t 1 BUFDCOP OUT4MIX OUT3MIX PLLEN MICBEN BIASEN BUFIOEN VMIDSEL Power manage’t 2 ROUT1EN LOUT1EN SLEEP BOOST BOOST INPPGA INPPGA ADCENR ADCENL Power manage’t 3...
  • Page 81 OUT3 mixer ctrl OUT3 OUT4_ BYPL2 LMIX2 LDAC2 MUTE 2OUT3 OUT3 OUT3 OUT3 OUT4 (MONO) OUT4 HALFSIG LMIX2 LDAC2 BYPR2 RMIX2 RDAC2 mixer ctrl MUTE OUT4 OUT4 OUT4 OUT4 OUT4 Table 63 WM8978 Register Map PTD Rev 2.6 November 2005...

  • Page 82: Register Bits By Address

    WM8978 Preliminary Technical Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER LABEL...
  • Page 83 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS INPPGAENL Left channel input PGA enable Power Management 0 = disabled 1 = enabled ADCENR Enable ADC right channel: Analogue to Digital 0 = ADC disabled Converter 1 = ADC enabled...
  • Page 84 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS DACLRSWAP Controls whether DAC data appears in ‘right’ or Digital Audio ‘left’ phases of LRC clock: Interfaces 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC ADCLRSWAP Controls whether ADC data appears in ‘right’...
  • Page 85 Sets the chip to be master over LRC and BCLK Digital Audio Interfaces 0=BCLK and LRC clock are inputs 1=BCLK and LRC clock are outputs generated by the WM8978 (MASTER) 7 (07h) 00000 Reserved Approximate sample rate (configures the Audio Sample...
  • Page 86 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 9 (09h) JD_VMID [7] VMID_EN_0 Output Switching [8] VMID_EN_1 (Jack Detect) JD_EN Jack Detection Enable Output Switching 0=disabled (Jack Detect) 1=enabled JD_SEL Pin selected as jack detection input Output...
  • Page 87 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13 (0Dh) Reserved JD_EN1 0000 Output enabled when selected jack detection Output input is logic 1 Switching (Jack Detect) [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 JD_EN0 0000...
  • Page 88 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 18 (12h) EQ3DMODE 0 = Equaliser and 3D Enhancement applied to Output Signal ADC path Path 1 = Equaliser and 3D Enhancement applied to DAC path Reserved EQ1C EQ Band 1 Cut-off Frequency:...
  • Page 89 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS EQ5G 01100 EQ Band 5 Gain Control. See Table 32 for Output Signal details. Path 24 (18h) LIMEN Output Signal Enable the DAC digital limiter: Path 0=disabled 1=enabled LIMDCY...
  • Page 90 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 27 (1Bh) Notch filter update. The notch filter values used Analogue to internally only update when one of the NFU bits Digital is set high. Converter (ADC) NFEN Analogue to...
  • Page 91 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS ALCMINGAIN Set minimum gain of PGA Input Limiter/ Automatic 000=-12dB Level Control 001=-6dB (ALC) 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB 33 (21h) ALCHLD 0000 ALC hold time before gain is increased.
  • Page 92 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 0010 ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms … (time doubles with every step) 1010 23.2ms...
  • Page 93 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS BEEPVOL AUXR input to ROUT2 inverter gain Analogue Outputs 000 = -15dB 111 = +6dB BEEPEN 0 = mute AUXR beep input Analogue Outputs 1 = enable AUXR beep input...
  • Page 94 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS INPPGAVOLL 010000 Left channel input PGA volume Input Signal Path 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = 35.25dB 46 (2Eh) INPPGAUPDATE INPPGAVOLL and INPPGAVOLR volume do...
  • Page 95 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS R2_2BOOSTVOL Controls the R2 pin to the right channel input Input Signal boost stage: Path 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage …...
  • Page 96 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS BYPLMIXVOL Left bypass volume contol to output channel Analogue mixer: Outputs 000 = -15dB 001 = -12dB … 101 = 0dB 110 = +3dB 111 = +6dB BYPL2L Left bypass path (from the left channel input...
  • Page 97 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS LOUT1VOL 111001 Left headphone output volume: Analogue Outputs 000000 = -57dB 111001 = 0dB 111111 = +6dB 53 (35h) HPVU LOUT1 and ROUT1 volumes do not update until Analogue...
  • Page 98 WM8978 Preliminary Technical Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS OUT4_2OUT3 OUT4 mixer output to OUT3 Analogue Outputs 0 = disabled 1= enabled BYPL2OUT3 Left ADC input to OUT3 Analogue Outputs 0 = disabled 1= enabled LMIX2OUT3 Left DAC mixer to OUT3...

  • Page 99: Digital Filter Characteristics

    WM8978 Preliminary Technical Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner...

  • Page 100: Dac Filter Responses

    WM8978 Preliminary Technical Data DAC FILTER RESPONSES 3.05 2.95 2.85 2.75 -100 -120 2.65 -140 -160 0.05 0.15 0.25 0.35 0.45 Frequency (fs) Frequency (fs) Figure 43 DAC Digital Filter Frequency Response Figure 44 DAC Digital Filter Ripple (128xOSR) (128xOSR) 3.05...

  • Page 101: Highpass Filter

    Preliminary Technical Data HIGHPASS FILTER The WM8978 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz.

  • Page 102: 5-Band Equaliser

    Preliminary Technical Data 5-BAND EQUALISER The WM8978 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 53 to Figure 66 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of ±12dB, and...
  • Page 103 WM8978 Preliminary Technical Data Frequency (Hz) Frequency (Hz) Figure 58 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure 59 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 Frequency (Hz) Figure 60 EQ Band 3 – EQ3BW=0, EQ3BW=1...
  • Page 104 WM8978 Preliminary Technical Data Frequency (Hz) Frequency (Hz) Figure 61 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BFigure 62 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 Frequency (Hz) Figure 63 EQ Band 4 – EQ3BW=0, EQ3BW=1...
  • Page 105 WM8978 Preliminary Technical Data Figure 66 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.

  • Page 106: Application Information

    WM8978 Preliminary Technical Data APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 67 Recommended External Component Diagram PTD Rev 2.6 November 2005...

  • Page 107: Package Diagram

    WM8978 Preliminary Technical Data PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE 5 0.9 mm BODY, 0.50 mm LEAD PITCH DM033.D DETAIL 1 INDEX AREA EXPOSED (D/2 X E/2) GROUND PADDLE TOP VIEW BOTTOM VIEW 0.08 R = 0.3MM SIDE VIEW...

  • Page 108: Important Notice

    Preliminary Technical Data IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current.

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