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Multichannel CODEC with S/PDIF Transceiver
DESCRIPTION
The WM8581 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8581 is ideal for DVD and surround
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
Integrated into the device is a stereo 24-bit multi-bit sigma
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
Also included are four stereo 24-bit multi-bit sigma delta
DACs,
each
with a dedicated oversampling digital
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
The S/PDIF transceiver is IEC-60958-3 compatible and
supports frame rates from 32k/s to 192k/s. It has four
multiplexed inputs and one output. Status and error
monitoring is built-in and results can reported over the serial
interface or via GPO pins. S/PDIF Channel Block
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
The device is available in a 48-lead TQFP package.
WOLFSON MICROELECTRONICS plc
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FEATURES
•
Mutli-channel CODEC with 4 Stereo DACs and 1 Stereo
ADC
•
Integrated S/PDIF / IEC-60958-3 transceiver
•
Audio Performance
−
103dB SNR ('A' weighted @ 48kHz) DAC
−
-90dB THD (48kHz) DAC
−
100dB SNR ('A' weighted @ 48kHz) ADC
−
-90dB THD (48kHz) ADC
•
DAC Sampling Frequency: 8kHz – 192kHz
•
ADC Sampling Frequency: 8kHz – 192kHz
•
Independent ADC and DAC Sample Rates
•
2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
•
GPO pins allow visibility of user selected status flags
•
Programmable Audio Data Interface Modes
−
2
I
S, Left, Right Justified or DSP
−
16/20/24/32 bit Word Lengths
•
Four independent stereo DAC outputs with independent
digital volume controls
•
Two Independent Master or Slave Audio Data Interfaces
•
Flexible Digital Interface Routing with Clock Selection
Control
•
2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
•
48-lead TQFP Package
APPLICATIONS
•
Digital TV
•
DVD Players and Receivers
•
Surround Sound AV Processors and Hi-Fi systems
•
Automotive Audio
Product Preview, March 2006, Rev 1.0
Copyright 2006 Wolfson Microelectronics plc
WM8581
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Table of Contents
Related Manuals for Wolfson WM8581
Summary of Contents for Wolfson WM8581
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Page 1: Description
DESCRIPTION FEATURES • Mutli-channel CODEC with 4 Stereo DACs and 1 Stereo The WM8581 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8581 is ideal for DVD and surround • sound processing applications for home hi-fi, automotive Integrated S/PDIF / IEC-60958-3 transceiver and other audiovisual equipment. -
Page 2: Block Diagram
WM8581 Product Preview BLOCK DIAGRAM PP Rev 1.0 March 2006... -
Page 3: Table Of Contents
WM8581 Product Preview TABLE OF CONTENTS DESCRIPTION ....................................1 FEATURES ...................................... 1 APPLICATIONS ....................................1 BLOCK DIAGRAM ................................... 2 TABLE OF CONTENTS..................................3 PIN CONFIGURATION..................................4 ORDERING INFORMATION................................4 PIN DESCRIPTION ..................................5 MULTI-FUNCTION PINS................................6 ABSOLUTE MAXIMUM RATINGS ..............................8 RECOMMENDED OPERATING CONDITIONS .......................... -
Page 4: Pin Configuration
WM8581 Product Preview PIN CONFIGURATION ORDERING INFORMATION PEAK TEMPERATURE MOISTURE DEVICE PACKAGE SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE 48-lead TQFP WM8581SEFT/V -25 to +85 MSL1 260°C (Pb-free) 48-lead TQFP WM8581SEFT/RV -25 to +85 MSL1 260°C (Pb-free, tape and reel) PP Rev 1.0 March 2006... -
Page 5: Pin Description
WM8581 Product Preview PIN DESCRIPTION NAME TYPE DESCRIPTION VOUT4L Analogue Output DAC channel 4 left output VOUT4R Analogue Output DAC channel 4 right output PGND Supply PLL ground PVDD Supply PLL positive supply Digital Input Crystal or CMOS clock input... -
Page 6: Multi-Function Pins
MULTI-FUNCTION PINS The WM8581 has 7 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins reconfigured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs have the function shown in column 1 of Table 1. - Page 7 WM8581 Product Preview PIN FUNCTION TYPE DESCRIPTION PAIFTX_BCLK Digital Input/Output Primary Audio Interface Transmitter (PAIFTX) Bit Clock ADCMCLK Digital Input Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs SAIF_DIN Digital Input Secondary Audio Interface (SAIF) Receiver data input...
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Page 8: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. The WM8581 has been classified as MSL1, which has an unlimited floor life at <30 C / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags. -
Page 9: Recommended Operating Conditions
WM8581 Product Preview RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS UNIT Digital supply range DVDD Analogue supply range AVDD, PVDD Ground AGND, VREFN, DGND. PGND Difference DGND to -0.3 +0.3 AGND/PGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. - Page 10 WM8581 Product Preview Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated.
- Page 11 WM8581 Product Preview Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated.
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Page 12: Terminology
WM8581 Product Preview TERMINOLOGY Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). -
Page 13: Digital Audio Interface - Master Mode
WM8581 Product Preview DIGITAL AUDIO INTERFACE – MASTER MODE PAIFRX_BCLK/ PAIFTX_BCLK/ SAIF_BCLK (Output) PAIFRX_LRCLK/ PAIFTX_LRCLK/ SAIF_LRCLK (Outputs) DOUT/ SAIF_DOUT DIN1/2/3/4 SAIF_DIN Figure 2 Digital Audio Data Timing – Master Mode Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, PGND, DGND = 0V, T... -
Page 14: Digital Audio Interface - Slave Mode
WM8581 Product Preview DIGITAL AUDIO INTERFACE – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. -
Page 15: Control Interface Timing - 3-Wire Mode
WM8581 Product Preview CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 SPI Compatible Control Interface Input Timing Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless... - Page 16 WM8581 Product Preview Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SYMBOL UNIT Program Register Input Information SCLK Frequency SCLK Low Pulse-Width...
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Page 17: Device Description
The serial control interface is controlled by pins CSB, SCLK, and SDIN, which are 5V tolerant with TTL input thresholds, allowing the WM8581 to be used with DVDD = 3.3V and be controlled by a controller with 5V output. -
Page 18: Control Interface Operation
Product Preview CONTROL INTERFACE OPERATION Control of the WM8581 is implemented either in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. - Page 19 WM8581 Product Preview REGISTER ADDRESS LABEL DEFAULT DESCRIPTION READMUX Determines which status register is to be read back: READBACK [2:0] 000 = Error Register 001 = Channel Status Register 1 010 = Channel Status Register 2 011 = Channel Status Register 3...
- Page 20 Once the WM8581 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8581 register address plus the first bit of register data). The WM8581 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e.
- Page 21 Product Preview REGISTER READBACK The WM8581 allows readback of certain registers in 2-wire mode. As in 3-wire mode, there are two methods of reading back data: continuous and non-continuous readback. Continuous readback is set by writing to the Readback Control register (see Table 9) to set READEN and CONTREAD to 1, and to set the READMUX bits to select the register to be read back.
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Page 22: Digital Audio Interfaces
SOFTWARE REGISTER RESET Writing to register R53 will cause a register reset, resetting all register bits to their default values. Note that the WM8581 is powered down by default so writing to this register will power down the device. REGISTER... - Page 23 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRX PAIF Rx Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode PAIFTX PAIF Tx Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode SAIFMS SAIF Master/Slave Mode Select:...
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Page 24: Audio Data Formats
LEFT JUSTIFIED MODE In Left Justified mode, the MSB of the input data is sampled by the WM8581 on the first rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the same falling edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. - Page 25 WM8581 Product Preview Figure 15 Right Justified Mode Timing Diagram S MODE In I S mode, the MSB of DIN1/2/3/4 is sampled on the second rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK following an LRCLK transition, and may be sampled on the next rising edge of BCLK.
- Page 26 WM8581 Product Preview For the SAIF receiver, only stereo information is processed. Figure 18 DSP Mode A Timing Diagram - SAIF Receiver Input Data The MSB of the left channel of the output data changes on the first falling edge of BCLK following a low to high LRCLK transition and may be sampled on the rising edge of BCLK.
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Page 27: Audio Interface Control
WM8581 Product Preview Figure 21 DSP Mode B Timing Diagram - SAIF Receiver Input Data The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data. - Page 28 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRXFMT PAIF Receiver Audio Data Format Select PAIF 3 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified PAIFRXWL PAIF Receiver Audio Data Word Length [1:0] 11: 32 bits (see Note 1/2)
- Page 29 WM8581 Product Preview SAIFLRP In LJ/RJ/I S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B SAIFBCP SAIF BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted...
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Page 30: Dac Features
WM8581 Product Preview DAC FEATURES DAC INPUT CONTROL The Primary Audio Interface Receiver has a separate input pin for each stereo DAC. Any input pin can be routed to any DAC using the DACSEL register bits. REGISTER ADDRESS LABEL DEFAULT... - Page 31 WM8581 Product Preview DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio interface are applied to the left and right DACs: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PL[3:0] 1001 PL[3:0] Left O/P...
- Page 32 WM8581 Product Preview INFINITE ZERO DETECT Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Infinite zero detection circuit control and automute control DAC CONTROL 2 0 = Infinite zero detect automute...
- Page 33 1 = Apply gain and update attenuation on all channels. Table 21 Digital Attenuation Registers Note: The volume update circuit of the WM8581 has two sets of registers; LDAx and RDAx. These can be accessed individually, or simultaneously by writing to MASTDA - Master Digital Attenuation.
- Page 34 Table 24 Digital Zero Cross Register MUTE MODES The WM8581 has individual mutes for each of the four DAC channels. Setting DMUTE for a channel will apply a ‘soft-mute’ to the input of the digital filters for that channel. DMUTE[0] mutes DAC1 channel, DMUTE[1] mutes DAC2 channel, DMUTE[2] mutes DAC3 channel and DMUTE[3] mutes DAC4 channel.
- Page 35 WM8581 Product Preview -0.5 -1.5 -2.5 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 23 Application and Release of Mute Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample.
- Page 36 WM8581 Product Preview DAC OUTPUT PHASE The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PHASE 11111111 Controls phase of DAC outputs [7:0] DAC CONTROL 4 0 = non-inverted...
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Page 37: Adc Features
WM8581 Product Preview ADC FEATURES ADC HIGH-PASS FILTER DISABLE The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled. -
Page 38: Digital Routing Options
Product Preview DIGITAL ROUTING OPTIONS The WM8581 has extremely flexible digital interface routing options, which are illustrated in Figure 24. It has a S/PDIF Receiver, S/PDIF Transmitter, four Stereo DACs, a Stereo ADC, a Primary Audio Interface and a Secondary Audio Interface. - Page 39 WM8581 Product Preview The registers described below configure the digital routing options. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DAC_SRC DAC1 Source: [1:0] 00 = S/PDIF received data. 10 = SAIF Rx data 11 = PAIF Rx data Note: When DAC_SRC = 00, DAC2/3/4 may be turned off, depending on RX2DAC_MODE.
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Page 40: Clock Selection
Product Preview CLOCK SELECTION To accompany the flexible digital routing options, the WM8581 offers a clock configuration scheme for each interface. The user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or PLLBCLK. For some interfaces, the rate can be controlled either by external LRCLK (slave mode), internal LRCLK (master mode) or by control register. - Page 41 WM8581 Product Preview ADC INTERFACE The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or ADCMCLK. However, if the S/PDIF receiver is powered up, the PLLACLK and PLLBCLK are invalid for ADC operation, so the choice is limited to ADCMCLK (default) or MCLK. The rate that the ADC operates at is determined by the ADC Rate module.
- Page 42 WM8581 Product Preview S/PDIF INTERFACES The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK. If the digital routing has been configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected.
- Page 43 The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34.
- Page 44 The PAIF Transmitter requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34.
- Page 45 BCLK. These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34. The clock supplied to this module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected using the SAIFMS_CLKSEL register.
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Page 46: Phase-Locked Loops And S/Pdif Clocking (Software Mode)
Product Preview PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE) The WM8581 is equipped with two independent phase-locked loop clock generators and a comprehensive clocking scheme which provides maximum flexibility and function and many configurable routing possibilities for the user in software mode. An overview of the software mode clocking scheme is shown in Figure 31. - Page 47 Table 37 Oscillator Control PHASE-LOCKED LOOP (PLL) The WM8581 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can be used to: •...
- Page 48 WM8581 Product Preview Refer to Table 39 and Table 41 for details of the registers available for configuration in this mode. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PLLA_K[8:0] 100100001 Fractional (K) part of PLLA frequency ratio (R). PLLA 1/ Value K is one 22-digit binary...
- Page 49 WM8581 Product Preview In order to choose and configure the correct values for PLLx_N and PLLx_K, multiplication factor R must first be calculated. Once value R is calculated, the value of PLLx_N is the integer (whole number) value of R, ignoring all digits to the right of the decimal point.
- Page 50 WM8581 Product Preview POSTSCALE_A PLLACLK FREQUENCY 256fs 128fs Table 43 PLL S/PDIF Receiver Mode Clock Divider Configuration PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required PLLBCLK frequency is 12.288MHz.
- Page 51 CLKOUT signal are shown in Table 45. The MCLK pin can be configured as an input or output – the WM8581 should be powered down when switching MCLK between an input and an output. As an output, MCLK can be sourced from OSCCLK, PLLACLK or PLLBCLK.
- Page 52 WM8581 Product Preview S/PDIF RECEIVE MODE CLOCKING In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream. PLLB must be configured to produce a specific reference clock frequency for the S/PDIF receiver.
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Page 53: Phase-Locked Loops And S/Pdif Clocking (Hardware Mode)
WM8581 Product Preview The recommended configuration sequences are as follows: TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP: Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF receiver sample rate operation. -
Page 54: S/Pdif Transceiver
DSP (via the Digital Audio Interfaces), or if the data is audio PCM, it can route the stereo recovered data to DAC1. The recovered clock may be routed out of the WM8581 onto a pin for external use, and may be used to clock the internal DAC as required. -
Page 55: S/Pdif Transmitter
The Channel Status bits form a 192-frame block - transmitted at 1 bit per sub-frame. Each sub-frame forms its own 192-frame block. The WM8581 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8581 is stereo, so the channel status data is duplicated for both channels. - Page 56 WM8581 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS CON/PRO 0 = Consumer Mode 1 = Professional Mode (not supported by SPDTXCHAN 1 WM8581) AUDIO_N 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM.
- Page 57 WM8581 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS SRCNUM 19:16 0000 Source Number. No definitions are attached to data. [3:0] SPDTXCHAN 3 CHNUM1[1:0] 23:20 Channel Number for Subframe 1 CHNUM1 Channel Status Bits[23:20] 0000 = Do not use channel...
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Page 58: S/Pdif Receiver
WM8581 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS MAXWL Maximum Audio sample word length 0 = 20 bits SPDTXCHAN 5 1 = 24 bits TXWL[2:0] 35:33 Audio Sample Word Length. 000 = Word Length Not Indicated TXWL[2:0] MAXWL==1... - Page 59 DAC1. The WM8581 can detect when the data is in a non-compressed audio format and will automatically mute the DAC. See Non-Audio Detection for more detail.
- Page 60 WM8581 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS CATCODE 15:8 Category Code. Refer to S/PDIF specification IEC60958-3 for details. [7:0] SPDRXCHAN 2 00h indicates “general” mode. (read-only) Table 55 S/PDIF Receiver Channel Status Register 2 REGISTER LABEL CHANNEL...
- Page 61 WM8581 Product Preview REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS MAXWL Maximum Audio sample word length 0 = 20 bits SPDRXCHAN 5 1 = 24 bits (read-only) RXWL[2:0] 35:33 Audio Sample Word Length. 000: Word Length Not Indicated RXWL[2:0] MAXWL==1...
- Page 62 WM8581 Product Preview STATUS FLAGS There are several status flags generated by the S/PDIF Receiver, described below. FLAG DESCRIPTION VISIBILITY UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked, or the S/PDIF Status incoming S/PDIF signal is not present.
- Page 63 WM8581 Product Preview HARDWARE INTERRUPT GENERATION (INTB) The hardware interrupt INTB flag (active low) indicates that an event has occurred on UNLOCK, INVALID, TRANS_ERR, NON_AUDIO, CPY_N, DEEMPH, CSUD or REC_FREQ. To determine which flag caused the interrupt, the Interrupt Status Register should be read when INTB is asserted.
- Page 64 Should a TRANS_ERR or INVALID flag be asserted, it is assumed the recovered S/PDIF sub-frame is corrupted or invalid. If either flag is masked using the mask register, the WM8581 will overwrite the recovered frame (i.e. both sub-frames) with either all-zeros or the last valid data sample; depending on how FILLMODE has been set.
- Page 65 S/PDIF INPUT/ GPO PIN CONFIGURATION The WM8581 has seven pins which can be configured as GPOs using the registers shown in Table 65. The GPO pins can be used to output status data decoded by the S/PDIF receiver. These same pins may be used as S/PDIF inputs as described in Table 53.
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Page 66: Powerdown Modes
POWERDOWN MODES The WM8581 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use. -
Page 67: Internal Power On Reset Circuit
INTERNAL POWER ON RESET CIRCUIT Figure 33 Internal Power On Reset Circuit Schematic The WM8581 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a default state after power up. Figure 33 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum threshold Vpor_off. - Page 68 WM8581 Product Preview Figure 34 Typical Power up sequence where DVDD is powered before AVDD Figure 35 Typical Power up sequence where AVDD is powered before DVDD SYMBOL UNIT pora porr pora_off pord_off Table 67 Typical POR Operation In a real application, the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD.
- Page 69 VMID to reach the threshold is a function of the VMID resistor string and the decoupling capacitor. To reduce transient audio effects during power on, the stereo DACs on the WM8581 have their outputs clamped to VMID at power-on. This increases the capacitive loading of the VMID resistor string, as the DAC output AC coupling capacitors must be charged to VMID, and hence the required charge time.
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Page 70: Hardware Control Mode
Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. In Hardware Control Mode the user has limited control over the features of the WM8581. Most of the features will assume their default settings but some can be modified using external pins. - Page 71 WM8581 Product Preview STATUS PINS In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag information. FLAG DESCRIPTION SWMODE UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked or that the input S/PDIF signal is not present.
- Page 72 WM8581 Product Preview PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary Audio Interface transmitter. This has the same operation as the PAIFTX_MS register bit. The PAIFTX_RATE default settings of 256fs, and 64 BCLKs/LRCLK for BCLKSEL, are used in Hardware Control Mode.
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Page 73: Register Map
REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8581 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER... - Page 74 WM8581 Product Preview SPDMODE RXINSEL[1:0] 000111001 SPDIFIN1MODE INTMASK MASK[8:0] 000000000 GPO1 GPO2OP[3:0] GPO1OP[3:0] 000010000 FILLMODE GPO2 GPO4OP[3:0] GPO30P[3:0] 000110010 ALWAYSVALID GPO3 GPO6OP[3:0] GPO5OP[3:0] 001010100 GPO4 GPO70P[3:0] 001110110 Reserved 010011000 INTSTAT Error Flag Interupt Status Register SPDRXCHAN 1 Channel Status Register 1...
- Page 75 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PLLB_K[21:18] 1101 PLLB 3 PLLB_N[3:0] 0111 Integer (N) divisor part of PLLB input/output frequency ratio. Use values greater than 5, less than 13. PRESCALE_B 0 = no pre-scale PLLB 4 1 = divide MCLK by 2 prior to PLLB...
- Page 76 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 4:3 PAIFRX_BCLKSEL Master Mode BCLK Rate [1:0] 00 = 64 BCLKs/LRCLK 01 = 128 BCLKs/LRCLK 10 = 256 BCLKs/LRCLK 11 = BCLK = System Clock PAIFRXMS PAIF Receiver Master/Slave Mode Select 0 = Slave Mode...
- Page 77 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRXFMT PAIF Receiver Audio Data Format Select PAIF 3 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified PAIFRXWL PAIF Receiver Audio Data Word Length [1:0] 11: 32 bits (see Note)
- Page 78 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SAIFFMT SAIF Audio Data Format Select SAIF 2 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified SAIFWL SAIF Audio Data Word Length [1:0] 11: 32 bits (see Note)
- Page 79 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PL[3:0] 1001 PL[3:0] Left O/P Right O/P 0000 Mute Mute CONTROL 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left...
- Page 80 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MUTEALL DAC channel master soft mute. Mutes all DAC channels 0 = disable soft-mute on all DACs 1 = enable soft-mute on all DACs DZCEN DAC Digital Volume Zero Cross Enable 0 = Zero Cross detect disabled...
- Page 81 0 = SPDIFOP pin sources output of S/PDIF Transmitter 1 = SPDIFOP pins sources output of S/PDIF IN Mux CON/PRO 0 = Consumer Mode 1 = Professional Mode (not supported by WM8581) SPDTXCHAN 1 AUDIO_N 0 = S/PDIF transmitted data is audio PCM.
- Page 82 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DEEMPH[2:0] 000 = Data from Audio interface has no pre-emphasis. 001 = Data from Audio interface has pre-emphasis. 010 = Reserved (Audio interface has pre-emphasis). 011 = Reserved (Audio interface has pre-emphasis).
- Page 83 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS RXINSEL[1:0] S/PDIF Receiver input mux select. Note that the general purpose inputs must be configured using GPOxOP to be either CMOS or comparator inputs if selected by RXINSEL. 00 = SPDIFIN1 01 = SPDIFIN2 (MFP3)
- Page 84 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPO3OP[3:0] 0010 0000 = INTB GPO2 0001 = V GPO4OP[3:0] 0011 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD...
- Page 85 CON/PRO 0 = Consumer Mode 1 = Professional Mode SPDRXCHAN 1 The WM8581 is a consumer mode device. Detection of professional mode may give erroneous behaviour. AUDIO_N Recovered S/PDIF Channel status bit 1. 0 = Data word represents audio PCM samples.
- Page 86 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 24 bits 20 bits 21 bits 17 bits All other combinations are reserved and may give erroneous operation. Data will be truncated internally when these bits are set ORGSAMP Original Sampling Frequency. See S/PDIF specification for details.
- Page 87 WM8581 Product Preview REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPDIFPD S/PDIF Clock Recovery PowerDown 0 = S/PDIF enabled 1 = S/PDIF disabled SPDIFTXD S/PDIF Transmitter powerdown 0 = S/PDIF Transmitter enabled 1 = S/PDIF Transmitter disabled SPDIFRXD S/PDIF Receiver powerdown 0 = S/PDIF Receiver enabled...
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Page 88: Digital Filter Characteristics
WM8581 Product Preview DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter ±0.01 dB Passband 0.4535fs -6dB 0.5fs ±0.01 Passband ripple Stopband 0.5465fs Stopband Attenuation f > 0.5465fs DAC Filter ±0.05 dB Passband 0.444fs -3dB 0.487fs ±0.05 Passband ripple Stopband 0.555fs... -
Page 89: Digital De-Emphasis Characteristics
WM8581 Product Preview DIGITAL DE-EMPHASIS CHARACTERISTICS -0.5 -1.5 -2.5 Frequency (kHz) Frequency (kHz) Figure 40 De-Emphasis Frequency Response (32kHz) Figure 41 De-Emphasis Error (32KHz) -0.1 -0.2 -0.3 -0.4 Frequency (kHz) Frequency (kHz) Figure 42 De-Emphasis Frequency Response (44.1KHz) Figure 43 De-Emphasis Error (44.1KHz) -0.2... -
Page 90: Adc Filter Responses
Figure 46 ADC Digital Filter Frequency Response Figure 47 ADC Digital Filter Ripple ADC HIGH PASS FILTER The WM8581 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. 1 - z H(z) = 1 - 0.9995z... -
Page 91: Recommended External Components
WM8581 Product Preview RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components - Hardware PP Rev 1.0 March 2006... - Page 92 WM8581 Product Preview Figure 50 Recommended External Components - Software PP Rev 1.0 March 2006...
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Page 93: Package Dimensions
WM8581 Product Preview PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C Θ Θ Θ Θ A A2 SEATING PLANE ccc C Dimensions Symbols (mm) ----- ----- 1.20 0.05 ----- 0.15 0.95 1.00 1.05 0.17 0.22 0.27... -
Page 94: Important Notice
IMPORTANT NOTICE Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current.
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