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DESCRIPTION
The WM8580 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8580 is ideal for DVD and surround
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
Integrated into the device is a stereo 24-bit multi-bit sigma
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
Also included are three stereo 24-bit multi-bit sigma delta
DACs,
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
The S/PDIF transceiver is IEC-60958-3 compatible and
supports frame rates from 32k/s to 96k/s. It has four
multiplexed inputs and one output. Status and error
monitoring is built-in and results can reported over the serial
interface or via GPO pins. S/PDIF Channel Block
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
The device is available in a 48-lead TQFP package.
WOLFSON MICROELECTRONICS plc
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Multichannel CODEC with S/PDIF Transceiver
each
with a dedicated oversampling digital
at
http://www.wolfsonmicro.com/enews/
FEATURES
•
Multi-channel CODEC with 3 Stereo DACs and 1 Stereo
ADC
•
Integrated S/PDIF / IEC-60958-3 transceiver
•
Audio Performance
−
103dB SNR ('A' weighted @ 48kHz) DAC
−
-90dB THD (48kHz) DAC
−
100dB SNR ('A' weighted @ 48kHz) ADC
−
-87dB THD (48kHz) ADC
•
DAC Sampling Frequency: 8kHz – 192kHz
•
ADC Sampling Frequency: 8kHz – 192kHz
•
Independent ADC and DAC Sample Rates
•
2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
•
GPO pins allow visibility of user selected status flags
2
S, Left
•
Programmable Audio Data Interface Modes
2
−
I
S, Left, Right Justified or DSP
−
16/20/24/32 bit Word Lengths
•
Three Independent Stereo DAC Outputs with Digital
Volume Controls
•
Two Independent Master or Slave Audio Data Interfaces
•
Flexible Digital Interface Routing with Clock Selection
Control
•
2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
•
48-lead TQFP Package
APPLICATIONS
•
Digital TV
•
DVD Players and Receivers
•
Surround Sound AV Processors and Hi-Fi systems
•
Automotive Audio
Copyright ©2009 Wolfson Microelectronics plc
WM8580
Production Data, March 2009, Rev 4.7
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Table of Contents
Related Manuals for Wolfson WM8580
Summary of Contents for Wolfson WM8580
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Page 1: Description
DESCRIPTION FEATURES • Multi-channel CODEC with 3 Stereo DACs and 1 Stereo The WM8580 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8580 is ideal for DVD and surround sound processing applications for home hi-fi, automotive • Integrated S/PDIF / IEC-60958-3 transceiver and other audiovisual equipment. -
Page 2: Block Diagram
WM8580 Production Data BLOCK DIAGRAM PD, Rev 4.7, March 2009 Downloaded from Elcodis.com electronic components distributor... -
Page 3: Table Of Contents
WM8580 Production Data TABLE OF CONTENTS DESCRIPTION .......................1 FEATURES......................1 APPLICATIONS .....................1 BLOCK DIAGRAM ....................2 TABLE OF CONTENTS ..................3 PIN CONFIGURATION...................4 ORDERING INFORMATION ..................4 PIN DESCRIPTION ....................5 MULTI-FUNCTION PINS....................6 ABSOLUTE MAXIMUM RATINGS.................8 RECOMMENDED OPERATING CONDITIONS .............9 ELECTRICAL CHARACTERISTICS ..............9 TERMINOLOGY ......................12 MASTER CLOCK TIMING ................... -
Page 4: Pin Configuration
WM8580 Production Data PIN CONFIGURATION ORDERING INFORMATION PEAK TEMPERATURE MOISTURE DEVICE PACKAGE SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE 48-lead TQFP WM8580AGEFT/V -40 to +85 MSL2 260°C (Pb-free) 48-lead TQFP WM8580AGEFT/RV -40 to +85 MSL2 260°C (Pb-free, tape and reel) Note: Reel quantity = 2,200 PD, Rev 4.7, March 2009... -
Page 5: Pin Description
WM8580 Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION PGND Supply PLL ground PVDD Supply PLL positive supply Digital Input Crystal or CMOS clock input Digital Output Crystal output MFP10 Digital Output Multi-Function Pin (MFP) 10. See Table 1 for details of all MFP pins. -
Page 6: Multi-Function Pins
In hardware control mode, pin 31 is used for NON_AUDIO flag output. MULTI-FUNCTION PINS The WM8580 has 8 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins are configured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs have the function shown in column 1 of Table 1. - Page 7 WM8580 Production Data Notes for MFP1: ADC_CLKSEL selected in REG 8, default is ADC_MCLK. PAIFTXMS_CLKSEL selects PLLACLK if PAIF sources SPDIF Rx, otherwise PAIFTXMS_CLKSEL selects ADC_CLK (register 8) MFP2 usage can be described as follows: (ADC_CLKSEL ≠ ADCMCLK) (controlled by reg 8) (TX_CLKSEL ≠...
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Page 8: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. The WM8580 has been classified as MSL1, which has an unlimited floor life at <30 C / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags. -
Page 9: Recommended Operating Conditions
WM8580 Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS UNIT Digital supply range DVDD Analogue supply range AVDD PLL supply range PVDD Ground AGND, VREFN, DGND. PGND Difference DGND to -0.3 +0.3 AGND/PGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. - Page 10 WM8580 Production Data Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24- Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated.
- Page 11 WM8580 Production Data Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T = +25 C, 1kHz Signal, fs = 48kHz, 24- Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V Input Signal Level unless otherwise stated.
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Page 12: Terminology
WM8580 Production Data TERMINOLOGY Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). -
Page 13: Digital Audio Interface - Master Mode
WM8580 Production Data DIGITAL AUDIO INTERFACE – MASTER MODE PAIFRX_BCLK/ PAIFTX_BCLK/ SAIF_BCLK (Output) PAIFRX_LRCLK/ PAIFTX_LRCLK/ SAIF_LRCLK (Outputs) DOUT/ SAIF_DOUT DIN1/2/3 SAIF_DIN Figure 2 Digital Audio Data Timing – Master Mode Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, PGND, DGND = 0V, T... -
Page 14: Digital Audio Interface - Slave Mode
WM8580 Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE PAIFTX_BCLK/ PAIFRX_BCLK/ SAIF_BCLK PAIFTX_LRCLK/ PAIFRX_LRCLK/ SAIF_BCLK LRSU DIN1/2/3/ SAIF_DIN DOUT/ SAIF_DOUT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, T... -
Page 15: Control Interface Timing - 3-Wire Mode
WM8580 Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 SPI Compatible Control Interface Input Timing Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless... -
Page 16: Control Interface Timing - 2-Wire Mode
WM8580 Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T = +25 C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless... -
Page 17: Device Description
The serial control interface is controlled by pins CSB, SCLK, and SDIN, which are 5V tolerant with TTL input thresholds, allowing the WM8580 to be used with DVDD = 3.3V and be controlled by a controller with 5V output. SDO allows status registers to be read back over the serial interface (SDO is not 5V tolerant). -
Page 18: Control Interface Operation
Production Data CONTROL INTERFACE OPERATION Control of the WM8580 is implemented either in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. - Page 19 WM8580 Production Data With CONTREAD set, a single read-only register can be read back by writing to any other register or to a dummy register. The register to be read is determined by the READMUX[2:0] bits. When a write to the device is performed, the device will respond by returning the status byte in the register selected by the READMUX register bits.
- Page 20 SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8580 returns to the idle condition and wait for a new start condition and valid address. Once the WM8580 has acknowledged a correct address, the controller sends the first byte of control data (REGA(6:0), i.e.
- Page 21 Production Data REGISTER READBACK The WM8580 allows readback of certain registers in 2-wire mode, with data output on the SDO pin. As in 3-wire mode, there are two methods of reading back data: continuous and non-continuous readback. Continuous readback is set by writing to the Readback Control register (see Table 9) to set READEN and CONTREAD to 1, and to set the READMUX bits to select the register to be read back.
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Page 22: Digital Audio Interfaces
Production Data DIGITAL AUDIO INTERFACES Audio data is transferred to and from the WM8580 via the digital audio interfaces. There are two receive audio interfaces and two transmit audio interfaces. The digital routing options for these interfaces are described on page 22. Control of the audio interfaces is described below. - Page 23 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRX PAIF Receiver Master/Slave Mode Select: PAIF 1 0 = Slave Mode 1 = Master Mode PAIFTX PAIF Transmitter Master/Slave Mode Select: 0 = Slave Mode PAIF 2 1 = Master Mode...
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Page 24: Audio Data Formats
WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFRX_BCLKSEL Master Mode BCLK Rate: PAIF 1 [1:0] 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK PAIFTX_BCLKSEL 11 = BCLK = System Clock. - Page 25 LEFT JUSTIFIED MODE In Left Justified mode, the MSB of the input data is sampled by the WM8580 on the first rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the same falling edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK.
- Page 26 WM8580 Production Data S MODE In I S mode, the MSB of DIN1/2/3 is sampled on the second rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK following an LRCLK transition, and may be sampled on the next rising edge of BCLK.
- Page 27 WM8580 Production Data The MSB of the left channel of the output data changes on the first falling edge of BCLK following a low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data.
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Page 28: Audio Interface Control
WM8580 Production Data The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data. - Page 29 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFTXFMT PAIF Transmitter Audio Data Format Select PAIF 4 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified PAIFTXWL PAIF Transmitter Audio Data Word Length [1:0] 11: 32 bits (see Note 1,2)
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Page 30: Dac Features
WM8580 Production Data In 24 bit I S mode, any data width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit clocks occur in one full left/right clock period the interface will auto detect and configure a 16 bit data word length. - Page 31 WM8580 Production Data DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio interface are applied to the left and right DACs: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PL[3:0] 1001 PL[3:0] Left O/P...
- Page 32 WM8580 Production Data INFINITE ZERO DETECT Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Infinite zero detection circuit control and automute control DAC Control 2 0 = Infinite zero detect automute...
- Page 33 1 = Apply gain and update attenuation on all channels. Table 22 Digital Attenuation Registers Note: The volume update circuit of the WM8580 has two sets of registers; LDAx and RDAx. These can be accessed individually, or simultaneously by writing to MASTDA – Master Digital Attenuation.
- Page 34 WM8580 Production Data L/RDAx[7:0] GAIN LEVEL 00(hex) -∞ dB (mute) 01(hex) -127.5dB FE(hex) -0.5dB FF(hex) Table 23 Digital Volume Control Gain Levels Setting the DACATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for DACATC to take effect.
- Page 35 Production Data MUTE MODES The WM8580 has individual mutes for each of the three DAC channels. Setting DMUTE for a channel will apply a ‘soft-mute’ to the input of the digital filters for that channel. DMUTE[0] mutes DAC1 channel, DMUTE[1] mutes DAC2 channel and DMUTE[2] mutes DAC3 channel. Setting the MUTEALL register bit will apply a ‘soft-mute’...
- Page 36 WM8580 Production Data -0.5 -1.5 -2.5 0.001 0.002 0.003 0.004 0.005 0.006 Time(s) Figure 23 Application and Release of Mute PD, Rev 4.7, March 2009 Downloaded from Elcodis.com electronic components distributor...
- Page 37 WM8580 Production Data DMUTE(2:0) DACPD(2:0) PL(3:0) MUTEALL DZFM (2:0) DAC_SRC[1:0] = 00 S/PDIF Rx Data MUTE PCM_N or (register) AUDIO_N = 1 Decode MPDENB MUTE (pin) DZFM Channel 1 Selector Softmute Channel 2 Softmute Channel 3 Softmute zflag1 DAC1 i/p...
- Page 38 WM8580 Production Data Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards V with a time constant of approximately 64 input samples.
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Page 39: Adc Features
WM8580 Production Data ADC FEATURES ADC HIGH-PASS FILTER DISABLE The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled. -
Page 40: Digital Routing Options
Production Data DIGITAL ROUTING OPTIONS The WM8580 has extremely flexible digital interface routing options, which are illustrated in Figure 25. It has S/PDIF Receiver, S/PDIF Transmitter, 3 Stereo DACs, a Stereo ADC, a Primary Audio Interface and a Secondary Audio Interface. - Page 41 WM8580 Production Data The registers described below configure the digital routing options. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DAC_SRC DAC1 Source: PAIF 3 [1:0] 00 = S/PDIF received data. 10 = SAIF Receiver data 11 = PAIF Receiver data Note: When DAC_SRC = 00, DAC2/3 may be turned off, depending on RX2DAC_MODE.
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Page 42: Clock Selection
Production Data CLOCK SELECTION To accompany the flexible digital routing options, the WM8580 offers a similar flexible clock configuration capability. The user can chose which clock drives each of the main functional blocks. In general the choice of clock is between MCLK, ADCMCLK, PLLACLK and PLLBCLK, with some restrictions dependant upon the digital routing configuration. - Page 43 WM8580 Production Data It is possible to override any autoconfiguration of clocks, allowing the user to manually select an available clock for a particular interface using the appropriate CLKSEL register bits. The autoconfiguration can be overridden using the CLKSEL_MAN bit (Reg6, bit 6). Great care must to used when overriding autoconfigured clocking.This is described in Manual Clock Selection section.
- Page 44 WM8580 Production Data DAC Data Source Clock used for DAC Comments rate Generator (fs) DAC1 =PAIFRX PAIFRX_LRCLK DAC sample rate based on PAIF Rx DAC1=SAIFRX SAIFRX_LRCLK DAC sample rate based on SAIF Rx DAC1=S/PDIFRX SFRM_CLK or RX2DAC_MODE bit selects between the...
- Page 45 Table 36 ADC Rate Selection The ADC_CLK clock source can be independent from the DACs and PLLs, however for optimum performance it is recommended that clock sources on the WM8580 are synchronous. If this condition is not met performance may be degraded.
- Page 46 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADC_CLKSEL ADC clock source CLKSEL 00 = ADCMCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin ADCRATE[2:0] ADC Rate Control (only used when the S/PDIF Transmitter is the only...
- Page 47 WM8580 Production Data S/PDIF INTERFACES The TX_CLKSEL register selects S/PDIF Transmitter clock, TX_CLK, from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. Figure 28 illustrates how the clock is selected. The S/PDIF Receiver only uses PLLACLK, but both PLLACLK and PLLBCLK are unavailable in user mode when the S/PDIF receiver is active.
- Page 48 PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX) The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). Register R9, bit 5 selects master or slave mode.
- Page 49 The SAIF Transmit and Receive interfaces share a common LRCLK and a common BCLK. These can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode). Register R11, bit 5 selects master or slave mode.
- Page 50 WM8580 Production Data In master mode the BCLK and LRCLK driving the SAIF interface are generated by the Master Mode Clock Gen module. The control of this module is described on page 22. The clock supplied to the Master Mode Clock Gen module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK.
- Page 51 WM8580 Production Data MANUAL CLOCK SELECTION It is possible to override all default clocking configuration restrictions by setting CLKSEL_MAN. When CLKSEL_MAN is set, default clocking configurations such as automatic selection of PLLACLK for DAC1 when DACSRC=00 (S/PDIF received data) are not applied. Instead, clock selection is determined only by the relevant CLK_SEL register.
- Page 52 WM8580 Production Data Figure 35 Manual Clock Over-ride of PAIF Tx Figure 36 Manual Clock Over-ride of PAIF Rx Figure 37 Manual Clock Over-ride of SAIF PD, Rev 4.7, March 2009 Downloaded from Elcodis.com electronic components distributor...
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Page 53: Phase-Locked Loops And S/Pdif Clocking (Software Mode)
The oscillator circuit contains a bias generator within the WM8580 and hence an external bias resistor is not required. Crystal frequencies between 10 and 14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT must be powered up using the OSCPD bit. - Page 54 Table 45 Oscillator Control PHASE-LOCKED LOOP (PLL) The WM8580 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can be used to: •...
- Page 55 WM8580 Production Data • PLL User Mode (Selected if S/PDIF Receiver Disabled) In user mode, the user has full control over the function and operation of both PLLA and PLLB. In this mode, the user can accurately specify the PLL N and K multiplier values and the pre and post- scale divider values and can hence fully control the generated clock frequencies.
- Page 56 WM8580 Production Data PLL CONFIGURATION The PLLs perform a configurable frequency multiplication of the input clock signal (f ). The multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f ÷...
- Page 57 WM8580 Production Data FREQMODE_x[1:0] TO PLLxCLK DIVISION FACTOR POSTSCALE_x ÷2 ÷4 ÷4 ÷8 ÷8 ÷16 ÷12 ÷24 Table 50 PLL User Mode Clock Divider Configuration POSTSCALE_A PLLACLK FREQUENCY 256fs 128fs Table 51 PLL S/PDIF Receiver Mode Clock Divider Configuration PLL CONFIGURATION EXAMPLE Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required PLLBCLK frequency is 12.288MHz.
- Page 58 CLKOUT signal are shown in Table 53. The MCLK pin can be configured as an input or output – the WM8580 should be powered down when switching MCLK between an input and an output. As an output, MCLK can be sourced from OSCCLK, PLLACLK or PLLBCLK.
- Page 59 WM8580 Production Data S/PDIF RECEIVE MODE CLOCKING In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream.
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Page 60: Phase-Locked Loops And S/Pdif Clocking (Hardware Mode)
DSP (via the Digital Audio Interfaces), or if the data is audio PCM, it can route the stereo recovered data to DAC1. The recovered clock may be routed out of the WM8580 onto a pin for external use, and may be used to clock the internal DAC as required. - Page 61 WM8580 Production Data Frame Frame ..Subframe 1 Subframe 2 27 28 32 bit Sync Audio Sample Word preamble Word Figure 39 S/PDIF Format S/PDIF TRANSMITTER The S/PDIF transmitter generates the S/PDIF frames, and outputs on the SPDIFOP pin. The audio data for the frame can be taken from one of four sources, selectable using the TXSRC register.
- Page 62 The Channel Status bits form a 192 frame –lock - transmitted at one bit per sub-frame. Each sub- frame forms its own 192-frame block. The WM8580 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8580 is stereo, so the channel status data is duplicated for both channels.
- Page 63 WM8580 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS CATCODE 15:8 00000000 Category Code. Refer to S/PDIF specification IEC60958-3 for details. [7:0] SPDTXCHAN 2 00h indicates “general” mode. Table 57 S/PDIF Transmitter Channel Status Bit Control 2 REGISTER LABEL...
- Page 64 WM8580 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS BIT MAXWL Maximum Audio sample word length 0 = 20 bits SPDTXCHAN 5 1 = 24 bits TXWL[2:0] 35:33 Audio Sample Word Length. 000 = Word Length Not Indicated TXWL[2:0]...
- Page 65 DAC1. The WM8580 can detect when the data is in a non-compressed audio format and will automatically mute the DAC. See Non-Audio Detection section for more detail.
- Page 66 When the audio data sample is transferred to the AIF, and if the AIF is operating in a mode which has less data bits, then the WM8580 will reduce the audio data sample to the length of the AIF. For example, if the AIF is operating in 16 bit mode, but the SPDIF Rx receives an audio data sample length of 21 bits, then the WM8580 will reduce the 21 bits to 16 bits by removing the LSBs.
- Page 67 WM8580 Production Data REGISTER LABEL CHANNEL DEFAULT DESCRIPTION ADDRESS STATUS SRCNUM 19:16 Indicates S/PDIF source number. [3:0] Refer to S/PDIF specification IEC60958-3 for SPDRXCHAN 3 details. CHNUM1[1:0] 21:20 Channel number for sub-frame 1. (read-only) 00 = Take no account of channel number...
- Page 68 WM8580 Production Data STATUS FLAGS There are several status flags generated by the S/PDIF Receiver, described below. FLAG DESCRIPTION VISIBILITY UNLOCK Indicates that the S/PDIF Clock Recovery circuit is unlocked, or the S/PDIF Status incoming S/PDIF signal is not present.
- Page 69 WM8580 Production Data INTERRUPT GENERATION (INT_N) The hardware interrupot INT_N flag (active low) indicates that a change of status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, NON_AUDIO, CPY_N, DEEMPH, CSUD or REC_FREQ flags. To determine which flag caused the interrupt, the Interrupt Status Register (INTSTAT) should be read when INT_N is asserted.
- Page 70 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUDIO_N Linear PCM Identification SPDSTAT 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. (read-only) PCM_N Indicates that non-audio code (defined in IEC-61937) has been detected.
- Page 71 AUTOMATIC ERROR HANDLING This automatic handling of errored Rx S/PDIF data can be used when an application processor is not being interrupted via the INT_N signal leaving the WM8580 to handle the error condition. If the TRANS_ERR and INVALID error flags are masked using the MASK register, the WM8580 output data from the S/PDIF Rx interface depends on the setting of FILLMODE.
- Page 72 S/PDIF INPUT/ GPO PIN CONFIGURATION The WM8580 has ten pins which can be configured as GPOs using the registers shown in Table 72. The GPO pins can be used to output status data decoded by the S/PDIF receiver. These same pins may be used as S/PDIF inputs as described in Table 61.
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Page 73: Powerdown Modes
Production Data POWERDOWN MODES The WM8580 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use. - Page 74 WM8580 Production Data REGISTER ADDRESS LABEL DEFAULT DESCRIPTION PWDN Master powerdown (overrides all powerdown registers) PWRDN 1 0 = All digital circuits running, outputs are active 1 = All digital circuits in power down mode, outputs muted ADCPD ADC powerdown...
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Page 75: Internal Power On Reset Circuit
INTERNAL POWER ON RESET CIRCUIT Figure 40 Internal Power On Reset Circuit Schematic The WM8580 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a default state after power up. Figure 40 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. - Page 76 WM8580 Production Data Figure 41 Typical Power up Sequence where DVDD is Powered before AVDD Figure 42 Typical Power up Sequence where AVDD is Powered before DVDD SYMBOL UNIT pora porr pora_off pord_off Table 74 Typical POR Operation In a real application, the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD.
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Page 77: Hardware Control Mode
Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. In Hardware Control Mode the user has limited control over the features of the WM8580. Most of the features will assume their default settings but some can be modified using external pins. - Page 78 WM8580 Production Data S/PDIF TRANSMITTER DATA SOURCE S/PDIF received data ADC digital output data PAIF receiver data Table 77 DR3 / DR4 Operation The Secondary Audio Interface (SAIF) is not operational in Hardware Mode. STATUS PINS In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag information.
- Page 79 WM8580 Production Data DESCRIPTION MUTE Normal Operation Mute DAC channels Floating MUTE is an output to indicate when Zero Detection occurs on all DACs (ZFLAG). H = detected, L = not detected. Table 80 MUTE Pin Control Options PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary Audio Interface transmitter.
- Page 80 WM8580 Production Data SLAVE MODE If the S/PDIF Rx interface is enabled, then an internal MCLK is generated at 256fs. This internal clock will act as a source clock for ADC, DACs and PAIF. The user is required to supply input clocks to the PAIFTX_BCLK and the PAIF_LRCLK.
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Page 81: Register Map
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8580 can be configured using the Control Interface. All unused bits should be set to ‘0’. Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers can be read. - Page 82 WM8580 Production Data REGISTER NAME ADDRESS DEFAULT GPO2 GPO4OP[3:0] GPO30P[3:0] 000110010 ALWAYSVALID GPO3 GPO6OP[3:0] GPO5OP[3:0] 001010100 GPO4 GPO8OP[3:0] GPO70P[3:0] 001110110 GPO5 GPO10OP[3:0] GPO9OP[3:0] 010011000 INTSTAT Error Flag Interupt Status Register Read-only SPDRXCHAN 1 Channel Status Register 1 Read-only SPDRXCHAN 2...
- Page 83 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PLLB_K[8:0] 100100001 Fractional (K) part of PLLB freqIcy ratio (R). PLLB 1 Value K is one 22-digit binary number spread over registers R4, R5 and R6 as shown. Note: PLLB_K must be set to specific values when the S/PDIF...
- Page 84 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS TX_CLKSEL S/PDIF Transmitter clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin CLKSEL_MAN Clock selection auto-configuration override 0 = auto-configuration enabled 1 = auto-configuration disabled, clock configuration follows relevant CLKSEL bits in R8 to R11.
- Page 85 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SAIF_RATE Master Mode LRCLK Rate SAIF1 [2:0] 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs SAIF_BCLKSEL Master Mode BCLK Rate...
- Page 86 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PAIFTXFMT PAIF Transmitter Audio Data Format Select PAIF 4 [1:0] 11: DSP Format 10: I S Format 01: Left justified 00: Right justified PAIFTXWL PAIF Transmitter Audio Data Word Length [1:0] 11: 32 bits (see Note)
- Page 87 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DAC1SEL DAC digital input select [1:0] 00 = DAC takes data from DIN1 Control 1 01 = DAC takes data from DIN2 DAC2SEL 10 = DAC takes data from DIN3 [1:0] DAC3SEL...
- Page 88 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS PHASE [5:0] 111111 Controls phase of DAC outputs PHASE[0] = 0 inverts phase of DAC1L output Control 4 PHASE[1] = 0 inverts phase of DAC1R output PHASE[2] = 0 inverts phase of DAC2L output...
- Page 89 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS Attenuation UPDATE Not latched Controls simultaneous update of all Attenuation Latches DACR 3 0 = Store RDA3 in intermediate latch (no change to output) 1 = Apply RDA3 and update attenuation on all channels...
- Page 90 0 = transmit validity = 0 1 = transmit validity = 1 CON/PRO 0 = Consumer Mode 1 = Professional Mode (not supported by WM8580) SPDTXCHAN 1 AUDIO_N 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM.
- Page 91 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 23 bits 19 bits 24 bits 20 bits 21 bits 17 bits All other combinations reserved ORGSAMP 0000 Original Sampling Frequency. See S/PDIF specification for details. [3:0] 0000 = original sampling frequency not indicated...
- Page 92 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS FILLMODE Fill Mode Overwrite Configuration Determines S/PDIF receiver action when TRANS_ERR or INVALID flag is masked and error condition sets the flag: 0 = Data from S/PDIF receiver is overwritten with last valid data sample when flag is set.
- Page 93 1 = INT_N caused by update to REC_FREQ flag CON/PRO 0 = Consumer Mode 1 = Professional Mode SPDRXCHAN 1 The WM8580 is a consumer mode device. Detection of professional mode may give erroneous behaviour. AUDIO_N Linear PCM Identification 0 = Data word represents audio PCM samples.
- Page 94 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS CLKACU[1:0] Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. MAXWL Maximum Audio sample word length...
- Page 95 WM8580 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACPD[2:0] DAC powerdowns (0 = DAC enabled, 1 = DAC disabled) DACPD[0] = DAC1 DACPD[1] = DAC2 DACPD[2] = DAC3 ALLDACPD Overrides DACPD[3:0] 0 = DACs under control of DACPD[3:0] 1= All DACs are disabled.
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Page 96: Digital Filter Characteristics
WM8580 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband ±0.01 dB 0.4535fs -6dB 0.5fs Passband ripple ±0.01 Stopband 0.5465fs Stopband Attenuation f > 0.5465fs DAC Filter Passband ±0.05 dB 0.444fs -3dB 0.487fs Passband ripple ±0.05 Stopband 0.555fs... -
Page 97: Dac Filter Responses
WM8580 Production Data DAC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -120 -0.2 0.05 0.15 0.25 0.35 0.45 Frequency (Fs) Frequency (Fs) Figure 43 DAC Digital Filter Frequency Response Figure 44 DAC Digital Filter Ripple –44.1, 48 and 96kHz –... -
Page 98: Digital De-Emphasis Characteristics
WM8580 Production Data DIGITAL DE-EMPHASIS CHARACTERISTICS -0.1 -0.2 -0.3 -0.4 Frequency (kHz) Frequency (kHz) Figure 47 De-Emphasis Frequency Response (44.1kHz) Figure 48 De-Emphasis Error (44.1kHz) -0.2 -0.4 -0.6 -0.8 Frequency (kHz) Frequency (kHz) Figure 49 De-Emphasis Frequency Response (48kHz) Figure 50 De-Emphasis Error (48kHz) ADC FILTER RESPONSES 0.02... -
Page 99: Adc High Pass Filter
WM8580 Production Data ADC HIGH PASS FILTER The WM8580 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. 1 - z H(z) = 1 - 0.9995z 0.0005 0.001 0.0015 0.002... -
Page 100: Applications Information
WM8580 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 54 Recommended External Components PD, Rev 4.7, March 2009 Downloaded from Elcodis.com electronic components distributor... - Page 101 WM8580 Production Data Figure 55 Recommended External Components PD, Rev 4.7, March 2009 Downloaded from Elcodis.com electronic components distributor...
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Page 102: Package Dimensions
WM8580 Production Data PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C Θ A A2 ccc C SEATING PLANE Dimensions Symbols (mm) ----- ----- 1.20 0.05 ----- 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----- 0.20... -
Page 103: Important Notice
Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
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