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Wolfson WM8758 Manual

Stereo codec with headphone driver and line out
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Stereo CODEC with Headphone Driver and Line Out

DESCRIPTION

The WM8758B is a low power, high quality stereo CODEC
designed for portable applications such as MP3 audio player.
The device integrates preamps for stereo differential mics, and
drivers for headphone and differential or stereo line output.
External component requirements are reduced as no separate
microphone or headphone amplifiers are required. Headphone
and line common feedback improves crosstalk and noise
performance.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as 'wind noise reduction' and notch
filter.
The WM8758B digital audio interface can operate in master or
slave mode with an integrated PLL.
The WM8758B operates at analogue supply voltages from 2.5V
to 3.3V, although the digital supply voltages can operate at
voltages down to 1.71V to save power. Additional power
management control enables individual sections of the chip to
be powered down under software control.

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc
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http://www.wolfsonmicro.com/enews

FEATURES

Stereo CODEC:
DAC SNR 100dB, THD -86dB ('A' weighted @ 48kHz)
ADC SNR 92.5dB, THD -75dB ('A' weighted @ 48kHz)
Headphone Driver
40mW per channel output power into 16 / 3.3V AVDD2
Line output
Mic Preamps:
Stereo Differential or mono microphone Interfaces
Programmable preamp gain
Psuedo differential inputs with common mode rejection
Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
Other Features:
Enhanced 3-D function for improved stereo separation
Digital playback limiter
5-band Equaliser (record or playback)
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
PLL supporting various clocks between 8MHz-50MHz
Sample rates supported (kHz): 8, 11.025, 12, 16, 22.05, 24,
32, 44.1, 48
Low power, low voltage
2.5V to 3.6V analogue supplies
1.71V to 3.6V digital supplies
5x5mm 32-lead QFN package

APPLICATIONS

Portable audio player
Production Data, January 2012, Rev 4.4
Copyright 2012 Wolfson Microelectronics plc
WM8758B

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Summary of Contents for Wolfson WM8758

  • Page 1: Description

     5x5mm 32-lead QFN package APPLICATIONS BLOCK DIAGRAM  Portable audio player Production Data, January 2012, Rev 4.4 WOLFSON MICROELECTRONICS plc Copyright 2012 Wolfson Microelectronics plc To receive regular email updates, sign up http://www.wolfsonmicro.com/enews...

  • Page 2: Table Of Contents

    WM8758B Production Data TABLE OF CONTENTS DESCRIPTION ....................... 1 BLOCK DIAGRAM ....................1 FEATURES ......................1 APPLICATIONS ..................... 1 TABLE OF CONTENTS ..................2 PIN CONFIGURATION ..................4 ORDERING INFORMATION .................. 4 PIN DESCRIPTION ....................5 RECOMMENDED OPERATING CONDITIONS ............. 6 ELECTRICAL CHARACTERISTICS ..............
  • Page 3 WM8758B Production Data APPLICATIONS INFORMATION ................ 87 RECOMMENDED EXTERNAL COMPONENTS ............87 PACKAGE DIAGRAM ..................88 IMPORTANT NOTICE ..................89 ADDRESS: ........................89 PD, Rev 4.4, January 2012...

  • Page 4: Pin Configuration

    WM8758B Production Data PIN CONFIGURATION AGND2 ROUT2 OUT3 L2/GPIO2 OUT4 TOP VIEW LINE_COM R2/GPIO3 HP_COM MODE SDIN BCLK ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE PEAK SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE WM8758CBGEFL/V -40C to +85C 32-lead QFN (5 x 5 mm) MSL3 (Pb-free) WM8758CBGEFL/RV...

  • Page 5: Pin Description

    WM8758B Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION Analogue Input Left MIC pre-amp positive input Analogue Input Left MIC pre-amp negative input Analogue Input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin L2/GPIO2 Analogue Input Right MIC pre-amp positive input Analogue Input Right MIC pre-amp negative input R2/GPIO3...

  • Page 6: Recommended Operating Conditions

    Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity.

  • Page 7: Electrical Characteristics

    WM8758B Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2) Full-scale Input Signal Level – PGABOOST = 0dB AVDD1/3.3 Vrms...
  • Page 8 WM8758B Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Analogue to Digital Converter (ADC) - Input from LIN/P and RIN/P, PGA and boost gains=0dB Signal to Noise Ratio (Note 5,6) A-weighted 92.5...
  • Page 9 WM8758B Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT DAC to L/R Mix to Line-Out (LOUT1/ROUT1 with 10k / 50pF load, analogue volume controls set to 0dB) Full-scale output PGA gains set to 0dB AVDD1/3.3...
  • Page 10 WM8758B Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT DAC to L/R Mix to Headphone (LOUT1/ROUT1, analogue volume controls set to 0dB) Full-scale output PGA gains set to 0dB AVDD1/3.3...
  • Page 11 WM8758B Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT MIC PGA to Input Boost to OUT3/OUT4 outputs (with 10k / 50pF load) Full-scale output voltage, 0dB AVDD2/3.3 Vrms...

  • Page 12: Terminology

    WM8758B Production Data Test Conditions DCVDD=1.8V, AVDD1=AVDD2=3.0V, DBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Bias Bias Voltage MBVSEL=0 0.9*AVDD1 MICBIAS MBVSEL=1 0.65*AVDD1 Bias Current Source for V within +/-3% MICBIAS...

  • Page 13: Headphone Output Performance

    WM8758B Production Data HEADPHONE OUTPUT PERFORMANCE SNR Graphs TBA: SNR vs AVDD1=AVDD2 L/ROUT1 (DAC path) for 16, 32 SNR vs AVDD1=AVDD2 L/ROUT2 (DAC path) for 16, 32 THD+N Graphs TBA: THD+N vs output power (Analogue in to L/ROUT1) 16, 32 Plots for AVDD1=AVDD2=2.7, 3.0, 3.3, 3.6V THD+N vs output power (Analogue in to L/ROUT2) 16, 32...

  • Page 14: Power Consumption

    WM8758B Production Data POWER CONSUMPTION TYPICAL SCENARIOS Estimated current consumption for typical scenarios are shown below. All measurements are made with quiescent signal. Power delivered to the load is not included. Ω 0.001 0.01 0.036 No clocks None 0.008 0.020 All default 0.008 0.020...

  • Page 15: Audio Paths Overview

    WM8758B Production Data AUDIO PATHS OVERVIEW Figure 1 Audio Paths Overview PD, Rev 4.4, January 2012...

  • Page 16: Signal Timing Requirements

    WM8758B Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T = +25 C, Slave Mode PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY MCLK cycle time...

  • Page 17: Audio Interface Timing - Slave Mode

    WM8758B Production Data Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T =+25 C, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge AUDIO INTERFACE TIMING –...

  • Page 18: Control Interface Timing - 3-Wire Mode

    WM8758B Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND = AGND1 = AGND2 = 0V, T =+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

  • Page 19: Control Interface Timing - 2-Wire Mode

    WM8758B Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD1=AVDD2=3.0V, DGND=AGND1=AGND2=0V, T =+25 C, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

  • Page 20: Internal Power On Reset Circuit

    WM8758B Production Data INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8758B includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and monitors DCVDD.
  • Page 21 WM8758B Production Data Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1 Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum threshold, V , there is enough voltage for the circuit to guarantee PORB is asserted low and the pora...

  • Page 22: Recommended Power Up/Down Sequence

    WM8758B Production Data RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8758B device is powered up and down under control using the following sequences: Power Up: Turn on external power supplies. Wait for supply voltage to settle. Set low bias mode, BIASCUT = 1.
  • Page 23 WM8758B Production Data Figure 10 ADC Power Up and Down Sequence (not to scale) SYMBOL TYPICAL UNIT midrail_on >6 midrail_off 2/fs n/fs adcint ADC Group Delay 29/fs n/fs Table 2 Typical POR Operation (typical values, not tested) Notes: The analogue input pin charge time, t is determined by the VMID pin charge time.
  • Page 24 WM8758B Production Data por_on pora por_off Power Supply DGND No Power Device Ready Internal POR active POR Undefined S Clocks dacint dacint DAC Internal State Power down Init Normal Operation Init Normal Operation Power down line_midrail_on (Note 3) line_midrail_off (Note 1) AVDD/2 Line Out Outputs (Note 2)

  • Page 25: Device Description

    WM8758B Production Data DEVICE DESCRIPTION INTRODUCTION The WM8758B is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. FEATURES The chip offers great flexibility in use, and so can support many different modes of operation as follows: MICROPHONE INPUTS Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be...

  • Page 26: Input Signal Path

    WM8758B Production Data CLOCKING SCHEMES WM8758B offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller.
  • Page 27 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIP2INPPGA Connect LIP pin to left channel input PGA amplifier positive terminal. Input Control 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) LIN2INPPGA Connect LIN pin to left channel input PGA...
  • Page 28 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS INPPGAVOLL 010000 Left channel input PGA volume Left channel 000000 = -12dB input PGA 000001 = -11.25db volume control 010000 = 0dB 111111 = +35.25dB INPPGAMUTEL Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected...
  • Page 29 WM8758B Production Data VOLUME UPDATES Volume settings will not be applied to the PGAs until a ‘1’ is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 13. Figure 13 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 14.
  • Page 30 WM8758B Production Data Figure 15 Volume Update using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8758B will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the INPPGAVU bit is set as shown in Figure 16.
  • Page 31 WM8758B Production Data INPUT BOOST Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the L2/R2 input pin (can be used as a line input, bypassing the input PGA), and OUT4 mixer output.
  • Page 32 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT4_2ADCVOL Controls the OUT4 to ADC input boost stage: OUT4 to ADC 000 = Path disabled (disconnected) 001 = -12dB gain through boost stage 010 = -9dB gain through boost stage … 111 = +6dB gain through boost stage OUT4_2LNR...

  • Page 33: Analogue To Digital Converter (Adc)

    WM8758B Production Data MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit.
  • Page 34 WM8758B Production Data Figure 19 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCENL Enable ADC left channel: Power 0 = ADC disabled management 2 1 = ADC enabled ADCENR Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled...
  • Page 35 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS HPFEN High Pass Filter Enable ADC Control 0 = disabled 1 = enabled HPFAPP Select audio mode or application mode 0 = Audio mode (1 order, fc = ~3.7Hz) 1 = Application mode (2 order, fc = HPFCUT) HPFCUT...
  • Page 36 WM8758B Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.

  • Page 37: Input Limiter / Automatic Level Control (Alc)

    WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCLVOL 11111111 Left ADC Digital Volume Control Left channel [7:0] ( 0dB ) 0000 0000 = Digital Mute ADC Digital 0000 0001 = -127dB Volume 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB ADCVU ADC left and ADC right volume do not...
  • Page 38 WM8758B Production Data In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
  • Page 39 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCSEL ALC function select ALC Control 00 = ALC disabled 01 = Right channel ALC enabled 10 = Left channel ALC enabled 11 = Both channels ALC enabled ALCMAXGAIN Set Maximum Gain of PGA (+35.25dB) [2:0] 111 = +35.25dB...
  • Page 40 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCMODE Determines the ALC mode of operation: ALC Control 0 = ALC mode 1 = Limiter mode. ALCDCY 0011 Decay (gain ramp-up) time [3:0] (13.1ms/6dB) (ALCMODE ==0) 90% of step range 0000 410us 3.3ms 24ms...
  • Page 41 WM8758B Production Data MINIMUM AND MAXIMUM GAIN The ALCMINGAIN and ALCMAXGAIN register sets the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.

  • Page 42: Output Signal Path

    WM8758B Production Data OUTPUT SIGNAL PATH The WM8758B output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL and DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs).
  • Page 43 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACPOL Left DAC output polarity: DAC Control 0 = non-inverted 1 = inverted (180 degrees phase shift) DACRPOL Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) AMUTE Automute enable 0 = Amute disabled...
  • Page 44 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS DACLVOL 11111111 Left DAC Digital Volume Control Left DAC [7:0] ( 0dB ) 0000 0000 = Digital Mute Digital Volume 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB DACVU DAC left and DAC right volume do...
  • Page 45 WM8758B Production Data Figure 23 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 23, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter.
  • Page 46 WM8758B Production Data VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits.
  • Page 47 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMLVL Programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1dB 001 = -2dB 010 = -3dB 011 = -4dB 100 = -5dB 101 to 111 = -6dB Table 23 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equalizer is provided, which can be applied to the ADC or DAC path, together with...
  • Page 48 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS EQ3G 01100 Band 3 Gain Control. See Table 30 for details. EQ Band 3 (0dB) Control EQ3C Band 3 Centre Frequency: 00 = 650Hz 01 = 850Hz 10 = 1.1kHz 11 = 1.4kHz EQ3BW Band 3 Bandwidth Control 0 = narrow bandwidth...

  • Page 49: 3D Stereo Enhancement

    WM8758B Production Data 3D STEREO ENHANCEMENT The WM8758B has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled.
  • Page 50 WM8758B Production Data Figure 24 Left/Right Output Channel Mixers PD, Rev 4.4, January 2012...
  • Page 51 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS BYPL2RMIX Left bypass path (from the Left channel input PGA stage) to right Output mixer output mixer control 0 = not selected 1 = selected BYPR2LMIX Right bypass path (from the right channel input PGA stage) to Left Output mixer output mixer...
  • Page 52 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LMIXEN Left output channel mixer enable: Power 0 = disabled management 1= enabled RMIXEN Right output channel mixer enable: 0 = disabled 1 = enabled Table 32 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs LOUT1 and ROUT1 can drive a 16...
  • Page 53 WM8758B Production Data When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, f . Increasing the capacitance lowers f , improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: = 1 / 2...
  • Page 54 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS HP_COMEN Headphone common ground enable: 1 = Use external common ground 0 = use internal VMID Function inverts if MODE = 2-wire And CSB/GPIO1 = ‘hi’ 0 = Use external common ground 1 = Use internal VMID LOUT1ZC Headphone volume zero cross...
  • Page 55 WM8758B Production Data Figure 27 LOUT2 and ROUT2 Headphone Configuration with Feedback Figure 28 LOUT2 and ROUT2 Line Output Configuration with Feedback The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output and the bypass path (output of the input boost stage). The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits.
  • Page 56 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUT2ZC LOUT2 volume zero cross enable: LOUT2 1 = Change gain on zero cross only Volume 0 = Change gain immediately control LOUT2MUTE Left output mute: 0 = Normal operation 1 = Mute LOUT2VOL 111001 Left output volume:...
  • Page 57 WM8758B Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a differential line output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29. The OUT3 and OUT4 output stages are powered from AVDD1 and AGND1.
  • Page 58 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS OUT3MUTE 0 = Output stage outputs OUT3 mixer OUT3 mixer 1 = Output stage muted – drives out control VMID. Can be used as VMID reference in this mode. (Not to be used for Capless HP pseudo GND) OUT4_2OUT3 OUT4 mixer output to OUT3...
  • Page 59 WM8758B Production Data ENABLING THE OUTPUTS Each analogue output of the WM8758B can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of the WM8758B should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see “Power Management”...
  • Page 60 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS VROI VREF (AVDD1/2) to analogue output resistance 0 = approx 1k 1 = approx 30 k Table 40 Disabled Outputs to VREF Resistance A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This buffer can be enabled using the BUFIOEN register bit.

  • Page 61: Digital Audio Interfaces

    WM8758B Production Data DIGITAL AUDIO INTERFACES The audio interface has four pins:  ADCDAT: ADC data output  DACDAT: DAC data input  LRC: Data Left/Right alignment clock  BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be outputs when the WM8758B operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
  • Page 62 WM8758B Production Data Figure 32 Right Justified Audio Interface (assuming n-bit word length) In I S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
  • Page 63 WM8758B Production Data Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) PD, Rev 4.4, January 2012...
  • Page 64 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MONO Selects between stereo and mono device operation: Audio Interface 0 = Stereo device operation Control 1 = Mono device operation. Data appears in ‘left’ phase of LRC. ADCLRSWAP Controls whether ADC data appears in ‘right’...
  • Page 65 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS Sets the chip to be master over LRC and BCLK Clock Generation 0 = BCLK and LRC clock are inputs Control 1 = BCLK and LRC clock are outputs generated by the WM8758B (MASTER) BCLKDIV Configures the BCLK and LRC output frequency, for use when the chip is...
  • Page 66 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADC_COMP ADC companding Companding 00 = off Control 01 = reserved 10 = µ-law 11 = A-law DAC_COMP DAC companding 00 = off 01 = reserved 10 = µ-law 11 = A-law 0 = off 1 = device operates in 8-bit mode.
  • Page 67 WM8758B Production Data u-law Companding Normalised Input Figure 38 µ-Law Companding A-law Companding Normalised Input Figure 39 A-Law Companding PD, Rev 4.4, January 2012...

  • Page 68: Audio Sample Rates

    WM8758B Production Data AUDIO SAMPLE RATES The WM8758B filter characteristics for the ADCs and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
  • Page 69 WM8758B Production Data Figure 40 PLL and Clock Select Circuit The PLL frequency ratio R = f (see Figure 40) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (2 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz.

  • Page 70: General Purpose Input/Output

    WM8758B Production Data The PLL performs best when f is around 90MHz. Its stability peaks at N=8. Some example settings are shown below. K REGISTERS MCLK DESIRED OUTPUT (MHz) (MHz) REGISTER (SYSCLK) (f1) R36[3:0] (MHz) 11.2889025 90.31122 7.525935 7h 86A3ACh 0111 (XX7h) 000100001 (021h) 101010001 (151h) 110101100 (1ACh) 12.288 98.304 8.192...
  • Page 71 WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS GPIO1SEL CSB/GPIO1 pin function select: GPIO 000 = input (CSB / Jack detection: depending on MODE setting) Control 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1...

  • Page 72: Output Switching (Jack Detect)

    WM8758B Production Data OUTPUT SWITCHING (JACK DETECT) When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and R2/GPIO3 pins can also be used for this purpose.

  • Page 73: Control Interface

    WM8758B Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS JD_SEL Pin selected as jack detection input GPIO control 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved JD_EN Jack Detection Enable 0 = disabled 1 = enabled JD_VMID [7] VMID_EN_0 [8] VMID_EN_1 JD_EN0...

  • Page 74: Resetting The Chip

    WM8758B Production Data Figure 41 3-Wire Serial Control Interface 2-WIRE SERIAL CONTROL MODE The WM8758B supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8758B).

  • Page 75: Power Supplies

    WM8758B Production Data POWER SUPPLIES The WM8758B requires four separate power supplies:  AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1, ROUT1, OUT3 and OUT4. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones).
  • Page 76 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS HALFO HALFOPBIAS (Do not use) PBIAS Bias Control 0 = disabled 1 = enabled (Reduces AVDD current by 0.5mA) Table 58 HALFOPBIAS Control Wolfson’s recommendation is: Do not use HALFOPBIAS PD, Rev 4.4, January 2012...

  • Page 77: Pop Minimisation

    WM8758B Production Data POP MINIMISATION POBCTRL WM8758B has two bias generators. A noisy bias derived from AVDD and a low noise bias derived from VMID. POBCTRL is use to switch between the two bias generators. During power up, the AVDD derived bias is available as soon as AVDD is applied; the VMID derived bias is available once the VMID node has charged up.

  • Page 78: Register Map

    WM8758B Production Data REGISTER MAP REGISTER DEF’T ADDR NAME B[15:9] DEC HEX (HEX) Software Reset Software reset Power manage’t 1 OUT4MIX OUT3MIX PLLEN MICBEN BIASEN BUFIOEN VMIDSEL Power manage’t 2 ROUT1EN LOUT1EN SLEEP BOOST BOOST INPGA INPPGA ADCENR ADCENL Power manage’t 3 OUT4EN OUT3EN LOUT2EN ROUT2EN...
  • Page 79 WM8758B Production Data REGISTER DEF’T ADDR NAME B[15:9] DEC HEX (HEX) Input ctrl MICBVSEL R2_2 RIN2 RIP2 L2_2 LIN2 LIP2 INPPGA INPPGA INPPGA INPPGA INPPGA INPPGA Left INP PGA gain INPGAVU INPPGA INPPGA INPPGAVOLL ctrl MUTEL Right INP PGA gain INPGAVU INPPGA INPPGA...

  • Page 80: Digital Filter Characteristics

    WM8758B Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner -3dB Frequency -0.5dB...

  • Page 81: Dac Filter Responses

    WM8758B Production Data DAC FILTER RESPONSES 3.05 2.95 2.85 2.75 -100 -120 2.65 -140 -160 0.05 0.15 0.25 0.35 0.45 Frequency (fs) Frequency (fs) Figure 43 DAC Digital Filter Frequency Response Figure 44 DAC Digital Filter Ripple (128xOSR) (128xOSR) 3.05 2.95 2.85 2.75...

  • Page 82: Highpass Filter

    WM8758B Production Data HIGHPASS FILTER The WM8758B has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz.

  • Page 83: 5-Band Equaliser

    WM8758B Production Data 5-BAND EQUALISER The WM8758B has a 5-band equalizer which can be applied to either the ADC path or the DAC path. The plots from Figure 53 to Figure 66 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
  • Page 84 WM8758B Production Data Frequency (Hz) Frequency (Hz) Figure 58 EQ Band 3 – Peak Filter Centre Frequencies, EQ3B Figure 59 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 Frequency (Hz) Figure 60 EQ Band 3 – EQ3BW=0, EQ3BW=1 PD, Rev 4.4, January 2012...
  • Page 85 WM8758B Production Data Frequency (Hz) Frequency (Hz) Figure 61 EQ Band 4 – Peak Filter Centre Frequencies, EQ3B Figure 62 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 Frequency (Hz) Figure 63 EQ Band 4 – EQ3BW=0, EQ3BW=1 Frequency (Hz) Frequency (Hz) Figure 64 EQ Band 5 High Frequency Shelf Filter Cut-offs...
  • Page 86 WM8758B Production Data Figure 66 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EqxBW=0 for the peak filters.

  • Page 87: Applications Information

    WM8758B Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 67 External Component Diagram PD, Rev 4.4, January 2012...

  • Page 88: Package Diagram

    WM8758B Production Data PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE 5 0.9 mm BODY, 0.50 mm LEAD PITCH DM101.A DETAIL 1 INDEX AREA EXPOSED (D/2 X E/2) GROUND PADDLE TOP VIEW BOTTOM VIEW 0.08 SIDE VIEW SEATING PLANE 45° DETAIL 2 0.30 EXPOSED...

  • Page 89: Important Notice

    Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
  • Page 90 WM8758B Production Data REVISION HISTORY DATE ORIGINATOR CHANGES 12/12/11 JMacD Order codes changed from WM8758BGEFL/V and WM8758BGEFL/RV to WM8758CBGEFL/V and WM8758CBGEFL/RV to reflect change to copper wire bonding. 12/12/11 JMacD Package diagram changed to DM101.A. PD, Rev 4.4, January 2012...
  • Page 91 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic WM8758CBGEFL/V WM8758CBGEFL/RV...

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