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Mono CODEC with Speaker Driver and Video Buffer
DESCRIPTION
The WM8941 is a low power, high quality mono CODEC
designed for portable applications such as digital still cameras
or camcorders.
The device integrates support for a differential or single ended
mic, and includes drivers for speakers or headphone, and
mono line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required. A high performance, low power current-mode
video buffer provides inherent short circuit protection.
An
integrated
video
programmable gain from 0-6dB (6-12dB unloaded), sync-tip
rd
clamp and a 3
order input low pass filter for signal re-
construction.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48ks/s. A selectable high pass filter and
four fully-programmable notch filters are available in the ADC
path. An advanced mixed signal ALC function with noise gate
is provided, while readback of PGA gain during ALC operation
is supported. The digital audio interface supports A-law and μ-
law companding.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8941 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control using the selectable two
or three wire control interface.
WM8941 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area, with
high thermal performance.
WOLFSON MICROELECTRONICS plc
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FEATURES
•
Mono CODEC:
•
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
•
DAC SNR 98dB, THD -80dB ('A'-weighted @ 8 – 48ks/s)
•
ADC SNR 91dB, THD -83dB ('A'-weighted @ 8 – 48ks/s)
•
On-chip Headphone/Speaker Driver
-
40mW output power into 16Ω
-
BTL speaker drive 0.4W into 8Ω
•
Additional MONO Line output
•
Multiple analog or 'Aux' inputs, plus analog bypass path
•
Mic Preamps :
has
•
Differential or single end Microphone Interface
-
Programmable preamp gain
-
Pseudo differential inputs with common mode rejection
-
Programmable ALC / Noise Gate in ADC path
•
Low-noise bias supplied for electret microphones
OTHER FEATURES
•
Integrated video buffer with LPF and clamp.
•
Digital Playback Limiter
•
Programmable high pass filter (wind noise reduction)
•
4 notch filters (narrowband noise suppression)
•
On-chip PLL
•
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
•
4x4x0.75mm 28 lead QFN package
APPLICATIONS
•
Digital still cameras and camcorders
•
General purpose mono audio CODEC with video buffer
WM8941
Production Data, Rev 4.0, August 2008
Copyright ©2008 Wolfson Microelectronics plc
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Table of Contents
Related Manuals for Wolfson WM8941
Summary of Contents for Wolfson WM8941
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Page 1: Table Of Contents Description
Mono CODEC with Speaker Driver and Video Buffer DESCRIPTION FEATURES • Mono CODEC: The WM8941 is a low power, high quality mono CODEC • Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz designed for portable applications such as digital still cameras •... -
Page 2: Block Diagram
WM8941 Production Data BLOCK DIAGRAM PD, Rev 4.0, August 2008... -
Page 3: Table Of Contents
WM8941 Production Data TABLE OF CONTENTS DESCRIPTION........................ 1 FEATURES ........................1 APPLICATIONS......................1 BLOCK DIAGRAM ......................2 PIN CONFIGURATION ....................5 ORDERING INFORMATION................... 5 PIN DESCRIPTION......................6 ABSOLUTE MAXIMUM RATINGS ................. 7 RECOMMENDED OPERATING CONDITIONS.............. 7 ELECTRICAL CHARACTERISTICS ................8 TERMINOLOGY ........................ - Page 4 WM8941 Production Data RECOMMENDED EXTERNAL COMPONENTS ..............92 PACKAGE DIAGRAM ....................93 IMPORTANT NOTICE ....................94 ADDRESS ..........................94 PD, Rev 4.0, August 2008...
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Page 5: Pin Configuration
WM8941 Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE SENSITIVITY PACKAGE BODY RANGE LEVEL TEMPERATURE WM8941GEFL/V -25°C to +85°C 28-lead QFN (4x4x0.75mm) MSL3 (Pb-free) WM8941GEFL/RV -25°C to +85°C 28-lead QFN (4x4x0.75mm) MSL3 (Pb-free, tape and reel) Note: Reel Quantity = 3,500 PD, Rev 4.0, August 2008... -
Page 6: Pin Description
WM8941 Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION Analogue Output Microphone bias MICBIAS Supply Analogue supply AVDD Supply Analogue ground AGND DCVDD Supply Digital Supply (Core) DBVDD Supply Digital supply (Input/Output) DGND Supply Digital ground Digital Output ADC digital audio data output... -
Page 7: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. -
Page 8: Electrical Characteristics
WM8941 Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD=3.3V, SPKVDD =3.3V, , VBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level –... - Page 9 WM8941 Production Data Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD=3.3V, SPKVDD =3.3V, , VBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Digital to Analogue Converter (DAC) to MONO Output with 10kΩ / 50pF load and DACVOL 0dB...
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Page 10: Terminology
WM8941 Production Data Test Conditions DCVDD=1.8V, DBVDD=3.3V, AVDD=3.3V, SPKVDD =3.3V, , VBVDD=3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Low pass filter order order Low Pass Filter Response (referenced to 100kHz) Response at 2.4MHz... -
Page 11: Audio Paths Overview
WM8941 Production Data AUDIO PATHS OVERVIEW Power Consumption PD, Rev 4.0, August 2008... - Page 12 WM8941 Production Data Typical current consumption for various scenarios is shown below. AVDD SPKVDD VBVDD DVDD TOTAL MODE (3V3) (3V3) (3V3) (1.8V) POWER (MW) Power OFF (No Clocks) 0.038 0.125 Sleep (VMID maintained, No Clocks) 0.190 0.627 Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE 14.2...
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Page 13: Signal Timing Requirements
WM8941 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 1 System Clock Timing Requirements Test Conditions DVDD=1.8V, AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY MCLK cycle time... -
Page 14: Audio Interface Timing - Slave Mode
WM8941 Production Data Test Conditions DVDD=1.8V, AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T =+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL UNIT Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge... -
Page 15: Control Interface Timing - 3-Wire Mode
WM8941 Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DVDD = 1.8V, AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. -
Page 16: Control Interface Timing - 2-Wire Mode
WM8941 Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DVDD=1.8V, AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. -
Page 17: Device Description
DEVICE DESCRIPTION INTRODUCTION The WM8941 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or camcorders with mono audio, record and playback capability. An integrated video buffer provides a seamless transition from video DAC output to TV input, saving space and external components. -
Page 18: Input Signal Path
CONTROL INTERFACES To allow full software control over all its features, the WM8941 supports 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. - Page 19 WM8941 Production Data Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUX2INPPGA Select AUX amplifier output as input PGA signal source. Input Control 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal.
- Page 20 WM8941 Production Data The input PGA is enabled by the IPPGAEN register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS INPPGAEN Input microphone PGA enable Power 0 = disabled Management 2 1 = enabled Table 3 Input PGA Enable Control INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps.
- Page 21 WM8941 Production Data AUXILLIARY INPUT An auxiliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors.
- Page 22 WM8941 Production Data INPUT BOOST The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure...
- Page 23 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MICP2BOOSTVOL Controls the MICP pin to the input boost stage (NB, when using this path set Input BOOST MICP2INPPGA=0): control 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage …...
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Page 24: Analogue To Digital Converter (Adc)
Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8941 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. - Page 25 WM8941 Production Data The ADC is enabled by the ADCEN register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCEN 0 = ADC disabled Power 1 = ADC enabled management 2 Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit.
- Page 26 WM8941 Production Data HPFCUT FS (KHZ) SR=101/100 SR=011/010 SR=001/000 11.025 22.05 44.1 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 14.
- Page 27 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS NF1_UP Notch filter 1 update. The notch filter 1 values used internally only update when Notch Filter 1A one of the NFU bits is set high. NF1_EN Notch Filter 1 enable. 0=Disabled...
- Page 28 WM8941 Production Data The notch filter coefficients are calculated as follows: − tan( tan( − cos( Where: π π = centre frequency in Hz, f = -3dB bandwidth in Hz, f = sample frequency in Hz The actual register values can be determined from the coefficients as follows:...
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Page 29: Input Limiter / Automatic Level Control (Alc)
Production Data INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8941 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. - Page 30 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCHLD 0000 ALC hold time before gain is increased. [3:0] (0ms) 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s...
- Page 31 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS R42 (2Ah) ALCZC 0 (zero cross ALC uses zero cross detection circuit. off) ALC Control 4 0 = Disabled (recommended) 1 = Enabled Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
- Page 32 WM8941 Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode.
- Page 33 WM8941 Production Data NORMAL MODE ALCMODE = 0 (Normal Mode) Attack Time (s) ALCATK ATK6dB ATK90% 0000 104µs 832µs 0001 208µs 1.66ms 12ms 0010 416µs 3.33ms 24ms 0011 832µs 6.66ms 48ms 0100 1.66ms 13.3ms 96ms 0101 3.33ms 26.6ms 192ms 0110 6.66ms...
- Page 34 WM8941 Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) Attack Time (s) ALCATK ATKLIM ATKLIM6dB ATKLIM90% 0000 22.7µs 182µs 1.31ms 0001 45.4µS 363µs 2.62ms 0010 90.8µS 726µs 5.23ms 0011 182µS 1.45ms 10.5ms 0100 363µS 2.91ms 20.9ms 0101 726µS 5.81ms 41.8ms...
- Page 35 WM8941 Production Data MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
- Page 36 WM8941 Production Data ALCMIN Minimum Gain (dB) Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range.
- Page 37 WM8941 Production Data Figure 15 ALCLVL PD, Rev 4.0, August 2008...
- Page 38 WM8941 Production Data Figure 16 ALC Hold Time ALCHLD HOLD 0000 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 27 ALC Hold Time Values PD, Rev 4.0, August 2008...
- Page 39 WM8941 Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale.
- Page 40 WM8941 Production Data The diagrams below show the response of the system to the same signal with and without noise gate. Figure 17 ALC Operation Above Noise Gate Threshold PD, Rev 4.0, August 2008...
- Page 41 WM8941 Production Data Figure 18 Noise Gate Operation PD, Rev 4.0, August 2008...
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Page 42: Output Signal Path
Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8941, irrespective of whether the DACs are running or not. The WM8941 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: •... - Page 43 1 = DAC enabled Table 30 DAC Enable The WM8941 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will step back up to the digital gain setting. This function is disabled by default.
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Page 44: Volume Boost
Production Data DAC OUTPUT LIMITER The WM8941 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic. - Page 45 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMEN Enable the DAC digital limiter: DAC digital 0=disabled limiter control 1 1=enabled LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms...
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Page 46: Analogue Outputs
Table 33 DAC Digital Limiter Control ANALOGUE OUTPUTS The WM8941 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1V rms signals. - Page 47 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPKZC Speaker Volume control zero cross enable: Speaker volume control 1 = Change gain on zero cross only 0 = Change gain immediately SPKMUTE Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP)
- Page 48 Table 37 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8941 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8941 should remain disabled.
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Page 49: Output Switch
WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS VROI VREF (AVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩ Table 39 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. - Page 50 Table 41 Output Switch Operation (GPIOSEL=001) THERMAL SHUTDOWN The speaker outputs can drive very large currents. To protect the WM8941 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125 C.
- Page 51 WM8941 Production Data HEADPHONE OUTPUT The speaker outputs can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output: Figure 23 Recommended Headphone Output Configurations...
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Page 52: Video Buffer
Production Data VIDEO BUFFER DESCRIPTION The WM8941 incorporates a current mode output video buffer capable of operating from a 2.5V supply, with an input 3 order Low Pass Filter (LPF) and clamp. The gain through this buffer can be programmed as 0dB or 6dB (=6dB or 12dB unloaded) via the control interface. The current mode output means that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. - Page 53 -20dBV sinewave input, 0dB gain setting, VBVDD=3.3V 0dB Qboost 6dB Qboost 1000 10000 100000 Frequency (kHz) Figure 26 WM8941 Video Buffer Filter Response VIDEO BUFFER REGISTERS Video buffer enable / disable and gain are controlled via the following registers: REGISTER LABEL DEFAULT DESCRIPTION...
- Page 54 WM8941 Production Data TEST WAVEFORMS Figure 27 Black Needle Pulse (Full frame of white with Figure 28 Dual Needle Pulse (50% grey field with a vertical black line) closely-spaced white and black vertical lines spaced across the line scan) Figure 29 Multiburst (A horizontal multiburst of signals Figure 30 White Needle Pulse (A full frame of black with with frequencies ranging from 0.5MHz to 5.75MHz)
- Page 55 WM8941 Production Data RECOMMENDED VIDEO BUFFER INITIALISATION SEQUENCE Power Up (Video signal AC coupled to Video Buffer input): Turn on external power supplies. Wait for supply voltages to settle. Reset internal registers to default state (software reset). Set VMIDSEL[1:0] bits for 50kΩ reference string impedance. *Note 1.
- Page 56 WM8941 ensures that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a TV), providing excellent signal reproduction.
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Page 57: Digital Audio Interfaces
• BCLK: Bit clock, for synchronisation The clock signals BCLK, and FRAME can be outputs when the WM8941 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: •... - Page 58 WM8941 Production Data Figure 33 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
- Page 59 WM8941 Production Data Figure 36 DSP/PCM Mode Audio Interface (Mode A, FRAMEP=0) Figure 37 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1) AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below.
- Page 60 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LOUTR LOUTR control Audio interface 0=normal control 1=Input mono channel data output on both left and right channels BCLK polarity 0=normal 1=inverted FRAMEP Frame clock polarity (for RJ, LJ and I formats)
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Page 61: Audio Sample Rates
ADC audio interface. AUDIO SAMPLE RATES The WM8941 sample rates for the ADC and the DAC are set using the SR register bits. The cut-offs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. -
Page 62: Master Clock And Phase Locked Loop (Pll)
Table 46 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8941 has an on-chip phase-locked loop (PLL) circuit that can be used to: • Generate master clocks for the WM8940 audio functions from another external clock, e.g. - Page 63 WM8941 Production Data Figure 38 PLL and Clock Select Circuit The PLL frequency ratio R = f (see Table 48) can be set using the register bits PLLK and PLLN: N = int R K = int (2 (R - N)) N controls the ratio of the division, and K the fractional part.
- Page 64 WM8941 Production Data If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation. INPUT CLOCK DESIRED PLL DIVISION FRACTIONAL INTEGER OUTPUT (F REQUIRED (R) DIVISION (K) DIVISION (N) 11.2896MHz 90.3168MHz 12.2880MHz...
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Page 65: Companding
Production Data COMPANDING The WM8941 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available. - Page 66 WM8941 Production Data Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds.
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Page 67: General Purpose Input/Output
GENERAL PURPOSE INPUT/OUTPUT In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In the WM8941, a separate GPIO pin is available and this can be used for GPIO in 3-wire mode. Also in 3 wire mode, the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit Whichever pin is used for GPIO, it is controlled from the GPIO control register R8. - Page 68 WM8941 Production Data Figure 41 Example Usage of MODE Pin to Generate a Clock Out in 3-wire Mode This example shows how the MODE_GPIO register bit interfaces to the MODE pad in the case there MODE is used as a GPIO output. When MODE_GPIO is set, the internal version of MODE is overridden to high and the MODE pin output driver is enabled.
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Page 69: 3-Wire Serial Control Mode
WM8941 Production Data 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits. -
Page 70: 2-Wire Serial Control Mode
During a write, once the WM8941 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8941 register address plus the first bit of register data). The WM8941 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. - Page 71 WM8941 Production Data RECOMMENDED POWER UP/DOWN SEQENCE In order to minimise output pop and click noise, it is recommended that the WM8941 device is powered up and down using one of the following sequences: Power Up: Turn on external power supplies. Wait for supply voltages to settle.
- Page 72 WM8941 Production Data Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID in a way that is controlled and predictable.
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Page 73: Power Management
WM8941 Production Data POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. -
Page 74: Pop Minimisation
Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8941. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to be enabled before VMID at start-up. This feature can be used to minimise pops. -
Page 75: Register Map
WM8941 Production Data REGISTER MAP PD, Rev 4.0, August 2008... -
Page 76: Register Bits By Address
WM8941 Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER LABEL DEFAULT... - Page 77 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 3 (03h) 15:8 Reserved MONOEN MONOOUT enable Analogue Outputs 0 = disabled 1 = enabled SPKNEN SPKOUTN enable Analogue Outputs 0 = disabled 1 = enabled SPKPEN SPKOUTP enable Analogue Outputs...
- Page 78 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS ALRSWAP Controls whether ADC data appears in ‘right’ or ‘left’ Digital Audio phases of FRAME clock: Interfaces 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME...
- Page 79 ADDRESS Sets the chip to be master over FRAME and BCLK Digital Audio Interfaces 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8941 (MASTER) 7 (07h) 15:7 00000 Reserved POB_CTRL Power on Bias Control...
- Page 80 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 9 (09h) 15:2 Reserved AUTOINC Auto-Incremental write enable Control Interface 0=Auto-Incremental writes disabled 1=Auto-Incremental writes enabled Reserved 10 (0Ah) 15:7 Reserved DACMU DAC soft mute enable Output Signal Path 0 = DACMU disabled...
- Page 81 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13:0 NF0_A0 0000h Notch Filter 0 a0 coefficient Analogue to Digital Converter (ADC) 17 (11h) NF0_UP Notch filter 0 update. The notch filter 0 values used Analogue to internally only update when one of the NF0_UP bits is Digital Converter set high.
- Page 82 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13:0 NF3_A1 0000h Notch Filter 3 a1 coefficient Analogue to Digital Converter (ADC) 24 (18h) 15:9 Reserved LIMEN Enable the DAC digital limiter: Output Signal Path 0=disabled 1=enabled 24 (18h)
- Page 83 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 26 (1Ah) 15:0 0000h Reserved 27 (1Bh) 15:0 0000h Reserved 28 (1Ch) 15:0 0000h Reserved 29 (1Dh) 15:0 0000h Reserved 30 (1Eh) 15:0 0000h Reserved 31(1Fh) 15:0 0000h Reserved 32 (20h)
- Page 84 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS PLLN[3:0] 1100 Integer (N) part of PLL input/output frequency ratio. Master Clock and Use values greater than 5 and less than 13. Phase Locked Loop (PLL) 37 (25h) 15:6 000h...
- Page 85 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS MICP2INPPGA Connect input PGA amplifier positive terminal to MICP Input Signal Path or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to...
- Page 86 WM8941 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS AUX2SPK Output of auxiliary amplifier to speaker mixer input Analogue Outputs 0 = not selected 1 = selected Reserved BYP2SPK Bypass path (output of input boost stage) to speaker Analogue Outputs...
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Page 87: Digital Filter Characteristics
WM8941 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner... -
Page 88: Dac Filter Responses
WM8941 Production Data DAC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -120 -0.2 Frequency (Fs) Frequency (Fs) Figure 47 DAC Digital Filter Ripple Figure 46 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -0.2... -
Page 89: Highpass Filter
Production Data HIGHPASS FILTER The WM8941 has a selectable digital high pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2 order high pass filter with a selectable cut-off frequency. -
Page 90: Notch Filters And Low Pass Filter
NOTCH FILTERS AND LOW PASS FILTER The WM8941 supports four programmable notch filters. The fourth notch filter can be configured as a low pass filter. The following illustrates three digital notch filters, followed by a single low pass filter in the ADC filter path. - Page 91 WM8941 Production Data T T T (dB) Frequency (Hz) Figure 56 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; NF2 fc = 10kHz; LPF fc = 11kHz; fb = 100Hz, 600Hz, 2kHz...
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Page 92: Applications Information
WM8941 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 57 Recommended External Components PD, Rev 4.0, August 2008... -
Page 93: Package Diagram
WM8941 Production Data PACKAGE DIAGRAM FL: 28 PIN QFN PLASTIC PACKAGE 4 0.75 mm BODY, 0.45 mm LEAD PITCH DM042.B DETAIL 1 EXPOSED INDEX AREA GROUND (D/2 X E/2) PADDLE SEE DETAIL 2 0.226 Ref. TOP VIEW BOTTOM VIEW DETAIL 1 DETAIL 2 0.08... -
Page 94: Important Notice
Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
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