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DESCRIPTION
The WM8940 is a low power, high quality mono CODEC
designed for portable applications such as digital still cameras
or camcorders.
The device integrates support for a differential or single ended
mic, and includes drivers for speakers or headphone, and
mono line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48ks/s. A selectable high pass filter
and four fully-programmable notch filters are available in the
ADC path. An advanced mixed signal ALC function with noise
gate is provided, while readback of PGA gain during ALC
operation is supported. The digital audio interface supports A-
law and µ-law companding.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8940 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control using the selectable two
or three wire control interface.
WM8940 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area,
with high thermal performance.
WOLFSON MICROELECTRONICS plc
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FEATURES
•
Mono CODEC:
•
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
•
DAC SNR 98dB, THD -84dB ('A'-weighted @ 8 – 48ks/s)
•
ADC SNR 94dB, THD -80dB ('A'-weighted @ 8 – 48ks/s)
•
On-chip Headphone/Speaker Driver
-
40mW output power into 16Ω
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BTL speaker drive 0.4W into 8Ω
•
Additional MONO Line output
•
Multiple analog or 'Aux' inputs, plus analog bypass path
•
Mic Preamps:
•
Differential or single end Microphone Interface
-
Programmable preamp gain
-
Pseudo differential inputs with common mode rejection
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Programmable ALC / Noise Gate in ADC path
•
Low-noise bias supplied for electret microphones
OTHER FEATURES
•
Digital Playback Limiter
•
Programmable high pass filter (wind noise reduction)
•
4 notch filters (narrowband noise suppression)
•
On-chip PLL
•
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
•
4x4x0.9mm 24 lead QFN package
APPLICATIONS
•
Digital still cameras and camcorders
•
General purpose mono audio CODEC
Copyright ©2008 Wolfson Microelectronics plc
WM8940
Production Data, Rev 4.2, April 2008
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Table of Contents
Related Manuals for Wolfson WM8940
Summary of Contents for Wolfson WM8940
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Page 1: Description
Mono CODEC with Speaker Driver DESCRIPTION FEATURES • The WM8940 is a low power, high quality mono CODEC Mono CODEC: • Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz designed for portable applications such as digital still cameras •... -
Page 2: Block Diagram
WM8940 Production Data BLOCK DIAGRAM PD, Rev 4.2, April 2008... -
Page 3: Table Of Contents
WM8940 Production Data TABLE OF CONTENTS DESCRIPTION .......................1 FEATURES......................1 APPLICATIONS .....................1 BLOCK DIAGRAM ....................2 TABLE OF CONTENTS ..................3 PIN CONFIGURATION...................5 ORDERING INFORMATION ..................5 PIN DESCRIPTION ....................6 ABSOLUTE MAXIMUM RATINGS.................7 RECOMMENDED OPERATING CONDITIONS .............7 ELECTRICAL CHARACTERISTICS ..............8 TERMINOLOGY ......................10 AUDIO PATHS OVERVIEW .................11 SIGNAL TIMING REQUIREMENTS ..............13... - Page 4 WM8940 Production Data NOTCH FILTER WORKED EXAMPLE................ 84 APPLICATIONS INFORMATION .................85 RECOMMENDED EXTERNAL COMPONENTS ............85 PACKAGE DIAGRAM ..................86 IMPORTANT NOTICE ..................87 ADDRESS ........................87 PD, Rev 4.2, April 2008...
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Page 5: Pin Configuration
WM8940 Production Data PIN CONFIGURATION TOP VIEW ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE SENSITIVITY PACKAGE BODY RANGE LEVEL TEMPERATURE WM8940GEFL/V -25°C to +85°C 24-lead QFN (4x4x0.9mm) MSL3 (Pb-free) WM8940GEFL/RV -25°C to +85°C 24-lead QFN (4x4x0.9mm) MSL3 (Pb-free, tape and reel) -
Page 6: Pin Description
WM8940 Production Data PIN DESCRIPTION NAME TYPE DESCRIPTION MICBIAS Analogue Output Microphone bias AVDD Supply Analogue supply AGND Supply Analogue ground DCVDD Supply Digital Supply (Core) DBVDD Supply Digital supply (Input/Output) Supply Digital ground DGND ADCDAT Digital Output ADC digital audio data output... -
Page 7: Absolute Maximum Ratings
Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. -
Page 8: Electrical Characteristics
WM8940 Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level –... - Page 9 WM8940 Production Data Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Digital to Analogue Converter (DAC) to MONO Output with 10kΩ / 50pF load and DACVOL 0dB...
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Page 10: Terminology
WM8940 Production Data TERMINOLOGY Full-scale input and output levels scale in relation to AVDD or SPKVDD depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1V (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD. -
Page 11: Audio Paths Overview
WM8940 Production Data AUDIO PATHS OVERVIEW PD, Rev 4.2, April 2008... - Page 12 WM8940 Production Data POWER CONSUMPTION Typical current consumption for various scenarios is shown below. DCVDD DBVDD TOTAL MODE AVDD SPKVDD (1.8V) (1.8V) POWER (3V3) (3V3) (MW) Power OFF (No Clocks) 0.038 0.126 Sleep (VMID maintained, No Clocks) 0.190 0.627 Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE 14.3...
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Page 13: Signal Timing Requirements
WM8940 Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY MCLK cycle time... -
Page 14: Audio Interface Timing - Slave Mode
WM8940 Production Data Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T =+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL UNIT Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge... -
Page 15: Control Interface Timing - 3-Wire Mode
WM8940 Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. -
Page 16: Control Interface Timing - 2-Wire Mode
WM8940 Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. -
Page 17: Device Description
DEVICE DESCRIPTION INTRODUCTION The WM8940 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or camcorders with mono audio, record and playback capability. -
Page 18: Input Signal Path
Production Data CONTROL INTERFACES To allow full software control over all its features, the WM8940 supports 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. - Page 19 WM8940 Production Data Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUX2INPPGA Select AUX amplifier output as input PGA signal source. Input Control 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal.
- Page 20 WM8940 Production Data INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0].
- Page 21 WM8940 Production Data The AUXMODE register bit controls the auxiliary input mode of operation: In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the aux circuit using only the internal components.
- Page 22 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS INPPGAMUTE Mute control for input PGA: Input PGA gain 0=Input PGA not muted, normal operation control 1=Input PGA muted (and disconnected from the following input BOOST stage). PGABOOST 0 = PGA output has +0dB gain through input BOOST stage.
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Page 23: Analogue To Digital Converter (Adc)
Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8940 uses a multi-bit, over sampled sigma-delta ADC channel. The use of multi-bit feedback and high over sampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. - Page 24 WM8940 Production Data Figure 10 ADC Digital Filter Path The ADC is enabled by the ADCEN register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCEN 0 = ADC disabled Power 1 = ADC enabled management 2 Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit.
- Page 25 WM8940 Production Data HPFCUT FS (KHZ) SR=101/100 SR=011/010 SR=001/000 11.025 22.05 44.1 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 14.
- Page 26 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS NF1_UP Notch filter 1 update. The notch filter 1 Notch Filter 1A values used internally only update when one of the NFU bits is set high. NF1_EN Notch Filter 1 enable. 0=Disabled...
- Page 27 WM8940 Production Data − tan( tan( − cos( Where: π π = centre frequency in Hz, f = -3dB bandwidth in Hz, f = sample frequency in Hz The actual register values can be determined from the coefficients as follows:...
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Page 28: Input Limiter / Automatic Level Control (Alc)
Production Data INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8940 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. - Page 29 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ALCHLD 0000 ALC hold time before gain is increased. [3:0] (0ms) 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s...
- Page 30 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS 1010 or 23.2ms 186ms 1.34s higher R42 (2Ah) ALCZC 0 (zero cross ALC uses zero cross detection circuit. off) ALC Control 4 0 = Disabled (recommended) 1 = Enabled Table 20 ALC Control Registers NOTE: The Input PGA Volume register R45 must be written with the INPPGAMUTE bit R45[6] set to 0 before setting ALCSEL bit R32[8] to 1.
- Page 31 WM8940 Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode.
- Page 32 WM8940 Production Data NORMAL MODE ALCMODE = 0 (Normal Mode) Attack Time (s) ALCATK ATK6dB ATK90% 0000 104µs 832µs 0001 208µs 1.66ms 12ms 0010 416µs 3.33ms 24ms 0011 832µs 6.66ms 48ms 0100 1.66ms 13.3ms 96ms 0101 3.33ms 26.6ms 192ms 0110 6.66ms...
- Page 33 WM8940 Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) Attack Time (s) ALCATK ATKLIM ATKLIM6dB ATKLIM90% 0000 22.7µs 182µs 1.31ms 0001 45.4µS 363µs 2.62ms 0010 90.8µS 726µs 5.23ms 0011 182µS 1.45ms 10.5ms 0100 363µS 2.91ms 20.9ms 0101 726µS 5.81ms 41.8ms...
- Page 34 WM8940 Production Data MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
- Page 35 WM8940 Production Data ALCMIN Minimum Gain (dB) Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range.
- Page 36 WM8940 Production Data Figure 15 ALCLVL PD, Rev 4.2, April 2008...
- Page 37 WM8940 Production Data Figure 16 ALC Hold Time ALCHLD HOLD 0000 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 27 ALC Hold Time Values PD, Rev 4.2, April 2008...
- Page 38 When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8940 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH.
- Page 39 WM8940 Production Data The diagrams below show the response of the system to the same signal with and without noise gate. Figure 17 ALC Operation Above Noise Gate Threshold PD, Rev 4.2, April 2008...
- Page 40 WM8940 Production Data Figure 18 Noise Gate Operation PD, Rev 4.2, April 2008...
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Page 41: Output Signal Path
Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8940, irrespective of whether the DACs are running or not. The WM8940 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control A digital peak limiter. - Page 42 1 = DAC enabled Table 30 DAC Enable The WM8940 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will step back up to the digital gain setting. This function is disabled by default.
- Page 43 Production Data DAC OUTPUT LIMITER The WM8940 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
- Page 44 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMEN Enable the DAC digital limiter: DAC digital 0=disabled limiter control 1 1=enabled LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms...
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Page 45: Analogue Outputs
Table 33 DAC Digital Limiter Control ANALOGUE OUTPUTS The WM8940 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1V rms signals. - Page 46 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS SPKZC Speaker Volume control zero cross enable: Speaker volume control 1 = Change gain on zero cross only 0 = Change gain immediately SPKMUTE Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP)
- Page 47 Table 37 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8940 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8940 should remain disabled.
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Page 48: Output Switch
WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS VROI VREF (AVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩ Table 39 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. - Page 49 Table 41 Output Switch Operation (GPIOSEL=001) THERMAL SHUTDOWN The speaker outputs can drive very large currents. To protect the WM8940 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125 C.
- Page 50 WM8940 Production Data HEADPHONE OUTPUT The speaker outputs can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output: Figure 23 Recommended Headphone Output Configurations...
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Page 51: Digital Audio Interfaces
• BCLK: Bit clock, for synchronisation The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: •... - Page 52 WM8940 Production Data Figure 26 Right Justified Audio Interface (assuming n-bit word length) In I S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
- Page 53 WM8940 Production Data 1/fs 1 BCLK 1 BCLK falling edge can occur anywhere in this area BCLK LEFT CHANNEL RIGHT CHANNEL DACDAT / n-2 n-1 n-2 n-1 ADCDAT Input Word Length (WL) Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1)
- Page 54 101=divide by 32 110=reserved 111=reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) Table 44 Clock Control PD, Rev 4.2, April 2008...
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Page 55: Audio Sample Rates
ADC audio interface. AUDIO SAMPLE RATES The WM8940 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. - Page 56 N controls the ratio of the division, and K the fractional part. The PLL output then passes through a fixed divide by 4, and can also be further divided by MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940 DSP.
- Page 57 WM8940 Production Data INTEGER N DIVISION The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12. If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation.
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Page 58: Companding
Table 49 PLL Frequency Examples COMPANDING The WM8940 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available. - Page 59 WM8940 Production Data Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): F(x) = ln( 1 + µ|x|) / ln( 1 + µ) -1 ≤...
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Page 60: General Purpose Input/Output
WM8940 Production Data A-law Companding Normalised Input Figure 32 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In 3 wire mode, the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit Whichever pin is used for GPIO, it is controlled from the GPIO control register R8. -
Page 61: Control Interface
2 or 3 wire mode as shown in Table 53. The WM8940 is controlled by writing to registers through a serial control interface. A control word consists of 24 bits. The first 7 bits (B23 to B16) are address bits that select which control register is accessed. -
Page 62: 3-Wire Serial Control Mode
WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MODE_GPIO Selects MODE as a GPIO pin GPIO 0 = MODE is an input. MODE selects 2- wire mode when low and 3-wire mode control when high. 1 = MODE can be an input or output under the control of the GPIO control register. -
Page 63: 2-Wire Serial Control Mode
WM8940 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends the third byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse. -
Page 64: Resetting The Chip
RESETTING THE CHIP The WM8940 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up. - Page 65 WM8940 Production Data Disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB. Ramp up the SPKVOL using the following values: -27 dB, -21 dB, -15 dB, -13 dB, -11 dB, -9 dB, -8 dB, -7 dB, -6 dB, -5 dB, -4 dB, -3 dB, -2 dB, -1 dB, 0 dB.
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Page 66: Power Management
WM8940 Production Data POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. -
Page 67: Pop Minimisation
Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8940. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to be enabled before VMID at start-up. This feature can be used to minimise pops. -
Page 68: Register Map
WM8940 Production Data REGISTER MAP PD, Rev 4.2, April 2008... -
Page 69: Register Bits By Address
WM8940 Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER LABEL DEFAULT... - Page 70 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS MONOEN MONOOUT enable Analogue Outputs 0 = disabled 1 = enabled SPKNEN SPKOUTN enable Analogue Outputs 0 = disabled 1 = enabled SPKPEN SPKOUTP enable Analogue Outputs 0 = disabled...
- Page 71 Sets the chip to be master over FRAME and BCLK Digital Audio Interfaces 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) 7 (07h) 15:7 00000 Reserved PD, Rev 4.2, April 2008...
- Page 72 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS POB_CTRL Power on Bias Control POP Minimisation 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) SOFT_START VMID Soft Start POP Minimisation 0=disabled 1=enabled TOGGLE Fast VMID Discharge...
- Page 73 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS DACMU DAC soft mute enable Output Signal Path 0 = DACMU disabled 1 = DACMU enabled Reserved AMUTE DAC auto mute enable Output Signal Path 0 = auto mute disabled...
- Page 74 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13:0 NF0_A1 0000h Notch Filter 0 a1 coefficient Analogue to Digital Converter (ADC) 18 (12h) NF1_UP Notch filter 1 update. The notch filter 1 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high.
- Page 75 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS LIMEN Output Signal Enable the DAC digital limiter: Path 0=disabled 1=enabled 24 (18h) LIMDCY 0011 Output Signal DAC Limiter Decay time (per 6dB gain change) for Path 44.1kHz sampling. Note that these will scale with...
- Page 76 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 28 (1Ch) 15:0 0000h Reserved 29 (1Dh) 15:0 0000h Reserved 30 (1Eh) 15:0 0000h Reserved 31(1Fh) 15:0 0000h Reserved 32 (20h) 15:10 ALCGAIN [5:0] 000000 Readback from this register will return the ALC gain in...
- Page 77 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS PLLN[3:0] 1100 Integer (N) part of PLL input/output frequency ratio. Master Clock and Use values greater than 5 and less than 13. Phase Locked Loop (PLL) 37 (25h) 15:6 000h...
- Page 78 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS INPPGAVOL 010000 Input PGA volume Input Signal Path 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = 35.25dB 46 (2Eh) 15:0 0000h Reserved 47 (2Fh) 15:9 Reserved PGABOOST...
- Page 79 WM8940 Production Data REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 54 (36h) 15:9 Reserved SPKATTN Attenuation control for bypass path (output of input Analogue Outputs boost stage) to speaker mixer input 0 = 0dB 1 = -10dB SPKZC Speaker Volume control zero cross enable:...
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Page 80: Digital Filter Characteristics
WM8940 Production Data DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner... -
Page 81: Dac Filter Responses
WM8940 Production Data DAC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -120 -0.2 Frequency (Fs) Frequency (Fs) Figure 39 DAC Digital Filter Ripple Figure 38 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -0.2... -
Page 82: Highpass Filter
Production Data HIGHPASS FILTER The WM8940 has a selectable digital high pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz. -
Page 83: Notch Filters And Low Pass Filter
Production Data NOTCH FILTERS AND LOW PASS FILTER The WM8940 supports four programmable notch filters. The fourth notch filter can be configured as a low pass filter. The following illustrates three digital notch filters, followed by a single low pass filter in the ADC filter path. -
Page 84: Notch Filter Worked Example
WM8940 Production Data T T T (dB) Frequency (Hz) Figure 48 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; NF2 fc = 10kHz; LPF fc = 11kHz; fb = 100Hz, 600Hz, 2kHz... -
Page 85: Applications Information
WM8940 Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components PD, Rev 4.2, April 2008... -
Page 86: Package Diagram
WM8940 Production Data PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE 4 0.9 mm BODY, 0.50 mm LEAD PITCH DM035.E DETAIL 1 EXPOSED INDEX AREA GROUND (D/2 X E/2) PADDLE SEE DETAIL 2 TOP VIEW BOTTOM VIEW DETAIL 1 DETAIL 2 0.08... -
Page 87: Important Notice
Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
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