Yamaha Portable Grand DGX-630 Service Manual page 24

DGX-630/YPG-635
R8A02032BG ( X8810A00 ) CPU ( SWX02 )
PIN
OUTER
NAME I/O
NO.
NO.
1 A1 VSS
2 A2 AN2
3 A3 AN1
4 A4 VSS
5 A5 RxD1
6 A6 SCK1
7 A7 UCLK
8 A8 VSS
9 A9 FUNC_DM I/O
10 A10 VSS
11 A11 HOST_DM I/O
12 A12 POWER_ENB
13 A13 XTAL
14 A14 EXTAL
15 A15 VSS
16 A16 CS7N/PJ6
17 A17 TRSTN
A18
18 TDI
19 A19 TCK
20 A20 VCCQ
21 B1 MD15 I/O
22 B2 VSS
23 B3 AN3
24 B4 AN0
25 B5 VSS
26 B6 TxD1
27 B7 TxD0
28 B8 VSS
29 B9 FUNC_DP I/O
30 B10 VSS
31 B11 HOST_DP I/O
32 B12 SCL I/O
33 B13 VSS
34 B14 VSS
35 B15 CS4N/PJ3
36 B16 TIOC0A/PJ7
37 B17 TESTN
38 B18 TMS
39 B19 VCCQ
40 B20
VCCQ
I/O
41 C1 MD13
42 C2 MD14 I/O
43 C3 VSS
44 C4 VREFADC
45 C5 VSSADC
46 C6 VSS
47 C7 RxD0
48 C8 VSS
49 C9 VBUS
50 C10 VSS
51 C11 OVER_CURRENT_N
52 C12 SDA I/O
53 C13 CS0N
54 C14 CS2N/PJ1
55 C15 CS5N/PJ4
56 C16 ASEMDN
57 C17 TDO
58 C18 VCCQ
59 C19 VDDPLL
60 C20 VDDPLL
61 D1 MD10 I/O
62 D2 MD11 I/O
D3 I/O
63 MD12
64 D4 VSS
65 D5 VCCADC
66 D6 VSS
67 D7 RESN
68 D8 VCCQ
69 D9 PULLUP_ENB
70 D10 VCCQ
71 D11 UCTL
72 D12 EICN
73 D13 CS1N/PJ0
74 D14 CS3N/PJ2
75 D15 CS6N/PJ5
76 D16 ASEBRKAKN I/O
77 D17 VCCQ
78 D18 VCCQ
79 D19 VSSPLL
24
FUNCTION
- Ground
I ADC analog input 2
I ADC analog input 1
- Ground
I Serial input 1
I External sync. clock input 1
I USB external clock input (48 MHz)
- Ground
USB function data -
- Ground
USB host data -
O USB voltage enable
O Crystal oscillator output
I Crystal oscillator input (16.9344 MHz)
- Ground
O SH2A-CPU chip select 7
I JTAG test reset input
I
JTAG test data input
I JTAG test clock input
- Power supply +3.3 V
Wave memory data bus 15
- Ground
I ADC analog input 3
I ADC analog input 0
- Ground
O Serial output 1
O Serial output 0
- Ground
USB function data +
- Ground
USB host data +
E bus (I2C) clock input/output (5V compatible)
-
Ground
-
O SH2A-CPU chip select 4
O PWM output
I Test input
I JTAG test mode select input
-
Power supply +3.3 V
-
Wave memory data bus 13
Wave memory data bus 14
- Ground
- ADC reference power supply +3.3 V
- ADC analog ground
- Ground
I Serial input 0
- Ground
I USB cable connection monitor (5V compatible)
- Ground
I USB overcurrent detection (5V compatible)
E bus (I2C) data input/output (5V compatible)
O SH2A-CPU chip select 0
O SH2A-CPU chip select 2
O SH2A-CPU chip select 5
I Debug mode configuration
O JTAG test data output
- Power supply +3.3 V
-
PLL analog power supply +1.2 V
-
Wave memory data bus 10
Wave memory data bus 11
Wave memory data bus 12
-
Ground
- ADC analog power supply +3.3 V
- Ground
I Hardware reset
- Power supply +3.3 V
O USB pull-up enable
- Power supply +3.3 V
I USB output control
O E bus reset output
O SH2A-CPU chip select 1
O SH2A-CPU chip select 3
O SH2A-CPU chip select 6
Emulator break
-
Power supply +3.3 V
-
- PLL analog ground
PIN
OUTER
NAME I/O
NO.
NO.
80 D20 VSSPLL -
81 E1 MD6 I/O
82 E2 MD7 I/O
83 E3 MD8 I/O
84 E4 MD9 I/O
85 E5 VDD -
86 E6 VDD -
87 E7 VSS -
88 E8 VCCQ -
89 E9 VSS -
90 E10 VCCQ -
91 E11 VCCQ -
92 E12 VSS -
93 E13 VCCQ -
94 E14 VSS -
95 E15 VDD -
96 E16 VDD -
97 D31/PF7 I/O
E17
98
E18 D30/PF6 I/O
99
E19 D29/PF5 I/O
100 E20 D28/PF4 I/O
101 F1 MD2 I/O
102 F2 MD3 I/O
103 F3 MD4 I/O
104 F4 MD5 I/O
105 F5 VDD -
106 F16 VDD -
107 F17 D27/PF3 I/O
108 F18 D26/PF2 I/O
109 F19 D25/PF1 I/O
110 F20 D24/PF0 I/O
111 G1 MA2 O
112 G2 MA1 O
113 G3 MD0 I/O
114 G4 MD1 I/O
115 G5 VSS -
116 G16 VSS -
117 G17 D23/PE7 I/O
118 G18 D22/PE6 I/O
119 G19 D21/PE5 I/O
120 D20/PE4 I/O
G20
121
H1 MA6 O
122 H2 MA5 O
123 H3 MA4 O
124 H4 MA3 O
125 H5 VCCQ -
126 H16 VCCQ -
127 H17 D19/PE3 I/O
128 H18 D18/PE2 I/O
129 H19 VCCQ -
130 H20 VCCQ -
131 J1 MA10 O
132 J2 MA9 O
133 J3 MA8 O
134 J4 MA7 O
135 J5 VSS -
136 J9 VSS -
137 J10 VSS -
138 J11 VSS -
139 J12 VSS -
140 J16 VSS -
141 J17 D17/PE1 I/O
142 J18 D16/PE0 I/O
143 CKOEN
J19 I
144
J20 CKIO O
145 K1 MA14 O
146 K2 MA13 O
147 K3 MA12 O
148 K4 MA11 O
149 K5 VDD -
150 K9 VSS -
151 K10 VSS -
152 K11 VSS -
153 K12 VSS -
154 K16 VDD -
155 K17 CKE O
156 K18 D15 I/O
157 K19 VSS -
158 K20 VSS -
DM: IC7
FUNCTION
PLL analog ground
Wave memory data bus 6
Wave memory data bus 7
Wave memory data bus 8
Wave memory data bus 9
Power supply +1.2 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +3.3 V
Ground
Power supply +1.2 V
SH2A-CPU data bus 31
SH2A-CPU data bus 30
SH2A-CPU data bus 29
SH2A-CPU data bus 28
Wave memory data bus 2
Wave memory data bus 3
Wave memory data bus 4
Wave memory data bus 5
Power supply +1.2 V
SH2A-CPU data bus 27
SH2A-CPU data bus 26
SH2A-CPU data bus 25
SH2A-CPU data bus 24
Wave memory address bus 2
Wave memory address bus 1
Wave memory data bus 0
Wave memory data bus 1
Ground
SH2A-CPU data bus 23
SH2A-CPU data bus 22
SH2A-CPU data bus 21
SH2A-CPU data bus 20
Wave memory address bus 6
Wave memory address bus 5
Wave memory address bus 4
Wave memory address bus 3
Power supply +3.3 V
SH2A-CPU data bus 19
SH2A-CPU data bus 18
Power supply +3.3 V
Wave memory address bus 10
Wave memory address bus 9
Wave memory address bus 8
Wave memory address bus 7
Ground
SH2A-CPU data bus 17
SH2A-CPU data bus 16
Clock output control for SDRAM
Clock output for SDRAM
Wave memory address bus 14
Wave memory address bus 13
Wave memory address bus 12
Wave memory address bus 11
Power supply +1.2 V
Ground
Power supply +1.2 V
Clock enable for SDRAM
SH2A-CPU data bus 15
Ground