ABB REL300 Instruction Manual page 7

Significant Changes to Version V2.70 (from V2.10)
(For customers who are familiar with Version 2.00 and beyond)
Please refer to system drawing 2865F41 Sub 2, in I.L. 40-385.4 and drawing 2693F60 in I.L. 40-385.6 for the
following changes.
1. GENERAL APPLICATION UPGRADES
a) CIF trip logic – Added a timer 200/0 between OR222A and AND22 by changing the setting of CIF se-
lection, e.g., the CIF trip with or without the timer is now determined by user. Refer to section 3.4.7 for
the new settings and application.
b) Added an adjustable T1 timer from 0 to 15 cycles in one-cycle steps.
c) Changed the setting ranges of PANG and GANG from 40-90 to 0-90 degrees and ZR setting from 0.1-
7.0 to 0.1-10.0 for underground cable application.
d) Changed LOPB setting from NO/YES to NO/DIST/ALL, i.e., added a setting "ALL" to block trip for LOP
condition. The setting of LOPB=DIST is equivalent to "YES", i.e., block the distance units only.
e) Added PTRI setting (YES/NO) to control the pilot reclose.
f) Added an OR62E gate between the signal T1RI and switch Z1RI for Zone-1 and IT reclose. The
OR62E has three inputs – ITP, ITG and T1RI.
g) Correct the GB trip target error if the input trip currents are removed instantly after the closure of the
trip contacts.
h) Improved Phase Selector for single-pole trip with load current condition.
i) Added NOT logic selection in programmable contact outputs.
j) Desensitized FDOG and RDOG from 3V0 > 1 volt to 3V0 > 3 volts.
k) Can use the pre-fault phase voltages (FDOP) to supervise the Zone-1 and pilot trip for 3-phase fault
condition.
2. POTT SYSTEM IMPROVEMENTS
a) Added a path and an inverter between the output of OR16 and the input of AND45A. Removed the path
between the TBM timer (0/50) and AND45, and added a path and inverter between the TBM timer &
AND34. The TBM is now reset after the PLTG or PLTP picks up for three cycles.
b) Added a path from AND30A (PILOT) to the input of AND65A, i.e., the weakfeed application is for POTT
scheme only.
c) Changed the input of AND49A and AND49E from TRSL to TRSLA (TRSLB or TRSLC for single-pole
trip and keying application).
3. BLOCKING SYSTEM APPLICATIONS
a) Carrier keying logic was modified to speed up resetting TBM for certain types of evolving faults by
changing the input of AND24 from HST to TRSLA/TRSLB/TRSLC.
4. SINGLE-POLE TRIP LOGIC
a) Changed the faulty phase voltage from 0 to the pre-fault voltage after the single-pole trips.
b) Added a negated X2 to disable the LOIB logic and allows the 62T trip under the pole disagreement
condition.
5. SELF-CHECK
a) A self-test was added to indicate the opto-input status in the test mode.
viii
I.L. 40-385.7