ABB REL300 Instruction Manual page 64

I.L. 40-385.7
b. Carrier Keying Logic
(1)
The use of ∆I and ∆V for carrier start provides more security to the blocking scheme.
NOTE:
(2)
(3)
3-20
ceiver receives the blocking signal, disables the operation of AND-47; therefore,
AND-48 will produce no carrier trip signal for AND-52.
Reverse fault keying
For a reverse fault, the ∆I and ∆V as well as the local reverse-looking relay Z3P(R)/
Z3G(R) or RDOG sees the fault, operates the CARSND relay and starts the trans-
mitter, sending a blocking signal to the other terminals.
This keying circuit includes logic OR-50A, AND-50, AND-173, OR-41, AND-51, OR-
18 and AND-35. The signal of 52b to AND-35A is for disabling the "SEND" circuit
when the breaker is open and line side potential is used.
Since the present keying practice on BLK system uses either the contact open (neg-
ative or positive removal keying) or contact close (positive keying) approach, a form-
C dry contact output for keying is provided in REL300.
Signal continuation and TBM logic
For a reverse fault, both the local carrier start relay(s) and the remote pilot relay(s)
see the fault and operate. The local carrier start relay(s) start the carrier and send a
blocking signal to block the remote pilot relay from tripping. After the fault is cleared
by the external breaker, the remote breaker may have a tendency to trip falsely if the
carrier start unit resets faster than the pilot trip unit. The 0/50 ms timer between the
OR-41D and AND-51 holds the carrier signal for 50 ms after the carrier start units
have been reset for improving this problem. This logic also provides transient block
and unblock (TBM) effect on power reversal.
The subsequent out-of-step condition (as described in Section 3.4.17.1), may cause
the reverse looking units to fail to operate on external faults, and introduce false pilot
tripping at the other end. Enhanced logic has been added to the design as shown in
Figure 3-25 (page 3-45), which includes OR-41C, 32/0 ms timer, AND-41B and OR-
41. It utilizes the not FDOP (or FDOG) and LV condition (LV units can be set between
40 and 60 volts) to initiate the TBM circuit; and sends a blocking signal to the remote
end. Set OSB to YES for supervising AND-41B when this enhanced logic is required
in the application. Set WFEN to YES if this terminal may become a weakfeed source.
Internal fault preference and squelch
On an internal fault, the ∆I and ∆V signals also starts the transmitter for 65 ms. This
operation may block the system from pilot tripping. The output signal from OR-40 to
OR-16 to AND-50 and logic OR-16 to AND-120 will provide an internal fault prefer-
ence feature for solving this problem. The squelch 0/150 ms timer is required for
improving the problem if the local breaker tripped faster than the remote breaker on
an internal fault. The logic disables the carrier key circuit (SEND) for 150 ms after
any high speed tripping, including pilot trip, Zone 1 trip and instantaneous overcur-
rent trip.