SDIO CMD Timing Diagram – DDR50 Mode (VIOSD 1.8 V, 50 MHz)
SDIO DAT[3:0] Timing Diagram – DDR50 Mode
16
In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).
Product Specification Rev. 0.1
PAN9026 Wi-Fi/BT Module
16
(VIOSD 1.8 V, 50 MHz)
4 Specification
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