HP 8340A Service Manual page 241

current (through R36) to the YO FM Coil. A Phase-Lag Filter is
incorporated in the feedback of the amplifier which completes
the YO Loop frequency response ·and improves the overall noise
performance of the YO Loop. The output voltage signal is
clamped (by VR4 and VR5) to a maximum of +3.8V to prevent the
op-amp from becoming saturated during phase-lock.
The resistor-capacitor combination of R44-C28 and R43-C29 are
used to provide additional filtering of the power supply inputs
to A49Ul.
Unlocked Detectors
The output of integrator U7 in Loop Integrators
voltage representing the amount of frequency· or phase error
between the YO actual output and what it is supposed to be based
upon the M/N and 20-30 frequencies. This output voltage is
divided by 12 and presented to the comparators of the Unlock
Detector.
Comparator U2B compares the output to -0.SlV which is equivalent
to approximately -6.lV at the output of
U2A compares the output to +0.51V which is equivalent to
approximately +6.lV at the output of integrator U7.
The outputs of these two comparators are wire OR1ed together.
When the input to the Unlock Detector circuit exceeds
approximately +6.lV, one of the comparators will pull up to +20V
which will pulI HULY up to 4.64V
diode VR3). This High Unlock
Loop Interconnect board)
the processor is able to detect this error condition. HULY is
also routed through A50R6, and UlB and UlC
collector inverters) on the ASO YO Loop Interconnect board,
it causes a green LED
LOCKED.
When the output of the Loop Integrators
approximately 6.lV,
-lOV and will thus
HOLY signal will then be pulled LOW by R29,
-0.6V by the (forward biased)
Power Supplies
This circuitry filters the supplies used on this board. The
-5.2VFA supply routed to the analog circuitry is separately
filtered from the -5.2VFB supply for the digital circuitry to
prevent crosstalk. The chassis ground is isolated from the
Reference ground through R38. FM ground is connected to Reference
Model 8340A - Service
J
(HULY) signal is routed
to the A59 Digital Interface board where
(ASO DSl) to light whenever the YO Loop is
both comparator outputs will pull down to
reverse bias the two diodes
zener diode VR3.
K
Scans by HB9HCA and HB9FSX
(Block
integrator U7.
(where it is clamped by
(darlington open
(Block
F)
CR3 and
being limited to
is a
F)
Comparator
zener
(via the ASO
where
is within
CR4. The
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