HP 8340A Service Manual page 179

A42 PHASE LOCK LOOP 2 (PLL2) DIVIDER,
INTRODUCTION
The PLL2 Divider Board has two functions:
Generate the 500 kHz reference signal which is used by the
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PLL2 Phase Detector Board. This is accomplished by dividing
the lOMHz quartz crystal reference oscillator by 20.
Divide the PLL2 VCO output signal A42Wl
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100 to 150 MHz when not sweeping)
200.01 and 300 so that the resulting frequency is 500 kHz.
The two signals above are sent to the PLL2 Phase Detector board
so that phase lock can be achieved.
The circuit which performs the first function is explained in
REFERENCE DIVIDER
Divider board performs the second function. Refer to Figure 8C-29
for a simplified block diagram of this section of the PLL2
DIVIDER.
Refer to the "Frequency Range and CW Mode Accuracy" Performance
Test for use as a troubleshooting aid.
LATCHES A
Latches Ul2, Ul3,
the various counters on the PLL2 Divider board. The schematic
(Figure 8C-32) shows the relationship of each output line to the
frequency of the PLL2 vco.
determined by adding the total of each individual output's
contribution (if the output is HIGH)
from 150 MHz. For example,
HIGH and all the other outputs of Ul4 as well as U2 and Ul3 were
LOW the total contribution would be 40 MHz
frequency of the PLL2 VCO would then be 150-45
Ul4 pin 12 and Ul4 pin 15,
to the PLL2 VCO board and are used for control.
REFERENCE DIVIDER
A 10 MHz signal derived from the quartz crystal reference
oscillator is amplified by Q2 and used to drive divider U4. The
Model 83 40A - Service
CIRCUIT DESCRIPTION
(Block D). The remaining circuitry on the PLL2
and Ul4 store the BCD numbers used to preset
The frequency of the VCO can be
if Ul4 pin 10 and Ul4 pin 2 are both
SWl and SW2 respectively,
D
Scans by HB9HCA and HB9FSX
(which can range from
by some number between
and subtracting that total
5 MHz
+
=
105 MHz.
=
45 MHz. The
are routed
'
8-249