HP 8340A Service Manual page 130

INTRODUCTION
PLLl
(Phase Locked Loop 1)
It consists of the following assemblies:
A36 PLL 1 VCO
mi
A37 PLLl DIVIDER
�
A38 PLLl IF
181
DESCRIPTION
The PLLl and PLL3 phase-lock loops are only used when in CW Mode
or in swept frequency modes with YO sweep widths less than 100
kHz.
PLLl functions as a programmable frequency translator. The input
to the translator is the PLL3 output
PLLl VCO frequency is offset by a programmable amount from the
PLL3 output. As the PLL3 output changes frequency
tracks a sweeping PLL2)
output and the PLLl VCO output will remain constant. The offset
frequency, PLLl IF output, is determined by the value of
programmable divider Nl and is constant throughout the sweep. The
result is that the precision sweeps and high resolution of the
PLL2 Loop are effectively tra
vco.
A simplified diagram of the PLLl Loop is shown in Figure.SC-6.
The phase/frequency detector for PLLl,
PLLl DIVIDER assembly,
detector inputs comes from a 10 MHz
Detector) reference
The second phase detector input is the PLLl IF output,
passing through a divide-by-two and a fractional divider. The
fractional divider uses pulse-swallowing techniques to divide by
numbers between 3.60 and 13.97.
When the loop is locked,
in frequency. The PLLl IF output is then described by;
10 MHz, where Fl is the PLLl IF output frequency MHz and Nl is
the fractional divide number
The A38 PLLl IF assembly's primary function is to mix the output
of PLLl vco with the output of the PLL3 Loop
frequency relationships at the mixer are;
Model 8340A - Service
PLLl OVERALL DESCRIPTION
is part of the 20-30 Loop Synthesizer.
the offset frequency between the PLL3
'
nsferred up in frequency to
operates at 5 MHz. One of the phase
which is divided by two on the A37 assembly.
both phase detector inputs will be equal
(3.60 to
Scans by HB9HCA and HB9FSX
(160.15 to 166 MHz}.
(ie. as it
which resides on the A37
(A29 Reference Phase
13.97}.
(Fpll3).
F2 - Fpll3,
Fl
=
The
the PLLl
after
Fl
Nl
*
=
The
where
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