HP 8340A Service Manual page 119

Loops are used to translate the high resolution,
output up to a 200 to 300 MHz range. Since a translation is a fixed
offset in frequency,
dividing or multiplying. After the frequency translation,
output of PLLl is
200-300 MHz to 20-30 MHz. This also increases the output resolution
by a factor of 10 .
PLL3 functions as a fixed
output. PLL3 phase-locks a 160 to
down outputs of the PLL2 vco,
above the selected PLL2 ou
the 100 MHz VCXO reference to generate the
frequency. As the PLL2 divided-down output changes frequency,
PLL3 output will also change frequency with the same resolution and
sweep width, but at a higher operating frequency.
PLLl functions as a programmable offset to the output of PLL3. Like
PLL3,
it will not effect the resolution since it is an offset. The
selected PLL2 divided output is still determining the resolution
and sweep width of the signal. PLLl contains a 200 to 300 MHz VCO
that will be locked such that its frequency will be exactly Nl*lO
MHz above the PLL3 output,
3.60 and 13.97.
The output of the PLLl VCO is divided by 10 to become the output of
the 20-30 Loop for configuration 2 and 3. By dividing by 10, the
PLLl 200-300 MHz vco is reduced to the 20 to 30 MHz range and the
PLL2 MHz resolution is increased by another factor of 10.
Refer to Figure
20-30 Loop Simplified
The three configurations are summarized in Table 8C-l.
Model 8340A - Service
it will not change the resolution as does
divided by 10 to
.
160 MHz frequency offset to the PLL2
such that PLL3 vco will be
t
put. PLL3 uses a reference signal from
where Nl is a number programmed between
8C-7, 20-30 Loop Block Diagram,
Block Diagram,
Scans by HB9HCA and HB9FSX
low frequency PLL2
reduce the frequency from
166 MHz VCO to one of the divided
160 MHz off setting
or Figure
for further information.
the
160 MHz
the
8C-l,
8-163