Cpci-Frm11 Functions - DAQ cPCI-FRM11 User Manual

2. cPCI-FRM11 Functions

As shown in the following figure, main control of the board is performed in FPGA Core Logic.
Primary functions are receiving the image frame data, transmitting/receiving UART data and controlling
CC(Camera Control signal).
You can control these functions using API provided by DAQ system.
PCI BUS
The core logic program of the FPGA is loaded by JTAG. It saves a program at the FPGA Program
Logic and loads when power-up.
cPCI-FRM11 INTERNAL BLOCK - FPGA
PCI Target
/ Master
MEM Decoder
To each IO
Module
IO Decoder
DPRAM
CLOCK syn.
Interrupt
Controller
(0xb0)
INT sources in Chip
From Ext.
[Figure 2-1. Functional Block Diagram]
cPCI-FRM11 User's Manual (Rev 1.1)
Local Bus
Address
Data(Mem,I/O)
BUS Mux
Interrupt controller
Camera Link(LVDS)
Ext. Address, Data, Control
4
- -
Reserved
(0x00 – 0x5F)
UART
(0x60)
Reserved
(0x70 – 0xAF)
(0xC0)
DIO
(0xD0)
Reserved
(0xE0 – 0xFF)
MEM Decoder
http://www.daqsystem.com
Local BUS