TTI TSX Series Service Manual page 8

HF Switch Drive - IC1 PWM outputs A and B are applied via driver IC11 to each end of drive
transformer T3 primary, providing alternating antiphase PWM outputs of about 12V peak from
each secondary. Gate resistors R18,R22 slow Q1,Q2 switching transitions to about 100nsec to
limit RFI generation. R9,C14 and R10,C15 minimise drive waveform overshoot and cross
conduction of Q1,Q2. Schottkys D8,D9 avoid IC11 substrate reversal.
Soft Start - If IC1 detects VCC undervoltage, PWM generation is inhibited and soft start capacitor
C18 discharged. When VCC is adequate and PWM generation is enabled IC1 charges C18
slowly. The PWM on pulse width is internally limited by the voltage on C18. As C18 charges
narrow PWM pulses appear at about +1.25V which widen steadily until IC1 error amplifier takes
control. This feature allows orderly start up of the switchmode section after switch on.
Dual Function Opto-coupled Control - OPTO1 provides both analogue feedback for PWM
control and digital shut down control across the isolation boundary to the switchmode section. In
normal operation OPTO1 input current drive is arranged to ensure a minimum output current of
about 40 microamps. When switchmode shutdown is required the Supervisory System described
later cuts off OPTO1 input turning off Q13, inhibiting PWM output via D7,R157,Q3,Q7 and
clearing soft start capacitor C18.
PWM Control - OPTO1 collector feeds the error amplifier of IC1 (output at COMP) which is
operated in virtual earth mode to maximise optocoupler bandwidth. Clamp Q20 improves
amplifier overload behaviour. PWM output pulses cease at OPTO1 minimum current level.
Switchmode Protection - T2 primary current is returned via current transformer T4 primary.
Virtually instantaneous protection against gross overcurrents following severe faults is effected
when T4 secondary output rectified by D21,D22 generates enough voltage across R156 to turn
on Q3,Q7 regeneratively via spike filter R121,C68. PWM output is immediately inhibited and soft
start capacitor C18 discharged. If the cause of overcurrent persists the process will repeat
(hiccough) after the subsequent soft restart. The limiting of peak operational current levels is
described later under Switchmode Current Limiting. If switchmode heatsink SK1 temperature
exceeds about 100 deg C thermostat TS1 opens triggering latch Q3,Q7 on via Q13,D7,R157.
This condition is registered elsewhere by supervisory logic to avoid automatic restart after
cooling.
HF Rectification and Filtering - The centre tapped secondary of T2 feeds ultra fast epitaxial
dual rectifier diode D14 which delivers rectified or freewheel current to HF power choke L3.
R75,C65 and R66,C64 reduce diode reverse recovery voltage spikes. Ferrite choke L3 and
reservoirs C73,(C74),C33 form a low pass choke input filter delivering low ripple DC output
voltage proportional to pulse width. R55 provides the minimum loading necessary for control over
the full 38 to 1.5 VDC output range.
Series Regulator Power Elements - Parallelled plastic cased bipolar power transistors are used.
35V/10A supplies use two devices sharing the single secondary side heat sink with rectifier D14
and driver transistor Q4 while 18V/20A supplies use four devices mounted on a separate
heatsink. Emitter resistors (R38-R41 as appropriate) ensure current sharing. Device dissipation is
minimised by using the switchmode section to regulate the collector-emitter voltage at about 1.5V.
Driver transistor Q4 is mounted on the same heatsink as D14. To avoid the premature driver
collector saturation of the Darlington connection, Q4 collector voltage is maintained about 3V
above the output transistor collectors by a floating auxiliary supply. R44,Q29 limit driver current to
about 2A. Voltage and current error amplifier outputs are applied to the driver via predriver
circuitry D11,D12,R34,Q8,R12. Driving ENABLE low shuts down the linear regulator.
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