Main Board Circuit Description; Overview; Mains Input, Switchmode And Linear Power Sections - TTI TSX Series Service Manual

Overview

The main board comprises a mains driven HF switchmode DC-DC isolating convertor using pulse
width modulation (PWM) which feeds a linear regulator operating at low input-output voltage
difference as shown in the skeleton circuit diagram opposite.

Mains Input, Switchmode and Linear Power Sections

Component references are to sheet 1 of the circuit diagram unless stated.
Mains Input Components and Fusing - When the power supplies are used on 240V, fused plug
tops should be fitted with a 5A fuse. The mains supply enters at the IEC receptacle on the rear
panel and is wired, via the front panel mains on-off double pole switch, to Faston connectors on
the main PCB. A 10A PCB mounted fuse F1 limits damage on switchmode failure. Varistor VDR1
clips mains 'spike' voltages for component protection. R212 provides safety discharge for C1,C2.
Input Noise Filter - Double wound filter choke L1, X capacitors C1,C2 and Y capacitor C4
provide low pass HF filtering to minimise noise currents injected into the mains supply by the
switchmode section. Y capacitor C4 also provides a low impedance HF path from the switchmode
section to case/earth.
Mains Voltage Selection - Voltage selector SW2 connects BR3 and series connected reservoirs
C9,C10 for bridge/voltage doubler rectification and the two 120V primary sections of 50 Hz
auxiliary transformer T1 in series/parallel in its 230/115V positions respectively. Rectified voltage
is 200-380 VDC. R5,R6 ensure voltage sharing and provide a safety discharge path for C8,C9.
C3,C7,C8 minimise rectifier snap-off transients and HF noise.
Mains Inrush Control - At switch on triac TC1 blocks and reservoirs C9,C10 charge up slowly
via the 33Ω of cold thermistor PTC1; this action also causes the primary peak voltage across
auxiliary transformer T1 and the inrush control voltage across C6, derived from a T1 primary tap,
to increase slowly. When the latter reaches about 8V enough current flows through R3,D10,R92
to trigger latch Q5,Q6 on, providing continuous drive to TC1 gate. D15 inhibits triggering during
BR3 conduction to avoid sudden connection of rectified mains voltage to reservoirs C9,C10.
Once turned on TC1 remains conductive until AC supply ceases or falls to a very low level
unlatching Q5,Q6. If TC1 fails to turn on, thermistor PTC1 switches into a high resistance state
within a few seconds, protecting itself against overtemperature and disabling the power supply.
HF Power Switching Stage HV power FETs Q1,Q2 form a totem pole switch that switches the
primary of the ferrite HF power transformer T2 to HV DC rails VRECT+ or VRECT- during on
periods and presents an open circuit during the off period of the PWM waveform. C11,C12 allow
the return end of the primary winding to assume about mid-rail voltage and provide low
impedance HF returns to either rail for the primary current. Snubber C13,R7 absorbs most of the
spike energy stored in the leakage inductance of T2 at FET switch off. T2 primary is returned via
current transformer T4. Plug PJ4 allows disconnection of Q1,Q2 from the HV rail during testing.
Switchmode auxiliary supply - Stabilised +12V at 50 mA for the PWM driving circuits is derived
from a primary side auxiliary winding on T1 via BR1,C25,IC2. PWM switching controller IC1
incorporates undervoltage lockout which inhibits operation until VCC reaches about 9V.
PWM Generation - The oscillator of PWM controller IC1 runs at about 160 kHz for 80 kHz PWM
output and generates a master saw- tooth waveform across timing capacitor C19 swinging
between about +0.9 and +2.8V. Minimum PWM deadtime of approximately 680 nsec corresponds
to the reset (negative going) stroke of this waveform. The PWM on pulse starts at the beginning
of the upward ramp and is terminated when the ramp voltage rises to about 1.25V below the DC
level at the error amplifier output COMP. Ramp charging current into C19 is proportional to the
current drawn from pin RT and is set by R14 for the main part of the PWM on time. The positive
pulse from IC1 CLK output turns on Q30 via C49,R49 discharging C50 during ramp reset. When
the upward ramp starts, C50 recharges rapidly through R47 momentarily increasing C19 charging
current and ramp slope over the first 300 nsec or so of the on period. This arrangement allows
stable generation of very narrow on pulse widths required at very low output voltages.
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Main Board Circuit Description