Linear Regulator Checks; Testing Main Pcb With Lv On Hf Switching Section - TTI TSX Series Service Manual

Linear Regulator Checks

1. Check/Preadjust Voltage Zero - Connect an external +5VDC, 2A limited power supply
between DCVOUT (+ve) and VOUT- (access top R55 and D37 respectively). Set Voltage
control(s) to minimum and Current control to maximum. Switch Output on. Switch supplies
on. CV LED should come on. Adjust VR3 for zero output voltage within 5 mV.
2. Check/Preadjust Current Zero - Connect 10Ω 10W load to output terminals. Set Voltage
control(s) to maximum and Current control to minimum. Adjust VR8 for zero output voltage
within 20 mV. CI LED should be on. Note and avoid saturated region below about -20 mV.
3. Check All Series Pass Transistors Active - Short circuit output. Set current control to
maximum. Check that voltage across each emitter resistor R38- 39/R38-41 is at least 10mV.
4. Check Linear Reg Shutdown - Trip the supervisory logic trip by momentarily connecting 0V
to IC9 pin 13 with pointed probe lead. The output voltage should fall below -20mV. Reset
the logic by momentarily connecting 0V to PJ1- 27.
5. Check Output Off Level. Switch Output off. Disconnect load. Output voltage should lie
between -0.25V and -0.15V. Disconnect +5V external supply.

Testing Main PCB with LV on HF Switching Section

1. Preparation - Allow time or discharge HV reservoirs C9,10 then connect external 60V 2A
limited PSU to switchmode section via connector lead of Fig 1 to PJ4. Connect 3.75Ω
load. Switch PSU off.
2. Check Switchmode Master/Clock Waveform - Connect CRO via x10 probe between
VRECT- (common) and IC1 pins 6,7. Check ramp waveform against Fig 4 observing:
(i)
(ii)
(iii)
(iv)
3. Check Power On Soft Start - Connect CRO via X10 probe to IC1 pin 8. Turn mains
supply to board off and on. The soft-start voltage should fall immediately to less than +1V
then rise slowly (about 0.5 sec) to about +4.5V.
4. Check Demand and Gate Waveforms - Turn voltage and current controls to maximum.
Q1 gate drive waveform should be an almost square, approximately 20V pk-pk waveform
swinging symmetrically about 0V. Q2 drive waveform may also be checked if node HF is
momentarily linked to VRECT-. Switch off.
5. Check Power FETs Blocking - Connect CRO between VRECT- and switchmode output
point HF. Set Voltage control(s) to minimum, Current control to maximum and Output off.
Switch 60V PSU on. No current should be drawn.
6. Check Switchmode Idling Waveforms and Pre-regulator Overhead - Switch on.
Current from 60V supply should still be less than 10 mA. Waveform at point HF should
show narrow symmetrical alternating pulses and very slow no-load ringing. At R10/22
junction the positive gate drive pulse should exceed +6V for 100-200ns. Linear regulator
overhead voltage between 0V and DCVOUT should be 1.7 to 1.9VDC.
7. Check Switchmode Waveforms - Switch Output on. Waveform at point HF should not
change. If Voltage control is advanced PWM duty cycle at point HF should increase with
rectangular PWM pulses of about 60V pk-pk amplitude separated by a plateau at 30V as
shown in Fig 5. Maximum duty cycle should occur at about 10V/5V DC output. Storage
spikes at point HF are then typically 20V pk and 100ns base width.The PWM waveform
edges should be stable; however instability or lack of output may be cured in the next
section.Remove all instrument connections from the primary side circuitry.
Basically saw tooth of period of 5.9 to 6.7 usec.
Downward stroke duration approx 0.7 usec.
Voltage swinging between approx +0.9V and +2.8V.
Fast rising section over first approx 0.7 usec of ramp.
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