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Neoway N720 OpenLinux Hardware User's Manual

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N720 OpenLinux
Hardware User Guide
Issue 1.4
Date 2019-03-25
Neoway Product Document

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Summary of Contents for Neoway N720 OpenLinux

  • Page 1 N720 OpenLinux Hardware User Guide Issue 1.4 Date 2019-03-25 Neoway Product Document...
  • Page 2 THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS. PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION. NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY IMPROPER OPERATIONS. THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO PRODUCT VERSION UPDATE OR OTHER REASONS.

  • Page 3: Table Of Contents

    N720 OpenLinux Hardware User Guide Contents 1 About N720 OpenLinux ................1 1.1 Product Overview ......................... 1 1.2 Block Diagram ..........................2 1.3 Basic Features ..........................3 2 Module Pins ....................6 2.1 Pad Layout ........................... 6 3 Application Interfaces ................15 3.1 Power Interface ..........................
  • Page 4 8 Safety Recommendations ............... 81 A Conformity and Compliance ..............82 A.1 Approvals ........................... 82 A.2 Chinese Notice........................... 82 A.2.1 CCC Class A Digital Device Notice ................... 82 A.2.2 Environmental Protection Notice ..................82 B Abbreviation .................... 83 Copyright © Neoway Technology Co., Ltd...
  • Page 5 Hardware User Guide Table of Figures Figure 1-1 Block Diagram ........................3 Figure 2-1 N720 OpenLinux pin definition (Top View) ............... 6 Figure 3-1 Current peaks and voltage drops ................... 16 Figure 3-2 Recommended design 1 ....................16 Figure 3-3 Recommended design 2 ....................17 Figure 3-4 Recommended design 3 ....................
  • Page 6 Figure 3-52 Reference Design of Passive GNSS Antenna .............. 56 Figure 3-53 Reference design of active GNSS antenna ..............57 Figure 3-54 Reference layout of GNSS antenna traces ..............58 Figure 3-55 Specifications of MM9329-2700RA1 ................59 Figure 3-56 RF connections ......................59 Copyright © Neoway Technology Co., Ltd...
  • Page 7 Figure 3-63 Reference design of USB_BOOT ................. 66 Figure 6-1 N720 dimensions ......................74 Figure 6-2 N720 Openlinux label ..................... 75 Figure 6-3 N720 OpenLinux packing with vacuum bag and tray ............. 76 Figure 6-4 Packaging process ......................76 Figure 7-1 Bottom view ........................78 Figure 7-2 Recommended Application Foot Print (Top View) ............
  • Page 8 Table 4-1 Electric features ........................ 67 Table 4-2 Temperature features ....................... 67 Table 4-3 ESD protection features ....................68 Table 5-1 Operating Bands ......................69 Table 5-2 RF TX power ........................70 Table 5-3 RF RX sensitivity ......................71 Copyright © Neoway Technology Co., Ltd...
  • Page 9 Scope This document is applicable to N720 OpenLinux series. It defines the features, indicators, and test standards of the N720 OpenLinux module and provides reference for the hardware design of each interface. Reference designs in this document are only for reference. Customers should design applications based on the actual scenarios and conditions.Please contact Neoway FAE if you have any question or...
  • Page 10 Hardware User Guide Modified the resistance of a resistor in level shifting  circuit 2. Modified description  Modified the pin definition according to Neoway  Module Pin Definition Updated Chapter 3.  Updated the block diagram of N720 2019-01 Dong Liuting ...

  • Page 11: About N720 Openlinux

    OpenLinux is well applicable to Mi-Fi, in-vehicle terminals, POS, industrial routers, and other IoT terminals. 1.1 Product Overview N720 OpenLinux series include multiple variants. Table 1-1 lists the variants and frequency bands supported. Table 1-1 Variant and frequency bands Version Region...

  • Page 12: Block Diagram

    GSM/GPRS/EDGE: 850/900/1800/1900 MHz FDD-LTE: B1, B3, B7, B8, B28 Taiwan Cat4 UMTS: B1, B8 support GSM/GPRS/EDGE: 900/1800 MHz 1.2 Block Diagram N720 OpenLinux consists of the following functionality units: Baseband   Power management unit  19.2MHz crystal oscillator ...

  • Page 13: Basic Features

    Dimensions: 30 mm * 28 mm * 2.8 mm Physical features Weight: around 5.1g Operating: -35° C to +75° C Temperature Extended: -40℃ to +85℃ ranges Storage: -45° C to +90° C Operating voltage VBAT: 3.3V to 4.3V, TYP: 3.8V Copyright © Neoway Technology Co., Ltd...
  • Page 14 Idle mode indicates the status of no service when the module is running. Current in operating mode indicates the current during data communication. For currents of other network modes and bands, see N720 Current Test Report. Copyright © Neoway Technology Co., Ltd...
  • Page 15 One SDIO interface, used to control WLAN One SGMII/MDIO interface, used for Ethernet Four GPIO interfaces AT Command Neoway extended commands Data PPP, RNDIS, ECM, RMNET Protocol TCP, UDP, MQTT, FTP/FTPS, HTTP/HTTP(S), SSL, TLS Certification CCC, SRRC, RoSH, CE approval Copyright © Neoway Technology Co., Ltd...

  • Page 16: Module Pins

    N720 OpenLinux Hardware User Guide 2 Module Pins There are 100 pins on N720 OpenLinux and their pads are introduced in LGA package. 2.1 Pad Layout Figure 2-1 shows the pad layout of N720 OpenLinux. Figure 2-1 N720 OpenLinux pin definition (Top View)

  • Page 17: Table 2-1 Io Types And Level Features

    USIM2 and MDIO interface =1.26V~2.1V =2V~3.15V, voltage, compatible with =-0.3V~0.36V =-0.3V~0.57V 1.8V/2.85V =1.44V~1.8V =2.28V~2.85V =0V~0.4V =0V~0.4V =1.2V, V = 0.3V IH min IL max 1.8V digital IO voltage =1.35V, V = 0.45V OH min OL max Copyright © Neoway Technology Co., Ltd...

  • Page 18: Table 2-2 Pin Description

    =50mA floating if it is not used. Used to pull up the crystal oscillator of external WLAN =1.8V norm DVDD_XO_1P8 1.8V power output module =20mA Leave this floating if it is not used. Copyright © Neoway Technology Co., Ltd...
  • Page 19 =50mA module compatible with USIM1_DATA USIM data IO 1.8V 2.85V USIM cards. USIM1_CLK USIM1 clock output Connect DATA pin USIM1_RESET USIM1 reset USIM_VCC through a 10 kΩ USIM1_DET USIM1 detect pull-up resistor. Leave them Copyright © Neoway Technology Co., Ltd...
  • Page 20 SGMII_RX_P SGMII receive plus MDIO Control Interfaces For MDIO data line to be connected through a pull-up USIM2_VCC USIM2 power output resistor Compatible with 1.8 V/3 V UIM card SGMII_MDIO_CLK SGMII clock output Multiplexed Copyright © Neoway Technology Co., Ltd...
  • Page 21 WLAN_SDIO_DATA_1 SDIO data1 IO floating if it is not used. Leave this WLAN_SDIO_DATA_2 SDIO data2 IO floating if it is not used. Leave this WLAN_SDIO_DATA_3 SDIO data3 IO floating if it is not Copyright © Neoway Technology Co., Ltd...
  • Page 22 BT_UART_RTS Request to send BT_EN Bluetooth enable Leave this BT_WAKEUP_HOST Bluetooth wakeup host floating if it is not used. Leave this BT_WAKEUP_SLAVE Bluetooth wakeup slave floating if it is not used. Copyright © Neoway Technology Co., Ltd...
  • Page 23 GPIO_77 GPIO without interrupt floating if it is not used. Leave this GPIO_78 GPIO without interrupt floating if it is not used. Leave this GPIO_79 GPIO with interrupt floating if it is not used. Copyright © Neoway Technology Co., Ltd...
  • Page 24 Do not pull this pin External power high before OTG_5V_EN enable module is powered Leave this NET_LIGHT Network status indicator floating if it is not used. Leave this GNSS_LNA_EN GNSS LNA enable floating if it is not used. Copyright © Neoway Technology Co., Ltd...

  • Page 25: Application Interfaces

    Hardware User Guide 3 Application Interfaces N720 OpenLinux provides power supply, control, communications, network and connection, RF, and other interfaces to meet customers requirements in different application scenarios. This chapter describes how to design each interface and provides reference designs and guidelines.

  • Page 26: Figure 3-1 Current Peaks And Voltage Drops

    The power supply design covers two parts: schematic design and PCB layout. Schematic Design Design the circuit of the power supply for N720 OpenLinux based on the input voltage you choose.Generally there are three types of input voltages: 3.3V-4.3V (3.8V typically, output by battery) ...

  • Page 27: Figure 3-3 Recommended Design 2

    If a digital NPN bipolar transistor is used, omit R1 and R2. TVS diodes work in the same way as those in Figure 3-2 and they should meet the same  requirements. Figure 3-4 shows schematic design recommended for 4.3V-5.5V input. Copyright © Neoway Technology Co., Ltd...

  • Page 28: Figure 3-4 Recommended Design 3

    500 kHz or larger switching frequency is recommended for DC-DC. The inductance depends on  the switching frequency. The switching frequency might produce EMC noise and it determines the performance of end products. For more design guidelines, see TPS54340 datasheet.  Copyright © Neoway Technology Co., Ltd...

  • Page 29: Vdd_1P8

    Connect GND pins and bottom pads to ground to optimize heat sink and separate noise.  3.1.2 VDD_1P8 N720 OpenLinux provides one VDD_1P8 output, load current lower than 50 mA. It is recommended that VDD_1P8 is used only for level shift and digital IO power supply. An ESD Copyright © Neoway Technology Co., Ltd...

  • Page 30: Control Interfaces

    PWRKEY_P ON/OFF button Triggered by high level N720 OpenLinux provides two PWRKEY pins: PWRKEY_N and PWRKEY_P, respectively triggered by low level and high level. It is recommended to use PWRKEY_N. 3.2.1 PWRKEY_N N720 OpenLinux allows startup by the following controls: Button ...

  • Page 31: Figure 3-6 Reference Design Of Startup Controlled By Button

    Figure 3-8 Reference design of automatic start once powered up PWRKEY_N 1.5 kΩ Startup Process After powering up the VBAT pin, input a negative pulse of wider than 100 ms (longer than 200 ms is Copyright © Neoway Technology Co., Ltd...

  • Page 32: Figure 3-9 N720 On/Off Timing

    For how to power off through software, see Neoway_N720 OpenLinux_AT_Command_Manual. Figure 3-9 N720 on/off timing Power Power Inactive Active Inactive VBAT t >2s t >200ms PWRKEY_N <0.6V <0.6V RESET_N Active Inactive Inactive All Interfaces Active Inactive Inactive Time Copyright © Neoway Technology Co., Ltd...

  • Page 33: Reset_N

    N720 module Figure 3-11 Reset circuit with triode separating RESET_N VCC_2P8/3P0/3P3 N720 module 4.7kΩ VDD_1P8 Figure 3-12 shows the reset timing of N720 OpenLinux. Figure 3-12 Reset timing of N720 OpenLinux VBAT RESET_N t≥1s <0.6V Active Inactive All Interfaces Copyright © Neoway Technology Co., Ltd...

  • Page 34: Peripheral Interfaces

    USB_DP AIO USB data positive signal 90Ω impedance for differential traces. USB_ID USB ID Used for OTG function USB can be used to download firmware for N720 OpenLinux and establish data communication for Copyright © Neoway Technology Co., Ltd...

  • Page 35: Figure 3-13 Usb Connection

    USB_ID is used for the OTG function. Pull USB_ID to low level, and the module will work in host  mode. To use the OTG function, supply a voltage to USB_VBUS. See Figure 3-14. Copyright © Neoway Technology Co., Ltd...

  • Page 36: Usim

    USIM1 detect A pull-up resistor is recommended N720 OpenLinux provides one USIM1 interface by default. USIM2 interface is a multiplex function of Ethernet interface and compatible with 1.8V/2.85V USIM card. For details, see Section 3.7 MUX Interfaces. Figure 3-15 shows the reference design of the USIM card interface.

  • Page 37: Uart

    UART5 data receiving Used for data transmission N720 OpenLinux provides one UART interface. To support hardware flow control, multiplex pin 51 and pin 52 as UART5_CTS and UART5_RTS. UART interfaces support 4 Mbps at most. The level at the interfaces 1.8V. To use multiple UART interfaces, see Section 3.7 MUX Interfaces. Figure 3-16 And Figure 3-17 show the reference designs of the UART interfaces.

  • Page 38: Figure 3-16 Reference Design Of Uart Connection (With Flow Control)

    Three types of level shifting circuit is recommended based on the logic level quality. If the low level at MCU_UART (V ) is lower than 200mV, adopt recommended level shifting circuit 1. Copyright © Neoway Technology Co., Ltd...

  • Page 39: Figure 3-18 Recommended Level Shifting Circuit 1

    If the low level at MCU_UART (V ) is lower than 200mV, adopt recommended level shifting circuit 2. Otherwise, low level at UART might be higher than required, resulting in failure to identify signals. Copyright © Neoway Technology Co., Ltd...

  • Page 40: Figure 3-19 Recommended Level Shifting Circuit 2

    UART_RXD are respectively the TX and RX of the module. VCC_IO is the IO voltage of the MCU. Level shift chip is recommended if the level of MCU is larger than 3.3V or the baudrate is higher than 1 MHz. Copyright © Neoway Technology Co., Ltd...

  • Page 41: Sdc

    SDC clock output SDC_CMD SDC command SDC_DATA0 SDC data bit 0 SDC_DATA1 SDC data bit 1 SDC_DATA2 SDC data bit 2 SDC_DATA3 SDC data bit 3 SDC_DET SD card detect SDC_PWR_EN Control of SD external power Copyright © Neoway Technology Co., Ltd...

  • Page 42: Figure 3-21 Sd Connection

    VDD_SDC_IO is the power supply to which the DATA and AMD signals of SDC connect through  a pull-up resistor. The power source is determined by the IO level of SD chipset. If the IO level is Copyright © Neoway Technology Co., Ltd...

  • Page 43: Figure 3-22 Sdc Sdr Timing

    For the timing of the SDC interface in SDR and DDR mode, see Figure 3-22 and Figure 3-23. For parameter values for the SD interface, see Table 3-4. Figure 3-22 SDC SDR timing SDC_CLK t(csurd) t(chrd) t(dsurd) t(dhrd) Read t(pddwr) t(cdvrd) t(pdcwr) t(dvrd) Write Copyright © Neoway Technology Co., Ltd...

  • Page 44: Figure 3-23 Sdc Ddr Timing

    DDR mode (max. 50MHz) t(chrd) Command hold time t(csurd) Command set-up time (dhrd) Data hold time t(dsurd) Data set-up time Delay time from data write to t(pddwr) transmit Delay time from command write t(pdcwr) -8.2 to transmit Copyright © Neoway Technology Co., Ltd...

  • Page 45: I2S/Pcm

    Codec N720 module Schematic Design Recommendations If the levels of N720 OpenLinux and CODEC do not match, add a level shift circuit as shown in  3.3.4. Leave I2S_MCLK floating in your application if it is not required for the CODEC chipset selected.

  • Page 46: Figure 3-25 I2S Timing

    PCM interface supports primary mode and auxiliary mode. Table 3-6 PCM work modes Mode Synchronization Mode Work Mode Primary Mode Short sync Host mode or device mode Auxiliary Mode Long sync Host mode Figure 3-26 shows PCM connection. Copyright © Neoway Technology Co., Ltd...

  • Page 47: Figure 3-26 Pcm Connection

    Figure 3-28 PCM data input timing in primary mode t(clk) t(clkh) t(clkl) PCM_CLK t(sus t(hsync) ync) PCM_SYNC t(hdin) t(sudin) PCM_DIN Figure 3-29 PCM data output timing in primary mode t(clk) t(clkh) t(clkl) PCM_CLK t(susync t(hsync) PCM_SYNC t(pdout t(pdout t(zdout) PCM_DOUT Copyright © Neoway Technology Co., Ltd...

  • Page 48: Figure 3-30 Pcm Sync Signal Timing In Auxiliary Mode

    Figure 3-30 PCM sync signal timing in auxiliary mode t(auxsync) PCM_SYNC t(auxsynca) t(auxsyncd) Figure 3-31 PCM data input timing in auxiliary mode t(auxclk) t(auxclkh) t(auxclkl) AUX_PCM_CLK t(hauxsync) t(suauxsync) AUX_PCM_SYNC t(suauxdin) t(hauxdin) AUX_PCM_DIN MSB-1 (Companded) AUX_PCM_DIN MSB-1 MSB-2 MSB-8 (Linear) Copyright © Neoway Technology Co., Ltd...

  • Page 49: Spi

    1.95 rising t(suauxdin) PCM_DIN set-up time to PCM_CLK falling 70 Hold time from PCM_CLK t(hauxdin) PCM_DIN high Delay time from PCM_CLK PCM_DOUT t(pauxdout) valid 3.3.7 SPI Signal Function Remarks SPI_CLK_BLSP2 Clock signal Max. 50MHz Copyright © Neoway Technology Co., Ltd...

  • Page 50: Figure 3-33 Spi Connection

    Note the SPI signal direction.  If the levels of slave SPI device and N720 OpenLinux do not match, add a level shifting circuit.  Refer to Figure 3-20 if the SPI speed does not exceed 20 MHz. Select other high-speed level shifting chipsets if the speed exceeds 20 MHz.

  • Page 51: I2C

    Its feature parameters and connection are shown in the following table and figure. Table 3-10 I2C feature parameters IO Level (V) Mode Max. Speed Standard-mode 100 kbit/s 1.8V (VDD) Fast-mode 400 kbit/s Fast-mode Plus 1 Mbit/s Copyright © Neoway Technology Co., Ltd...

  • Page 52: Figure 3-35 I2Cconnection

    I2C_SDA DATA Schematic Design Recommendations If the levels of I2C slave device and N720 OpenLinux do not match, add a level shifting circuit.  Refer to Figure 3-20. Some pins can be multiplexed for I2C function. Connect external pull-up resistors to these pins ...

  • Page 53: Figure 3-37 I2C Timing

    Rise time for SCL and SDA 1000 Fall time for SCL and SDA Set-up time for STOP condition SU;STO Bus free time between STOP and START condition Data invalid time 3.45 VD;DAT Data invalid acknowledge time 3.45 VD;ACK Copyright © Neoway Technology Co., Ltd...

  • Page 54: Table 3-12 I2C Timing Parameters (Fast Mode)

    HIGH Set-up time for a repeated START 0.26 SU;STA condition Data set-up time SU;DAT Rise time for SCL and SDA Fall time for SCL and SDA 6.55 Set-up time for STOP condition 0.26 SU;STO Copyright © Neoway Technology Co., Ltd...

  • Page 55: Network And Connection

    Data invalid time 0.45 VD;DAT Data invalid acknowledge time 0.45 VD;ACK 3.4 Network and Connection N720 OpenLinux supports Ethernet, Bluetooth, WLAN, and other network connections. 3.4.1 Ethernet SGMII Signal Function Remarks SGMII_TX_N SGMII transmit minus Leave this pin floating if it is not used.
  • Page 56 ETH_INT_N Ethernet PHY chipset interrupt MDIO and PHY chipset signals share the same pins with USIM2. The hardware does not support both functions simultaneously. Figure 3-39 shows the connection between MDIO and PHY chipset. Copyright © Neoway Technology Co., Ltd...

  • Page 57: Figure 3-39 Connection Between Mdio And Phy

    1.8V/2.85V auto-adaption. Figure 3-40 and Figure 3-41 show MDIO input/output timing. Figure 3-40 MDIO input timing (MIN) MDIO_CLK (MAX) (MIN) MDIO_DATA (MAX) 10ns MIN 10ns MIN Figure 3-41 MDIO output timing (MIN) MDIO_CLK (MAX) (MIN) MDIO_DATA (MAX) 0ns MIN 300ns MAX Copyright © Neoway Technology Co., Ltd...

  • Page 58: Wlan

    Clock frequency: 32.768 KHz Table 3-14 SDIO/WLAN feature parameters Mode IO Level (V) Max Clock Frequency (MHz) Timing Mode DS, HS, SDR12, SDR25, SDR50, SDR104 DDR50 WLAN uses SDIO 3.0 interface. Figure 3-42 shows the WLAN connection. Copyright © Neoway Technology Co., Ltd...

  • Page 59: Figure 3-42 Wlan Connection

    Leave this pin floating if the WLAN chipset does not support this function. PCB Design Guidelines SDIO interface requires control of trace length. For details about the requirements, refer to the  WLAN chipset spec. Copyright © Neoway Technology Co., Ltd...

  • Page 60: Figure 3-43 Sdio Sdr Timing

    Data valid time Delay time from data write to t(pddwr) -1.45 0.85 transmit Delay time from command write to t(pdcwr) -1.45 0.85 transmit DDR mode (max. 50MHz) t(chrd) Command hold time t(csurd) Command set-up time 5.53 Copyright © Neoway Technology Co., Ltd...

  • Page 61: Bluetooth

    N720 OpenLinux communicates with Bluetooth chipset through UART for data transmission. To use Bluetooth audio, connect one set of PCM signals (pins 65 to 68). See section 3.7 MUX Interfaces. Figure 3-45 shows the Bluetooth connection.

  • Page 62: Rf Interface

    The Bluetooth audio function is implemented through a PCM interface. If the PCM interface is  used, leave I2S_MCLK floating. PCB Design Guidelines Refer to the PCB design guidelines of UART and PCM.  3.5 RF Interface Signal Function Remarks ANT_MAIN AI/O 2G/3G/4G main antenna 50Ω impedance Copyright © Neoway Technology Co., Ltd...

  • Page 63: Ant_Main/Ant_Div Antenna Interface

    Diversity antenna 3.5.1 ANT_MAIN/ANT_DIV antenna interface MAIN_ANT and DIV_ANT of N720 OpenLinux require a characteristic impedance of 50 Ω. Developers should control the impedance of the traces between the pins and antenna to ensure the RF performance. An impedance matching circuit, such as L network, T network, or pi network is mandatory in between.

  • Page 64: Figure 3-48 Pi Network

    Lay copper foil around RF connector. Dig as many ground holes as possible on the copper to  ensure lowest grounding impedance. The trace between N720 OpenLinux and the antenna connector, should be as short as possible.  Control the trace impedance to 50Ω.

  • Page 65: Ant_Gnss Interface

    Figure 3-50 Recommended RF PCB design 2 3.5.2 ANT_GNSS Interface GPS Impedance Control ANT_GNSS (92) is the GNSS RF interface of N720 OpenLinux, which requires a characteristic impedance of 50Ω. Figure 3-51 shows the GNSS structure inside the module. Figure 3-51 GNSS RF structure...

  • Page 66: Figure 3-52 Reference Design Of Passive Gnss Antenna

    Reference design of active GNSS antenna After the antenna receives GNSS satellite signals, the LNA amplifies the signals first and then transmits them to the ANT_GNSS pin of N720 OpenLinux through feeder and PCB traces. See Figure 3-53. Copyright © Neoway Technology Co., Ltd...

  • Page 67: Figure 3-53 Reference Design Of Active Gnss Antenna

    Keep GNSS antenna circuit far away from the main/diversity antenna circuits on PCB.  Otherwise, these two parts will jam each other, lowing the RF performance. Figure 3-54 shows reference layout of GNSS antenna traces. This design is also applicable to Copyright © Neoway Technology Co., Ltd...

  • Page 68: Antenna Assembling

    Inverted F antenna (PIFA). Keep external RF wires far away from all disturbing sources, especially digital signals and DC/DC power if using RF wires. The following methods are commonly used to assemble antenna: GSC RF connector  MM9329-2700RA1 from Murata is recommended. Figure 3-55 shows its encapsulation specifications. Copyright © Neoway Technology Co., Ltd...

  • Page 69: Gpio

    GPIO with interrupt the module is started. N720 OpenLinux provides 4 GPIO pins, two among which support interrupt. Do not connect GPIO_78 or GPIO_79 to the power supply through a pull-up resistor before the module is started. Otherwise, the module will enter download mode forcibly once detecting high level or current input at this pin during startup.

  • Page 70: Mux Interfaces

    GPIO_31 USIM1_CLK GPIO_32 USIM1_RESET GPIO_33 USIM1_DET GPIO_34 Do not pull up these pins to high level before the module is started completely. otherwise, the module cannot start up successfully. GP_CLK indicates clock pulse signal. Copyright © Neoway Technology Co., Ltd...
  • Page 71 WAKE_ON_WIRELES GPIO_59 WLAN_EN GPIO_38 GPIO_79 GPIO_79 I2S_2_WS BT_PCM_SYNC GPIO_78 GPIO_78 I2S_2_SCLK BT_PCM_CLK GPIO_77 GPIO_77 I2S_2_D1 BT_PCM_DOUT Pull up this pin to high level before the module is started, and the module enter USB_BOOT mode. Copyright © Neoway Technology Co., Ltd...
  • Page 72 SDC_DET GPIO_26 46 pins of N720 OpenLinux allow multiplexing and all of them can be used as GPIO. Please use their default functions if you do not have any special requirements in your application. Copyright © Neoway Technology Co., Ltd...

  • Page 73: Other Interfaces

    Once a voice call is incoming, the UART port outputs "RING" character strings and meanwhile the RING pin outputs negative pulse with a width of 30 ms and a period of 5 seconds. Figure 3-57 Pulse wave for an incoming call 30 ms 30 ms Copyright © Neoway Technology Co., Ltd...

  • Page 74: Dtr

    2: Allow to enter sleep mode Enter sleep mode at high level Exits from sleep mode at low level Pull SLEEP low Whether the module Processing current is in idle state services Enter sleep mode and disable all interfaces Copyright © Neoway Technology Co., Ltd...

  • Page 75: Figure 3-60 Incoming Call Service Process

    MCU pulls SLEEP pin MCU pulls SLEEP pin to Figure 3-62 Process of exiting from sleep mode Sleep mode MCU pulls SLEEP high UART enabled AT+ENPWRSAVE=0 Forbid sleep mode Exits from sleep mode Copyright © Neoway Technology Co., Ltd...

  • Page 76: Usb_Boot

    Reserve this pin to facilitate software upgrade and debugging. Figure 3-63 shows the reference design of this pin. Figure 3-63 Reference design of USB_BOOT DVDD_1P8 USB_BOOT 10kΩ 10kΩ ESD1 ESD2 Add an ESD component to protect USB_BOOT in circuit. Copyright © Neoway Technology Co., Ltd...

  • Page 77: Electric Feature And Reliability

    N720 OpenLinux Hardware User Guide 4 Electric Feature and Reliability This chapter describes the electric features and reliability of N720 OpenLinux, including current and voltage of each power pin, operating and storage temperature ranges, and ESD protection features. 4.1 Electric Features...

  • Page 78: Esd Protection

    Table 4-3 ESD protection features Testing Point Contact Discharge Air Discharge VBAT ± 8kV ± 15kV ± 8kV ± 15kV ± 8kV ± 15kV Cover ± 8kV ± 15kV Others ± 2kV ± 4kV Copyright © Neoway Technology Co., Ltd...

  • Page 79: Rf Features

    N720 OpenLinux Hardware User Guide 5 RF Features N720 OpenLinux supports 2G/3G/4G network modes and frequency bands as well as GNSS function.This chapter describes the RF features of N720 OpenLinux. 5.1 Operating Bands Table 5-1 Operating Bands Operating Bands Uplink...

  • Page 80: Tx Power And Rx Sensitivity

    TD-SCDMA B34 24 dBm+1/-3 dBm <-49 dBm TD-SCDMA B39 24 dBm+1/-3 dBm <-49 dBm FDD-LTE B1 23 dBm+2/-2 dBm <-40 dBm FDD-LTE B2 23 dBm+2/-2 dBm <-40 dBm FDD-LTE B3 23 dBm+2/-2 dBm <-40 dBm Copyright © Neoway Technology Co., Ltd...

  • Page 81: Table 5-3 Rf Rx Sensitivity

    <-108 dBm WCDMA B2 <-107 dBm WCDMA B4 <-108 dBm WCDMA B5 <-108 dBm WCDMA B8 <-108 dBm TD-SCDMA B34 <-109 dBm TD-SCDMA B39 <-109 dBm FDD-LTE B1 <-97 dBm FDD-LTE B2 <-95 dBm Copyright © Neoway Technology Co., Ltd...

  • Page 82: Gnss Feature

    -160 dBm (GPS)/-159.5 dBm (GLONASS)/TBD (BDS) Acquisition sensitivity -144 dBm (GPS)/-143.5 dBm (GLONASS) Positioning precision (in air) < 3 m (CEP50) Hot start (in air) <2.5s Cold start (in air) <35s Update frequency 1Hz by default Copyright © Neoway Technology Co., Ltd...
  • Page 83 Tracking sensitivity, acquisition sensitivity, and re-acquisition sensitivity were obtained in signaling test on SPIRENT6300 and they are the maximum values of multiple tests on samples. No external LNA or active antenna was used in the test. Copyright © Neoway Technology Co., Ltd...

  • Page 84: Mechanical Features

    N720 OpenLinux Hardware User Guide 6 Mechanical Features This chapter describes the mechanical features of N720 OpenLinux. 6.1 Dimensions Figure 6-1 N720 dimensions The unit is mm. Copyright © Neoway Technology Co., Ltd...

  • Page 85: Label

    The material and surface finishing must comply with RoHS directives.  6.3 Pack N720 OpenLinux modules are packaged in sealed vacuum bags with dryer, humidity card, and tray on delivery to guarantee a long shelf life. Follow the same package method again in case of opened for any reasons.

  • Page 86: Tray

    N720 OpenLinux Hardware User Guide 6.3.1 Tray Figure 6-3 N720 OpenLinux packing with vacuum bag and tray Figure 6-4 Packaging process Copyright © Neoway Technology Co., Ltd...

  • Page 87: Moisture

    Hardware User Guide 6.3.2 Moisture N720 OpenLinux is a level 3 moisture-sensitive electronic elements, in compliance with IPC/JEDEC J- STD-020 standard. If the module is exposed to air for more than 48 hours at conditions not worse than 30° C/60% RH, bake it at a temperature higher than 90 degree for more than 12 hours before SMT.Or, if the indication...

  • Page 88: Mounting N720 Onto The Application Board

    Hardware User Guide 7 Mounting N720 onto the Application Board N720 OpenLinux is introduced in 100-pin LGA package. This chapter describes N720V5 foot print, recommended PCB design and SMT information to guide users how to mount the module onto application PCB board.

  • Page 89: Application Foot Print

    When using only solder pastes with lead, please ensure that the reflow temperature is kept at  220 ° C for more than 45 seconds and the peak temperature reaches 240 ° C. Copyright © Neoway Technology Co., Ltd...

  • Page 90: Smt Furnace Temperature Curve

    Neoway will not provide warranty for heat-responsive element abnormalities caused by improper temperature control. For information about cautions in N720 OpenLinux storage and mounting, refer to Neoway Module Reflow Manufacturing Recommendations. When manually desoldering the module, use heat guns with great opening, adjust the temperature to 250 degrees (depending on the type of the solder paste), and heat the module till the solder paste is melt.

  • Page 91: Safety Recommendations

     other electronic equipment. Please follow the requirements below in application design: Do not disassemble the module without permission from Neoway. Otherwise, we are entitled to  refuse to provide further warranty. Please design your application correctly by referring to the HW design guide document and our ...

  • Page 92: A Conformity And Compliance

    This product is in compliant with China RoHS directives and does not contain any hazardous substances as per the above referenced standard. Follow the regulations of the countries when storing, applying, and discarding it. Copyright © Neoway Technology Co., Ltd...

  • Page 93: B Abbreviation

    Long-Term Evolution MDIO Management Data Input/Output Printed Circuit Board Pulse-Coded Modulation Power management unit Radio Frequency Secure Digital Controller SGMII Serial Gigabit Media Independent Interface Serial Peripheral Interface TD-SCDMA Time Division-Synchronous Code Division Multiple Access Copyright © Neoway Technology Co., Ltd...
  • Page 94 Universal asynchronous receiver-transmitter USIM Universal Subscriber Identity Module UMTS Universal Mobile Telecommunications System Universal Serial Bus USB-OTG Universal serial bus on-the-go WCDMA Wide-band Code Division Multiple Access Wireless Coexistence Interface WLAN Wireless Local Area Network Copyright © Neoway Technology Co., Ltd...

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