Huawei MC509 Series Hardware Manual page 42

HUAWEI MC509 Series CDMA LGA Module
Hardware Guide
Table 3-10 Signals on the digital audio interface
Pin
No.
5
6
7
8
The MC509 PCM interface enables communication with an external codec to support
linear and μ-law format. The PCM_SYNC runs at 8 kHz with a 50% duty cycle.
Figure 3-20 Circuit diagram of the interface of the PCM (MC509 is used as PCM master)
Primary Mode
On Primary mode MC509 provides a 16-bit linear or μ-law, with short-sync and 2.048
MHz clock (on the PCM_CLOCK pin).
Issue 02 (2013-05-06)
Pin Name I/O
PCM_SYNC O
PCM_DIN I
PCM_DOUT O
PCM_CLK O
Module
(DC E)
PCM_SYNC
PCM_DIN
PCM_DOUT
PCM_CLK
 PCM_SYNC: Output when PCM master
PCM_CLK: Output when PCM master

 It is recommended that a TVS be used on the related interface, to prevent electrostatic
discharge and protect integrated circuit (IC) components.
 Data only edition does not support the voice function.
When the MC509 module works on master mode, PCM_CLK and PCM_SYNC pins are in

the output status.
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Copyright © Huawei Technologies Co., Ltd.
Description of the Application Interfaces
Description
PCM interface sync
PCM I/F data in
PCM I/F data out
PCM interface clock
PCM_SYNC
PCM_DOUT
PCM_DIN
PCM_CLK
DC Characteristics (V)
Min. Typ.
–0.3
2.6
–0.3
2.6
–0.3
2.6
–0.3
2.6
CODEC
Max.
2.9
2.9
2.9
2.9
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