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Phytec phyCORE-MPC5200B Hardware Manual

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phyCORE-MPC5200B
FPGA
Hardware Manual
Edition February 2006
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-MPC5200B

  • Page 1 FPGA Hardware Manual Edition February 2006 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.
  • Page 3 Contents Preface......................1 Introduction..................3 1.1 Block Diagram ................6 1.2 View of the phyCORE-MPC5200B..........7 1.3 Minimum Requirements to Operate the phyCORE-MPC5200B..............9 Pin Description .................. 11 Jumpers....................23 Power Requirements................. 27 4.1 Voltage Supervision and Reset ..........29 System Start-Up Configuration ............
  • Page 4 10.3.9 BDM Port X2..............77 10.3.10 Technical Specification of the Carrier Board ....78 10.3.11 Release Notes..............80 Technical Specifications of the phyCORE-MPC5200B ....81 Hints for Handling the Module ............85 Design Considerations - Check List ..........86 Revision History................87 Component Placement Diagram .............
  • Page 5 Contents Index of Figures Figure 1: Block Diagram phyCORE-MPC5200B ........6 Figure 2: View of the phyCORE-MPC5200B Revision 1238.0 ....8 Figure 3: Pinout of the phyCORE-MPC5200B (Bottom View) ..... 12 Figure 4: Numbering of the Jumper Pads..........23 Figure 5: Location of the Jumpers (Controller Side) (phyCORE-MPC5200B Standard Version) ......
  • Page 6 Transceiver on the Carrier Board with Galvanic Separation... 66 Table 17: Signal Pin Assignment for the phyCORE-MPC5200B / Carrier Board / Expansion Board..........74 Table 18: Pin Assignment Power Supply for the phyCORE-MPC5200B / Carrier Board / Expansion Board ..75 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 7 Contents Table 19: Pin Assignment of the BDM Pin Header X2 ......77 Table 20: Technical Data of the Carrier Board PCM-980 ....... 79 Table 21: Technical Data of the phyCORE-MPC5200B ......82 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 8 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 9 (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product’s pin header rows are longer than 3 m. © PHYTEC Messtechnik GmbH 2006...
  • Page 10 The phyCORE-MPC5200B is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...
  • Page 11 The phyCORE-MPC5200B is a subminiature (77 x 84 mm) insert- ready Single Board Computer populated with Freescale's PowerPC MPC5200 microcontroller. Its universal design enables its insertion in a wide range of embedded applications.
  • Page 12 MPC5200 controller. No description of compatible microcontroller derivative functions is included, as such functions are not relevant for the basic functioning of the phyCORE-MPC5200B. The phyCORE-MPC5200B offers the following features: • Single Board Computer...
  • Page 13 • one 10/100 Mbit/s Ethernet port via optional Micrel PHY • I C Real-Time Clock with calendar and alarm function • industrial temperature range (-40…+85°C) Please contact PHYTEC for more information about additional module configurations. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 14 Timer Outputs (PWM) ATA_CS /CS Signals for ATA Interface COP/JTAG COP/JTAG Debug / Test Port +1V2 Power +1V5 Supply VBAT +3V for RTC and SRAM +2V5 +3V3 Power +3V3@2,2A Figure 1: Block Diagram phyCORE-MPC5200B © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 15 Introduction 1.2 View of the phyCORE-MPC5200B NAND-Flash Flash Alterra Cyclone 2 Flash SRAM MPC5200B © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 16 FPGA Figure 2: View of the phyCORE-MPC5200B Revision 1238.0 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 17 GND pins neighboring the +3V3 pins. In addition, proper implementation of the phyCORE module into a target application also requires connecting all GND pins neighboring signals that are being used in the application circuitry.
  • Page 18 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 19 Many of the phyCORE-MPC5200B pins offer alternative functions. These alternative functions must be activated by configuring the applicable controller registers prior to their use. Certain controller functions are pre-configured based on the module’s design and are...
  • Page 20 As Figure 3 indicates, all controller signals extend to surface mount technology (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector; refer to section 11). This allows the phyCORE-MPC5200B to be plugged into any target application like a "big chip". Figure 3:...
  • Page 21 Please refer to J19 for this signal. FPGA_B1_J1 FPGA_B1_K2 Already used if NAND Flash is populated. Already used if NAND Flash is populated. FPGA_B1_K1 FL_VPEN Flash U13/U14 is write protected if this pin is driven low. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 22 Interrupt input 1 of the processor.. /IRQ2 Interrupt input 2 of the processor. 4B, 9B, 14B, Ground 0 V 19B, 24B, 29B, 34B, 39B, 44B, 49B, 54B, 59B, 64B, 69B, 74B, 79B, 84B, 89B, 94B, 99B © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 23 Already used if NAND Flash is populated. FPGA_B1_P1 Already used if NAND Flash is populated. FPGA_B1_P2 Already used if NAND Flash is populated. FPGA_B1_L4 Already used if NAND Flash is populated. FPGA_B1_M4 Already used if NAND Flash is populated. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 24 62C, 67C, 72C, 77C, 82C, 87C, 92C,97C VBAT Connection for external battery (+) 2.4-3.3 V to supply (back-up) the RTC and the SRAM. /WDO Watchdog output (U26) GPIO_WKUP_6 I/O Dedicated GPIO with wakeup capability © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 25 TxD output on the RS-232 transceiver for the MPC UART (PSC6). /UART6_RTS_TTL PSC6 request to send signal /UART6_CTS_TTL PCS6 clear to send signal Second I²C Interface I2C2_CLK Clock (SCL) I2C2_IO Data (SDA) I2C1_CLK Clock (SCL) signal of first I²C interface © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 26 Already used if NAND Flash is populated FPGA_B4_K7 I/O voltage is 3.3 V only. FPGA_B4_K6 I/O voltage is 3.3 V only. FPGA_B4_P6 I/O voltage is 3.3 V only. FPGA_B4_N6 I/O voltage is 3.3 V only. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 27 RxD input on the RS-232 transceiver for the MPC UART3 (PSC3). TXD3-232 TxD output on the RS-232 transceiver for the MPC UART3 (PSC3). /UART3_RTS_TTL PSC3 request to send signal /UART3_CTS_TTL PCS3 clear to send signal © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 28 If the FPGA is not populated, all pins are NC. FPGA_B1_D2 Already used if NAND Flash is populated. FPGA_B1_D1 Already used if NAND Flash is populated. FPGA_B1_J6 Already used if NAND Flash is populated. FPGA_B1_H6 Already used if NAND Flash is populated. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 29 Not connected on PCB revision 0. 73D, 75D, 76D, 77D, 78D, 80D, 81D, 82D, 83D, 85D, 86D, 87D, 88D, 90D, 91D, 92D, 93D, 95D, 96D, 97D, 98D, 100D Table 2: Pinout of the phyCORE-Connector X3 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 30 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 31 Jumpers 3 Jumpers For configuration purposes, the phyCORE-MPC5200B has 19 solder jumpers, some of which have been installed prior to delivery. Figure 4 illustrates the numbering of the jumper pads, while Figure 5 indicates the location of the jumpers on the SBC module.
  • Page 32 The UART receive signals UART3_RXD_TTL and UART6_RXD_TTL are disconnected from the RS-232 transceiver. closed The UART receive signals UART3_RXD_TTL and UART6_RXD_TTL are connected to the RS-232 transceiver. Package Type 0R in SMD 0805 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 33 These two jumpers can be used to connect the signals FPGA_B1_C2 and FPGA_B1_J2. 1 + 2 FPGA_B1_C2 and FPGA_B1_J2 are connected 2 + 3 FPGA_B1_C2 routed to X3A43 and FPGA_B1_J2 to X3A56 (fixed 3.3V voltage level) Package Type 0R in SMD 0805 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 34 7 enables the activation of a write protect function. It is not guaranteed that the standard serial memory populating the phyCORE-MPC5200B will have this write protection function. Please refer to the corresponding memory data sheet for more detailed information.
  • Page 35 Power Requirements 4 Power Requirements The phyCORE-MPC5200B must be supplied with a single main supply voltage: Supply voltage: +3.3 V ±10 % with 2.2A load Caution: Connect all +3V3 input pins to your power supply and at least the matching number of GND pins neighboring the +3V3 pins.
  • Page 36 Internally generated voltages: 1V2, 1V5, 2V5 Supply voltage summary: • 3V3 PowerPC I/O, Flash memory (external) • 2V5 DDR SDRAM, Ethernet PHY and VIDEO RAM • 1V5 PowerPC core • 1V2 Cyclone II FPGA core © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 37 The voltage supervisor offers 4 non-delayed comparator outputs which are combined to a global /Power_Good output signal. This signal is available at connector pin X3D7 and not used on-board. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 38 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 39 The following default configuration is read by the processor with the rising edge of reset line /PoReset. The logic level of the signals written in italic style can be configured via on-board solder jumpers. Refer to section 3, "Jumpers" for more details. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 40 ROM bus, with address and data tenures, ALE and TS active. 1 ETH_TXD0 large_flash_sel 0 bit=0: No boot in large Flash mode 1 bit=1: Boot in large Flash mode 1 ,3, 4 Table 4: System Start-up Configuration © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 41 FPGA. This NAND-Flash can be used as a mass storage device via the "CF IP Core". The SRAM (U5, 16-bit) is connected to the PowerPC LocalPlus Bus and is controlled by /CS2. The SRAM can be battery buffered with the © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 42 Communication to the small non-volatile memory device (EEPROM) at U6 is established over the processor's I C1 bus. This memory device contains the boot loader (U-Boot) environment parameters in the first two kilobytes and can also be used for parameter storage. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 43 Select signal is the dedicated control signal for boot purposes. The LocalPlus Bus can be configured to function in different bus modes. For the phyCORE-MPC5200B the 25-bit address / 32-bit data multiplexed mode was chosen because it offers the largest address space without interfering with the ATA or PCI bus.
  • Page 44 – 8.5 ns PCICK To support all memory speed grades up to 120 ns at least 7 wait states must be added for /CS0. • 7 wait states for /CS0 (supports 66 MHz PCI clock) © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 45 No additional voltages are needed for in-system programming. As of the printing of this manual, Flash devices generally guarantee at least 100,000 erase/programming cycles. Refer to the applicable INTEL data sheet for detailed description of the erasing and programming procedure. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 46 FPGA DDR SDRAM The phyCORE-MPC5200B is equipped with fast Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) devices. This memory is connected to a dedicated SDRAM interface provided by the MPC5200B processor. The DDR SDRAM memory bank consist of two 16-bit data port devices connected in parallel to support the 32-bit bus width of the processor.
  • Page 47 – 8.5 ns PCICK To support all memory speed grades up to 70 ns at least 4 wait states must be added for /CS2. • 4 wait states for /CS2 (supports 66 MHz PCI clock) © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 48 FPGA 6.4 Serial Memory The phyCORE-MPC5200B features a non-volatile memory device (EEPROM) with a serial I C interface. This memory can be used for storage of configuration data or operating parameters that must be maintained in the event of a power interruption. The available capacity is 4 kByte.
  • Page 49 This should be noted when configuring the I bus slave address. 6.5 NAND-Flash (U28) Will be described in conjunction with the IP cores 6.6 Video-RAM (U20) Will be described in conjunction with the IP cores © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 50 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 51 U22 via the FPGA JTAG interface. The FPGA is a member of the Altera Cyclone II family provided by Altera Corp. (http://www.altera.com/). • Altera Cyclone II EP2C8 Device Features: Under construction! © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 52 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 53 8.1 RS-232 Interface dual-channel RS-232 transceiver located phyCORE-MPC5200B at U3. This device adjusts the signal levels of the UART3_RXD/TXD_TTL and UART6_RXD/TXD_TTL lines (MPC5200B PSC3/PSC6). RS-232 interface enables connection of the module to a COM port on a host-PC or other peripheral devices. In this instance, the RXD3-232 or RXD6-232 line (X2D22/X2C21) of the transceiver is connected to the corresponding TXD line of the COM port;...
  • Page 54 FPGA 8.2 CAN Interface transceivers (SN65HV230) populate phyCORE-MPC5200B module at U4 / U5. The on-board transceivers enable transmission reception signals CAN1TX / CAN1RX CAN2TX / CAN2RX. transceivers support transmission speeds of up to 1 MBit/s and connection of up to 110 nodes on a single CAN network. Data transmission occurs with differential signals between CANH and CANL.
  • Page 55 Such COP signal converters enable connection of the MPC5200B to a host-PC for debugging purposes. This COP converter is NOT located on the phyCORE-MPC5200B module. The COP signals are available at the pin header connector X1 located at the front edge of the phyCORE module (refer to Figure 8).
  • Page 56 PCB as shown in Figure 8 while the even pin numbers are located on the top. Pin header X1 is not installed on the standard version of the phyCORE-MPC5200B module. In addition, the COP signals are routed to pins on the Molex connectors (refer to Table 10).
  • Page 57 Serial Interfaces 8.4 Ethernet Interface Connection of the phyCORE-MPC5200B to the world wide web or a local network is possible over the integrated FEC (Fast Ethernet Controller) of the Freescale processor. The FEC operates with a data transmission speed of 10 or 100 Mbit/s.
  • Page 58 IP number to the hardware's MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE-MPC5200B is located on the bar code sticker attached to the module.
  • Page 59 Carrier Board phyCORE-MPC5200B (part number PCM-980), a USB transceiver is already integrated on the board (refer to section 10). This transceiver is connected to USB port 1. For additional information of the USB 1.1 controller refer to the MPC5200B Reference Manual as well as the USB 1.1 bus...
  • Page 60 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 61 • Automatic word address incrementing • Programmable alarm, timer and interrupt functions If the phyCORE-MPC5200B is supplied with a battery at VBAT, the Real-Time Clock runs independently of the board's power supply. The Real-Time Clock is programmed via the I C bus (address 0xA2 / 0xA3).
  • Page 62 For more information on the features of the RTC-8564, refer to the corresponding Data Sheet. Note: After connection of the supply voltage, or after a reset, the Real-Time Clock generates no interrupt. The RTC must first be initialized (see RTC Data Sheet for more information). © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 63 The phyCORE-MPC5200B FPGA on the Carrier Board 10 phyCORE Carrier Board PCM-980 PHYTEC Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules. Carrier Boards are...
  • Page 64 TFT LCD ZIF connector Backlight connector LAN port 0 10/100 Mbit/s Ethernet, RJ-45 socket USB1 host socket USB2 host socket dual DB-9 plugs for CAN interface connectivity dual DB-9 sockets for RS-232 interface connectivity © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 65 The phyCORE-MPC5200B FPGA on the Carrier Board GND1 GND connector (for connection of GND signal of measuring devices such as an oscilloscope) Reset (/PoReset) push button green power LED, indicates +5 V green power LED, indicates +3V3 green power LED, indicates 3.3 V PCI supply...
  • Page 66 FPGA Figure 9: View of the Carrier Board PCM-980 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 67 The Carrier Board's peripheral components are configured for use with the phyCORE-MPC5200B by means of removable jumpers. If no jumpers are set, no signals are connected to the CAN transceivers. The reset input on the phyCORE-MPC5200B directly connects to the Reset button (S2).
  • Page 68 Figure 11 shows the factory default jumper settings for operation of phyCORE Carrier Board PCM-980 with standard phyCORE-MPC5200B. Jumper settings other functional configurations of the phyCORE-MPC5200B module mounted on the Carrier Board are described in section 10.3. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 69 Functional Components on the phyCORE Carrier Board PCM-980 This section describes the functional components of the phyCORE Carrier Board PCM-980 supported by the phyCORE-MPC5200B and appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-MPC5200B module, alternative jumper settings can be used.
  • Page 70 Socket P2B is the top socket of the double DB-9 connector at P2. Pin 2 TXD1 Pin 3 RXD1 Pin 5 GND Figure 14: Pin Assignment of the DB-9 Socket P2B as Second RS-232 (Front View) © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 71 Depending on the configuration of the CAN transceivers and their power supply, the following two configurations are possible: 1. CAN transceiver on the phyCORE-MPC5200B is populated and the CAN signals from the module extend directly to plug P1A. Jumper...
  • Page 72 Figure 16: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on Carrier Board with Galvanic Separation) Please make sure the CAN transceiver on the phyCORE-MPC5200B is not populated and Jumper J21 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2006...
  • Page 73 The phyCORE-MPC5200B FPGA on the Carrier Board 10.3.5 Second CAN Interface at Plug P1B Plug P1B is the top plug of the double DB-9 connector at P1. P1B is connected to the second CAN interface (CAN_1) of the phyCORE-MPC5200B via jumpers. Depending on the configuration...
  • Page 74 Figure 18: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Carrier Board with Galvanic Separation) Please make sure the CAN transceiver on the phyCORE-MPC5200B is not populated and Jumper J21 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2006...
  • Page 75 The phyCORE Carrier Board PCM-980 offers a programmable LED at D29 for user implementations. This LED is connected to port pin XPLD1_0 of the phyCORE-MPC5200B. A low-level at port pin XPLD1_0 causes the LED to illuminate, LED D29 remains off when writing a high-level to XPLD1_0.
  • Page 76 Figure 19: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 20: Pin Assignment Scheme of the Patch Field © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 77 The phyCORE-MPC5200B FPGA on the Carrier Board The pin assignment on the phyCORE-MPC5200B, in conjunction with the expansion bus (X12) on the Carrier Board and the patch field on an expansion board, is as follows: phyCORE- Carrier Board Expansion Board...
  • Page 78 XPLD3_10 XPLD3_10 BUS18 XPLD3_12 XPLD3_12 BUS20 XPLD3_15 XPLD3_15 CF_VS2 BUS23 XPLD3_17 XPLD3_17 CF_CSEL BUS25 XPLD3_18 XPLD3_18 CF_CS1 BUS26 XPLD3_20 XPLD3_20 BUS28 XPLD3_23 XPLD3_23 BUS31 XPLD3_25 XPLD3_25 BUS33 XPLD3_26 XPLD3_26 BUS34 XPLD3_28 XPLD3_28 CF_IOWR BUS36 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 79 The phyCORE-MPC5200B FPGA on the Carrier Board phyCORE- Carrier Board Expansion Board MPC5200B PCM-980 PCM-988 Expansion Bus Patch Field Alt. Pin Signal Pin Signal Function Signal XPLD3_31 XPLD3_31 CF_RESET 36A BUS39 XPLD3_33 XPLD3_33 CF_PDIAG 36B BUS41 XPLD3_34 XPLD3_34 CF_SPKR BUS42...
  • Page 80 GPIO55 XPLD1_5 XPLD1_5 GPIO58 XPLD1_7 XPLD1_7 GPIO60 XPLD1_8 XPLD1_8 GPIO61 XPLD1_10 XPLD1_10 GPIO63 XPLD0_34 XPLD0_34 GPIO66 XPLD0_32 XPLD0_32 GPIO68 XPLD0_31 XPLD0_31 GPIO69 XPLD0_29 XPLD0_29 GPIO71 XPLD0_26 XPLD0_26 GPIO74 XPLD0_24 XPLD0_24 GPIO76 XPLD0_22 XPLD0_22 GPIO77 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 81 The phyCORE-MPC5200B FPGA on the Carrier Board phyCORE- Carrier Board Expansion Board MPC5200B PCM-980 PCM-988 Expansion Bus Patch Field Alt. Pin Signal Pin Signal Function Signal XPLD0_20 XPLD0_20 GPIO79 DSCLK DSCLK GPIO82 GPIO84 GPIO85 PSTDDATA6 PSTDDATA6 GPIO87 PSTDDATA4 PSTDDATA4 GPIO90...
  • Page 82 XPLD_TDI GPIO97 XPLD_TDO XPLD_TDO GPIO99 ADC7 ADC7 GPIO102 ADC5 ADC5 GPIO104 ADC4 ADC4 GPIO105 ADC2 ADC2 GPIO107 REFA REFA GPIO110 Table 17: Signal Pin Assignment for the phyCORE-MPC5200B / Carrier Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 83 59D, 64D, 69D 46D, 47D, 48D, 51D, 52D, 53D, GNDA 77C, 74D, 79D GNDA 77C, 74D, 79D 1E, 2E Table 18: Pin Assignment Power Supply for the phyCORE-MPC5200B / Carrier Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 84 Board PCM-980 is connected to port pin XPLD1_4 of the XPLD. +3V3 DS18B20 XPLD1_4 Figure 21: Connecting the DS18B20 Temperature Sensor with Silicon Serial Number Figure 22: Pin Assignment of the DS2401 Silicon Serial Number © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 85 The phyCORE-MPC5200B FPGA on the Carrier Board 10.3.9 BDM Port X2 The 26-pin header with 2.54 mm pin spacing at X2 is used to connect the processor's BDM debug port to the host-PC's development system (e.g. Metrowerks CodeWarrior) using an appropriate BDM interface unit (e.g.
  • Page 86 FPGA 10.3.10 Technical Specification of the Carrier Board Figure 23 Physical Dimensions of the Carrier Board PCM-980 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 87 The phyCORE-MPC5200B FPGA on the Carrier Board Technical Data: Parameter Requirements Characteristics Dimensions 160 mm x 125 mm Weight With maximum Approximately 190 grams circuitry installed, no PCI connector mounted Humidity Max. 95 % r.F., not condensed Storage Temp. Range -40°...
  • Page 88 • CF-Card socket X8 pin 7 is disconnected from /FB_CS1 and wired to the phyCORE connector X1A6 signal XPLD3_1. • Power Connector X10: Pins 2 and 3 have to short circuit to connect the system ground to the external power supply line. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 89 Technical Specification Technical Specifications of the phyCORE-MPC5200B The physical dimensions of the phyCORE-MPC5200B are represented in Figure 24. PCB 1229.0 PHYTEC Flash ColdFire MCF548x Pin 1 XPLD Flash SDRAM Pin 2 SDRAM Figure 24: Physical Dimensions © PHYTEC Messtechnik GmbH 2006...
  • Page 90 RTC only Reset Delay Time After valid system Approx. 200 ms voltages Table 21: Technical Data of the phyCORE-MPC5200B These specifications describe the standard configuration of the phyCORE-MPC5200B as of the printing of this manual. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 91 Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-MPC5200B. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (3 mm) on the underside of the phyCORE must be subtracted.
  • Page 92 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 93 Alternatively, a hot air gun can be used to heat and loosen the bonds. Integrating the phyCORE-MPC5200B in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module.
  • Page 94 • Data line D0 represents the LSB and D31 the MSB. • Address line A0 represents the LSB and A31 the MSB. • Byte ordering is Big Endian. • Never connect signals to the MPC5200 output drivers carrying a higher potential (e.g.
  • Page 95 Revision History 14 Revision History Date Version numbers Changes in this manual 1/21/05 Manual L-645e_1 First release version. PCM-024 PCB# 1229.0 PCM-980 PCB# 4132.0 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 96 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 97 Component Placement Diagram 15 Component Placement Diagram Figure 25: phyCORE-MPC5200B Component Placement, Top View © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 98 FPGA Figure 26: phyCORE-MPC5200B Component Placement, Bottom View © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 99 • ADC converter is not present on 1229.0. Footprint is not compatible to the device. • Bootstrapping problems for the PHY 1 (U18) device. Reset input must be connected to /RSTI instead of /RSTO. © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 100 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 101 First CAN Interface....63 CAN Transceiver ...... 46 First Serial Interface....62 CAN_0 ........63 Flash ........5, 33 CAN_1 ........65 Flash Access Time ....36 CAN_H ........46 Flash Memory ......35 CAN_L........46 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 102 RTC_CLKOUT ......54 MAC ......... 50 MAC Address ......50 S1 ..........57 Mating Connector ..... 83 SDRAM ........38 MAX6364......... 27 Bus Width ......38 MICREL ........49 Capacity ......... 38 Molex........83 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 103 X23..........56 U28..........33 X3..........56 U3..........45 X4..........56 U4..........46 X5..........56 U5........33, 46 X6..........56 U6........34, 40 X7..........56 U7........27, 40, 53 X8..........56 UART........45 X9..........56 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 104 FPGA © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 105 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Messtechnik GmbH 2006 L-672e_0...
  • Page 106 Published by © PHYTEC Messtechnik GmbH 2006 Ordering No. L-672e_0 Printed in Germany...