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Phytec phyCORE-MCF548x Hardware Manual

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phyCORE-MCF548x
Hardware Manual
Edition January 2005
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-MCF548x

  • Page 1 Hardware Manual Edition January 2005 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Contents Preface ......................1 Introduction ..................3 1.1 Block Diagram................6 1.2 View of the phyCORE-MCF548x..........7 1.3 Minimum Requirements to Operate the phyCORE-MCF548x..8 Pin Description ..................9 Jumpers ....................23 Power Requirements .................33 4.1 Voltage Supervision and Reset...........35 System Start-Up Configuration ............37 System Memory .................39 6.1 Flash Memory................40...
  • Page 4 10.3.9 BDM Port X2 ..............79 10.3.10 Technical Specification of the Development Board ..80 10.3.11 Release Notes ..............82 Technical Specifications of the phyCORE-MCF548x ....83 Hints for Handling the Module............86 Design Considerations - Check List ..........87 Revision History ................
  • Page 5 Block Diagram phyCORE-MCF548x ........6 Figure 2: View of the phyCORE-MCF548x Revision 1229.0 (M 1.5:1) ..................7 Figure 3: Pinout of the phyCORE-MCF548x (Bottom View) ....9 Figure 4: Numbering of the Jumper Pads..........23 Figure 5: Location of the Jumpers (Controller Side)and Default Settings (phyCORE-MCF548x Standard Version) ....23...
  • Page 6 Figure 25 Physical Dimensions of the Development Board PCM-982................80 Figure 26: Physical Dimensions.............. 83 Figure 27: phyCORE-MCF548x Component Placement, Top View ..89 Figure 28: phyCORE-MCF548x Component Placement, Bottom View................89 Index of Tables Table 1: Pinout of the phyCORE-Connector X2 ......... 21 Table 2: Jumper Settings ..............
  • Page 7 Table 18: Signal Pin Assignment for the phyCORE-MCF548x / Development Board / Expansion Board........76 Table 19: Pin Assignment Power Supply for the phyCORE-MCF548x / Development Board / Expansion Board........77 Table 20: Pin Assignment of the BDM Pin Header X2 ......79 Table 21: Technical Data of the Development Board PCM-982 .....81...
  • Page 8 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 9: Preface

    (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product’s pin header rows are longer than 3 m. © PHYTEC Messtechnik GmbH 2005...
  • Page 10 The phyCORE-MCF548x is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...

  • Page 11: Introduction

    The phyCORE-MCF548x is a subminiature (70 x 57 mm) insert-ready Single Board Computer populated with Freescale’s ColdFire MCF548X microcontroller. Its universal design enables its insertion in a wide range of embedded applications.
  • Page 12 MCF548X controller. No description of compatible microcontroller derivative functions is included, as such functions are not relevant for the basic functioning of the phyCORE-MCF548x. The phyCORE-MCF548x offers the following features: • Single Board Computer...
  • Page 13 • 12-bit ADC, 8 channels, connected to I C Bus • 12-bit DAC, 1 channel, connected to I C Bus • JTAG/BDM test/debug port • Industrial temperature range (-40…+85°C) Please contact PHYTEC for more information about additional module configurations. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 14: Block Diagram

    12-Bit 12-Bit ADC, 8 channel 8 channels C Bus 12-Bit 12-Bit DAC, 1 channel 1 channel C Bus +1V5 Power +2V5 Supply VBat +3V for RTC +3V3 Power +3V3@1A Figure 1: Block Diagram phyCORE-MCF548x © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 15: View Of The Phycore-Mcf548X

    Introduction 1.2 View of the phyCORE-MCF548x PCB 1229.0 Flash PHYTEC ColdFire MCF548x Pin 1 XPLD Flash SDRAM Pin 2 SDRAM Figure 2: View of the phyCORE-MCF548x Revision 1229.0 (M 1.5:1) © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 16: Minimum Requirements To Operate The Phycore-Mcf548X

    1.3 Minimum Requirements to Operate the phyCORE-MCF548x Basic operation of the phyCORE-MCF548x only requires supply of a +3V3 input voltage and the corresponding GND connection. These supply pins are located at the phyCORE-connector X2: +3V3 1C, 2C, 1D, 2D, 4D, 5D...

  • Page 17: Pin Description

    As Figure 3 indicates, all controller signals extend to surface mount technology (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector; refer to section 11). This allows the phyCORE-MCF548x to be plugged into any target application like a "big chip". Figure 3:...
  • Page 18 62A, 67A, 72A, /IRQ7 Interrupt input 7 of the ColdFire processor. GPI PIRQ7 Reset state: GPI XPLD3_0 I/O XPLD GPIO /FB_CS1 Chip Select 1 of the ColdFire FlexBus. Reset state: high I/O PFBCS1 GPIO © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 19 DMA acknowledge 1 I/O PDMA3 GPIO Reset state: GPI TOUT1 GP timer output 1 /PCI_RESET PCI reset Reset state: Low /PCI_BR0 PCI bus request 0 I/O PPCIBR0 GPIO Reset state: GPI TIN0 GP timer input 0 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 20 Reset state: tristate /PCI_SERR I/O PCI system error signal Reset state: tristate 70° /PCI_CXBE1 I/O PCI command/byte enable signal 1 Reset state: tristate Refer to Table 3 for additional information to the system’s start-up configuration. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 21 49B, 54B, 59B, 64B, 69B, 74B, /FB_CS2 Chip Select 2 of the ColdFire FlexBus. Reset state: high I/O PFBCS2 GPIO /FB_CS3 Chip Select 3 of the ColdFire FlexBus. Reset state: high I/O PFBCS3 GPIO © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 22 PCI reference clock output supplied from the clock distribution device at U22. Ground 0 V /PCI_BG0 PCI external bus grant signal 0. I/O PPCIBG0 GPIO Reset state: GPI (PAR_PCIBG0) TOUT0 GP timer output 0 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 23 I/O PCI stop signal Reset state: tristate PCI_PAR I/O PCI parity signal Reset state: tristate I/O PCI command/byte enable signal 0 /PCI_CXBE0 Reset state: tristate Refer to Table 3 for additional information to the system’s start-up configuration. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 24 The voltage supervisor adds a reset delay of 200 ms for /RSTI. That means /RSTI will stay active 200 ms after /RESIN is released. /RSTO Reset output signal of the ColdFire processor. Reset state: low Refer to A.1 for additional information. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 25 Reset state: GPI DSPI_CS2 QSPI Chip Select signal 5 I/O PDSPI4 GPIO Reset ctate: GPI TOUT2 GP timer output 2 CANTX1 FlexCAN transmit 1 I/O I C serial clock signal I/O PFECI2C0 GPIO Reset state: GPI © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 26 Analog input of the analog to digital ADC3 converter U13. This device is connected to ADC1 the I C bus with slave address 0x90/0x91. ADC0 For detailed description refer to the ADC7828 Data Sheet provided by Texas Instruments/Burr-Brown. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 27 Reset state: GPI RXD2_TTL PSC2 receive data signal I/O PPSC3PSC021 GPIO Reset state: GPI /CTS2_TTL PCS2 clear to send signal I/O PPSC3PSC23 GPIO Reset state: GPI PSC2BCLK PSC2 modem clock CANRX0 FlexCAN receive input 0 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 28 PCS3BCLK PSC3 modem clock DSPI_CS0 DSPICS0/SS DSPI Chip Select 0 in master mode or slave select in slave mode. I/O PDSPI3 GPIO Reset state: GPI /PSC3RTS PSC3 request to send signal PSC3FSYNC PSC3 frame sync © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 29: Table 1: Pinout Of The Phycore-Connector X2

    The ADC provides an internal 2.5 V reference voltage that can be programmed for output. For detailed description refer to the ADC7828 data sheet provided by Texas Instruments/Burr- Brown. Table 1: Pinout of the phyCORE-Connector X2 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 30 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 31: Jumpers

    Jumpers 3 Jumpers For configuration purposes, the phyCORE-MCF548x has 36 solder jumpers, some of which have been installed prior to delivery. Figure 4 illustrates the numbering of the jumper pads, while Figure 5 and Figure 6 indicate the location of the jumpers on the board.

  • Page 32: Figure 6: Location Of The Jumpers (Connector Side) And Default Settings (Phycore-Mcf548X Standard Version)

    SDRAM Pin 2 SDRAM Figure 6: Location of the Jumpers (Connector Side) and Default Settings (phyCORE-MCF548x Standard Version) © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 33 0R in SMD 0402 open Reference voltage for CAN transceiver at U11 1 + 2 Do not close this jumper. 2 + 3 Do not close this jumper. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 34 0R in SMD 0805 Connection of the WAIT signal for the Flash devices to the processor’s /TA signal. open Disconnects WAIT from /TA signal. closed Connects WAIT to the /TA signal. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 35 7 enables the activation of a write protect function. It is not guaranteed that the standard serial memory populating the phyCORE-MCF548x will have this writing protection function. Please refer to the corresponding memory data sheet for more detailed information.
  • Page 36 CAN bus signals. 1 + 2 Routes CANTX0 signal to pin CAN_H1 at X2C18. 3 + 4 Routes CANRX0 signal to pin CAN_L1 at X2D18. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 37 Do not change this jumper! 1 + 2 Connects ball V4 of the processor to +1V5. 2 + 3 Connects ball V4 of the processor to +3V3. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 38 XPLD0_35 of the XPLD logic device. This feature may be used to establish a wired feedback of a software controlled global clock signal. open XPLD_CLK1 is not connected to XPLD0_35. closed XPLD_CLK1 is connected to XPLD0_35. Package Type 0R in SMD 0402 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 39: Table 2: Jumper Settings

    1 + 2 VCAN is connected to +3V3. 2 + 3 VCAN is connected to VIN5V. Package Type 0R in SMD 0805 Test point for +2V5 voltage. Test point for +1V5 voltage. Table 2: Jumper Settings © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 40 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 41: Power Requirements

    Power Requirements 4 Power Requirements The phyCORE-MCF548x must be supplied with one supply voltage only: Supply voltage: +3.3 V ±10 % with 1A load Caution: Connect all +3V3 input pins to your power supply and at least the matching number of GND pins neighboring the +3V3 pins.

  • Page 42: Figure 7: Power Supply Diagram

    Transceiver Solder Jumper J36 Figure 7: Power Supply Diagram Internally generated voltages: 1V5, 2V5, 3V3 • 1V5 ColdFire Core • 2V5 DDR SDRAM and Ethernet PHY • 3V3 ColdFire I/O, Flash memory and XPLD © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 43: Voltage Supervision And Reset

    To connect external reset sources such as push buttons e.g. use the input port /RESIN. /RESIN is connected to a 10kOhm pull-up resistor. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 44 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 45: System Start-Up Configuration

    TSIZE[1..0] and FB_AD[1..0] FB_AD6 reserved FB_AD7 FB_AD8 CLKCONFIG[4..0] Ratio 1:2 FB_AD9 CLKIN to SDCLK Ratio 50MHz CLKIN FB_AD10 100MHz int. FB_AD11 200MHz Core FB_AD12 Table 3: System Start-up Configuration © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 46: Table 4: System Start-Up Configuration Test/Debug Port

    MTMOD0=1 select JTAG mode MTMOD0=0 selects BDM mode Table 4: System Start-up Configuration Test/Debug Port MTMOD0 should not be changed while /RSTI is inactive (high). Dynamic switching between BDM and JTAG operation is not supported. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 47: System Memory

    Freescale ColdFire processor and operates at the maximum frequency. Communication to the small non-volatile memory device (EPROM, FRAM or SRAM) is established over the processor’s I C bus. This memory device can be used for parameter storage. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 48: Flash Memory

    Flash Memory Use of Flash as non-volatile memory on the phyCORE-MCF548x provides an easily reprogrammable means of code storage. Various Flash devices can be used on the phyCORE-MCF548x: • 32 or 64 MByte Intel Strata Flash memory • 32-bit bus width with two devices in parallel •...
  • Page 49 No additional voltages are needed for in-system programming. As of the printing of this manual, Flash devices generally guarantee at least 100.000 erase/programming cycles. Refer to the applicable INTEL data sheet for detailed description of the erasing and programming procedure. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 50: Ddr Sdram

    DDR SDRAM The phyCORE-MCF548x is equipped with fast "Double Data Rate Synchronous Dynamic Random Access Memory" DDR SDRAM devices. This memory is connected to the dedicated SDRAM interface provided by the MCF548x ColdFire processor. This enables the processor to communicate at full core speed of 200 MHz.

  • Page 51: Serial Memory

    System Memory 6.3 Serial Memory The phyCORE-MCF548x features a non-volatile memory device with a serial I C interface. This memory can be used for storage of configuration data or operating parameters, that must not be lost in the event of a power interruption. Depending on the module’s configuration, this memory can be in the form of an EEPROM, FRAM or SRAM.

  • Page 52: Figure 8: Serial Memory I 2 C Slave Address

    Table 8: Serial Memory I C Address (Examples) Address lines A1 and A2 are not always made available with certain serial memory types. This should be noted when configuring the I bus slave address. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 53: Xpld System Logic Device

    7 XPLD System Logic Device The XPLD logic device U19, supplied by Lattice Semiconductor, is responsible for routing resources on the phyCORE-MCF548x and provides a very flexibly way to connect and operate application- specific hardware components or interfaces in a target design. In...

  • Page 54: Xpld Firmware Development

    7.1 XPLD Firmware Development A basic firmware project with pin and signal assignment is provided by PHYTEC. This project is written in VHLD and can be easily extended with customer-specific functionality. The required development tool is called ispLever and is provided by Lattice Semiconductor.

  • Page 55: Serial Interfaces

    RS-232 transceiver located phyCORE-MCF548x at U12. This device adjusts the signal levels of the TXD0_TTL/RXD0_TTL and TXD1_TTL/RXD1_TTL lines (MCF548X UART). The RS-232 interface enables connection of the module to a COM port on a host-PC or other peripheral devices. In...

  • Page 56: Can Interface

    8.2 CAN Interface transceivers (SN65HV230) populate phyCORE-MCF548x module at U10 / U11. The on-board transceivers enable transmission and reception of CAN signals via CANTX0 / CANRX0 and CANTX1 / CANRX1. The CAN transceivers support transmission speeds of up to 1 MBit/s and connection of up to 110 nodes on a single CAN network.
  • Page 57 Furthermore, the signal rise time can be configured by closing both jumpers at 1+2 (leaving 2+3 open). This results in reduced interference from the CAN bus when using lower baud rates. For additional information refer to the data sheet for the SN65HV230 CAN transceiver. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 58: Bdm Debug Interface

    Such BDM signal converters enable connection of the MCF548X to a host-PC for debugging purposes. This BDM converter is NOT located on the phyCORE-MCF548x module. The BDM signals are available on the pin header connector X1 located at the front edge of the phyCORE module (refer to Figure 10).

  • Page 59: Table 9: 26-Pin Bdm Connector (X1) And Corresponding Pins On The Phycore-Connector (X2)

    PCB is shown in Figure 10. The even pin numbers are located on the bottom of the PCB. Pin header X1 is not installed on the standard version of the phyCORE-MCF548x module. In addition, the BDM signals are routed to pins on the Molex connectors (refer to Table 9).

  • Page 60: Ethernet Interface

    8.4 Ethernet Interface Connection of the phyCORE-MCF548x to the world wide web or a local network is possible over the integrated FEC’s (Fast Ethernet Controller) of the Freescale ColdFire processor. The processor provides up to two FEC’s (MCF5485) depending on the actual processor derivate populating the phyCORE module.

  • Page 61: Table 10: Signal Definition Phy 0 Ethernet Port (U17)

    E1_LED0 Link/activity LED output "H"/LED off no link "L"/LED on link "toggle"/LED toggle activity E1_LED1 Speed LED output "H"/LED off 10BT "L"/LED on 100BT Table 11: Signal Definition PHY 1 Ethernet Port (U18) © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 62: Mac Address

    IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE-MCF548x is located on the bar code sticker attached to the module.

  • Page 63: Real-Time Clock Rtc-8564 (U16)

    • 24-hour format • Automatic word address incrementing • Programmable alarm, timer and interrupt functions If the phyCORE-MCF548x is equipped with a battery (VBAT), the Real-Time Clock runs independently of the board’s power supply. The Real-Time Clock is programmed via the I C bus (address 0xA2 / 0xA3).
  • Page 64 For more information on the features of the RTC-8564, refer to the corresponding Data Sheet. Note: After connection of the supply voltage, or after a reset, the Real-Time Clock generates no interrupt. The RTC must first be initialized (see RTC Data Sheet for more information). © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 65: Phycore Development Board Pcm-982

    Development Board PCM-982 phyCORE Development Board PCM-982 PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules. Development...

  • Page 66: Development Board Pcm-982 Overview

    GND connector (for connection of GND signal of measuring devices such as an oscilloscope) dual DB-9 plugs for CAN interface connectivity dual DB-9 sockets for RS-232 interface connectivity Boot/NMI push button Reset push button © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 67 Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 68: Figure 11: View Of The Development Board Pcm-982

    Figure 11: View of the Development Board PCM-982 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 69: Jumpers On The Phycore Development Board

    Jumpers on the phyCORE Development Board PCM-982 Peripheral components of the phyCORE Development Board PCM-982 can be connected to the signals of the phyCORE-MCF548x by setting the applicable jumpers. The Development Board’s peripheral components are configured for use with the phyCORE-MCF548x by means of removable jumpers. If no jumpers are set, no signals are connected to the CAN transceivers.

  • Page 70: Table 13: Development Board Jumper Overview

    Figure 13 shows the factory default jumper settings for operation of the phyCORE Development Board PCM-982 with the standard phyCORE-MCF548x. Jumper settings other functional configurations of the phyCORE-MCF548x module mounted on the Development Board are described in section 10.3. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 71: Functional Components On The Phycore Development Board Pcm-982

    Development Board PCM-982 supported by the phyCORE-MCF548x and appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-MCF548x module, alternative jumper settings can be used. These jumper settings are different from the factory default settings as shown in Figure 13 and enable alternative or additional functions on the phyCORE Development Board PCM-982 depending on user needs.

  • Page 72: First Serial Interface At Socket P2A

    Socket P2B is the top socket of the double DB-9 connector at P2. Pin 2 TXD1 Pin 3 RXD1 Pin 5 GND Figure 16: Pin Assignment of the DB-9 Socket P2B as Second RS-232 (Front View) © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 73: First Can Interface At Plug P1A

    Depending on the configuration of the CAN transceivers and their power supply, the following two configurations are possible: 1. CAN transceiver on the phyCORE-MCF548x is populated and the CAN signals from the module extend directly to plug P1A. Jumper...

  • Page 74: Figure 18: Pin Assignment Of The Db-9 Plug P1A (Can Transceiver On Development Board With Galvanic Separation)

    Figure 18: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on Development Board with Galvanic Separation) Please make sure the CAN transceiver on the phyCORE-MCF548x is not populated and Jumper J21 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2005...

  • Page 75: Second Can Interface At Plug P1B

    Plug P1B is the top plug of the double DB-9 connector at P1. P1B is connected to the second CAN interface (CAN_1) of the phyCORE-MCF548x via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following two configurations are possible: 1.

  • Page 76: Figure 20: Pin Assignment Of The Db-9 Plug P2B (Can Transceiver On Development Board With Galvanic Separation)

    Figure 20: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board with Galvanic Separation) Please make sure the CAN transceiver on the phyCORE-MCF548x is not populated and Jumper J21 is closed at 1+2 and 3+4. © PHYTEC Messtechnik GmbH 2005...

  • Page 77: Programmable Led D29

    The phyCORE Development Board PCM-982 offers a programmable LED at D29 for user implementations. This LED is connected to port pin XPLD1_0 of the phyCORE-MCF548x. A low-level at port pin XPLD1_0 causes the LED to illuminate, LED D29 remains off when writing a high-level to XPLD1_0.

  • Page 78: Figure 21: Pin Assignment Scheme Of The Expansion Bus

    Figure 21: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 22: Pin Assignment Scheme of the Patch Field © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 79 Development Board PCM-982 The pin assignment on the phyCORE-MCF548x, in conjunction with the expansion bus (X12) on the Development Board and the patch field on an expansion board, is as follows: phyCORE-MCF548x Development Board Expansion Board PCM-982 PCM-988 Expansion Bus Patch Field Alt.
  • Page 80 XPLD3_10 XPLD3_10 BUS18 XPLD3_12 XPLD3_12 BUS20 XPLD3_15 XPLD3_15 CF_VS2 BUS23 XPLD3_17 XPLD3_17 CF_CSEL BUS25 XPLD3_18 XPLD3_18 CF_CS1 BUS26 XPLD3_20 XPLD3_20 BUS28 XPLD3_23 XPLD3_23 BUS31 XPLD3_25 XPLD3_25 BUS33 XPLD3_26 XPLD3_26 BUS34 XPLD3_28 XPLD3_28 CF_IOWR BUS36 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 81 BUS105 /PCI_STOP /PCI_STOP BUS106 PCI_PAR PCI_PAR BUS108 PCI_AD15 PCI_AD15 BUS111 PCI_AD13 PCI_AD13 BUS113 PCI_AD11 PCI_AD11 BUS114 PCI_AD9 PCI_AD9 BUS116 /PCI_CXBE0 /PCI_CXBE0 BUS119 PCI_AD6 PCI_AD6 BUS121 PCI_AD4 PCI_AD4 BUS122 PCI_AD2 PCI_AD2 BUS124 PCI_AD0 PCI_AD0 BUS127 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 82 GPIO55 XPLD1_5 XPLD1_5 GPIO58 XPLD1_7 XPLD1_7 GPIO60 XPLD1_8 XPLD1_8 GPIO61 XPLD1_10 XPLD1_10 GPIO63 XPLD0_34 XPLD0_34 GPIO66 XPLD0_32 XPLD0_32 GPIO68 XPLD0_31 XPLD0_31 GPIO69 XPLD0_29 XPLD0_29 GPIO71 XPLD0_26 XPLD0_26 GPIO74 XPLD0_24 XPLD0_24 GPIO76 XPLD0_22 XPLD0_22 GPIO77 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 83 /CTS0_TTL /CTS0_TTL GPIO24 DSPI_SIN DSPI_SIN GPIO25 DSPI_SOUT DSPI_SOUT GPIO27 DSPI_SCK DSPI_SCK GPIO30 DSPI_CS0 DSPI_CS0 GPIO32 GPIO33 /IRQRTC /IRQRTC GPIO35 E0_RX+ E0_RX+ GPIO38 E0_TX+ E0_TX+ GPIO40 USB+ USB+ GPIO41 USB- USB- GPIO43 E1_RX+ E1_RX+ GPIO46 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 84 XPLD_TDI GPIO97 XPLD_TDO XPLD_TDO GPIO99 ADC7 ADC7 GPIO102 ADC5 ADC5 GPIO104 ADC4 ADC4 GPIO105 ADC2 ADC2 GPIO107 REFA REFA GPIO110 Table 18: Signal Pin Assignment for the phyCORE-MCF548x / Development Board / Expansion Board © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 85 59D, 64D, 69D 46D, 47D, 48D, GNDA 77C, 74D, 79D GNDA 77C, 74D, 79D 51D, 52D, 53D, 1E, 2E Table 19: Pin Assignment Power Supply for the phyCORE-MCF548x / Development Board / Expansion Board © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 86: Silicon Serial Number/Temperature Sensor

    Development Board PCM-982 is connected to port pin XPLD1_4 of the XPLD. +3V3 DS18B20 XPLD1_4 Figure 23: Connecting the DS18B20 Temperature Sensor with Silicon Serial Number Figure 24: Pin Assignment of the DS2401 Silicon Serial Number © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 87: Bdm Port X2

    Pin Assignment of the BDM Pin Header X2 Caution: Do not install or remove the BDM cable from the header while the target system is powered up. Always disconnect the power supply before attaching or removing the BDM device! © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 88: Technical Specification Of The Development Board

    10.3.10 Technical Specification of the Development Board Figure 25 Physical Dimensions of the Development Board PCM-982 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 89 128 Mbyte Typ. 750 mA DDR SDRAM 32 Mbyte Flash without any installed I/O line or CF card, MMC/SD card, PCI card or expansion board Table 21: Technical Data of the Development Board PCM-982 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 90: Release Notes

    • CF-Card socket X8 pin 7 is disconnected from /FB_CS1 and wired to the phyCORE connector X1A6 signal XPLD3_1. • Power Connector X10: Pins 2 and 3 have to short circuit to connect the system ground to the external power supply line. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 91: Technical Specifications Of The Phycore-Mcf548X

    Technical Specification 11 Technical Specifications of the phyCORE-MCF548x The physical dimensions of the phyCORE-MCF548x are represented in Figure 26. PCB 1229.0 PHYTEC Flash ColdFire MCF548x Pin 1 XPLD Flash SDRAM Pin 2 SDRAM Figure 26: Physical Dimensions © PHYTEC Messtechnik GmbH 2005...
  • Page 92 RTC only Reset Delay Time After valid system Approx. 200 ms voltages Table 22: Technical Data of the phyCORE-MCF548x These specifications describe the standard configuration of the phyCORE-MCF548x as of the printing of this manual. © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 93 Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-MCF548x. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (3 mm) on the underside of the phyCORE must be subtracted.

  • Page 94: Hints For Handling The Module

    Alternatively, a hot air gun can be used to heat and loosen the bonds. Integrating the phyCORE-MCF548x in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module.

  • Page 95: Design Considerations - Check List

    • Data line D0 represents the LSB and D31 the MSB. • Address line A0 represents the LSB and A31 the MSB. • Byte ordering is Big Endian. • Never connect signals to the MCF548X output drivers carrying a higher potential (e.g.

  • Page 96: Revision History

    14 Revision History Date Version numbers Changes in this manual 1/21/05 Manual L-645e_1 First release version. PCM-024 PCB# 1229.0 PCM-982 PCB# 4132.0 © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 97: Component Placement Diagram

    Component Placement Diagram 15 Component Placement Diagram INSERT 1229-0BS TurboCAD.dxf Figure 27: phyCORE-MCF548x Component Placement, Top View INSERT 1229-0LS TurboCAD.dxf Figure 28: phyCORE-MCF548x Component Placement, Bottom View © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 98: A Appendices

    • ADC converter is not present on 1229.0. Footprint is not compatible to the device. • Bootstrapping problems for the PHY 1 (U18) device. Reset input must be connected to /RSTI instead of /RSTO. © PHYTEC Messtechnik GmbH 2005 L-645e_1...

  • Page 99: Index

    Dimensions........90 CAN ..........4 DMA..........4 Optical Isolation .....52 DS18B20 ........85 Terminating Resistor....54 DS2401........85 CAN Bus ........52 CAN Connector......64 CAN Interface ......52 EEPROM........42 CAN Transceiver ....30, 52 EEPROM, serial ......46 CAN_0 ........72 EMAC .........4 CAN_1 ........74 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 100 C Bus Frequency ....46 J8 ..........28 C Interface ......46 J9 ..........28 Intel Strata Flash ....... 43 JTAG ........6, 49 Introduction......... 3 Jumper Configuration ....68 ispXPLD LC5256MV....49 Jumper Location......25 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 101 Supply Voltage ......35 Pinout ........23 Serial Memory......28 Plug P1A ........72 System Memory ......42 Plug P1B........74 System Start-Up Power Requirements ....35 Configuration ......39 Power Supply ......10, 70 Internal SRAM2 .....28 Programmable LED ....76 Technical Specifications phyCORE-MCF548x .....90 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 102 X6..........64 USB2.0........4 X7..........64 X8..........64 VB082 ........92 X9..........64 VB085 ........92 XPLD ........49 VBAT........35 XPLD Firmware......50 VHLD ........50 XPLD System Logic Device..49 VIN5V........35 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 103 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Messtechnik GmbH 2005 L-645e_1...
  • Page 104 Published by © PHYTEC Messtechnik GmbH 2005 Ordering No. L-645e_1 Printed in Germany...

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