FabiaTech FX5612 User Manual page 30

FabiaTech Corporation
DRAM RAS# to CAS# delay
This field specifies the length of the delay inserted between RAS and CAS signals of
the Synchronous DRAM system access cycle when SDRAM is installed.
Available Options: 3, 2
Default setting: 3
DRAM RAS# Precharge
This field specifies the length of the RAS pre-charge part of the Synchronous DRAM
access cycle when SDRAM is installed.
Available Options: 3, 2
Default setting: 3
DRAM Date Integrity Mode
Select parity ECC (Error –Correcting Code), according to the type of installed
DRAM
MGM Core Frequency
This Select equates are used for determining the FSB/MEM/GFX, Low/GFX High core
frequency DRAM Date integrity mode
Available Options: AUTO Max 266Mhz, 400/266/133/200Mhz, 400/200/100/200Mhz,
400/200/100/133Mhz, 400/266/133/267Mhz, 400/333/166/250Mhz, Auto Max
400/300Mhz
Default setting: Auto Max 400/300Mhz
System BIOS Cacheable
This field specifies selecting enabled allows caching of the system BIOS ROM at
F0000H ~ FFFFFH, resulting in better system performance.
writes to this memory area, a system error may result.
Available Options: Disabled, Enabled
Default setting: Enabled
Video BIOS Cacheable
This field specifies selecting enabled allows caching of the video BIOS ROM,
resulting in better system performance.
memory area, a system error may result.
Available Options: Disabled, Enabled
Default setting: Enabled
However, if any program
However, if any program writes to this
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