Backup And Recovery; Dd Sequence; Table 59 Vdd Sequence Characteristics - Epson RX8804CE Applications Manual

Real time clock module
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RX8804CE

8.10. Backup and Recovery

tR1
V
DET
0V
2
I
C-Bus Communication state
Non-Communication
Figure 25 V
Sequence
DD
This circuit is sensitive to power supply noise and supply voltage should be stabilized to avoid negative impact on the
accuracy.
tR1 is needed for a proper power-on reset. If this power-on condition cannot be kept, it is necessary to send an
initialization routine to the RTC by software.
In case of repeated ON / OFF of the power supply within short term, it is possible that the power-on reset becomes
unstable.
After power-OFF, keep V
DD
When it is impossible, please initialize the RTC by the software.
As for the communication of I
If such communication requires 2 seconds (Max.) or longer, the I
function.
*:tR2 is specifications for an oscillation not to stop. Some clocks are not output by an FOUT terminal.
When bus-time-out occur, SDA turns to Hi-Z input mode. readout data of a clock is stable anytime, and there isn't
contradiction.
And it does not occur that data of a clock delay even if access time is prolonged.
Table 59 V
sequence characteristics
DD
Item
Power supply rise time1
Access wait time
(after initial power on)
Power supply fall time
Power supply rise time
Setup time from finish of I
V
DD
tCL
Communication
= GND for more than 10 seconds for a proper power-on reset.
2
C-Bus, completion of less than 1 second is recommended.
symbol
tR1
tCL
tF
tR2
2
C-Bus
tCD
tF
tCD
Back-up operation
Non-Communication
2
C-Bus interface is reset by the internal bus timeout
Condition
Min.
V
= V
~ 5.5 V
DD
SS
After V
= V
DET
DD
V
= 5.5 V ~ V
100
DET
DD
V
= V
~ 5.5 V
DET
DD
Before V
= V
DET
DD
Page - 37
*
tR2
Typ.
Max.
1
10
30
15
0
Unit
ms / V
ms
µs / V
µs / V
µs
ETM59E-05

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