Evaluation Board Schematics And Artwork - Analog Devices EVAL-AD5753SDZ User Manual

EVAL-AD5753SDZ

EVALUATION BOARD SCHEMATICS AND ARTWORK

SCHEMATIC PAGE - DUT & SUPPLY
AVDD1/AVSS
AVDD1
GND
AVSS
1727023
JP17
OPTION TO SHORT AVSS TO GND => UNIPOLAR SUPPLY
GND
AVDD2
AVDD2
GND
1727010
VLOGIC SOURCE OPTIONS
3.3V_SDP
IN
VLDO IN
GROUND PLANE APPROACH = SHORT AGND, DGND, PGND1 AND PGND2 TO PRODUCE "GND"
REFGND "ISLAND" PINNED TO OTHER GND PLAIN AT 1 POINT
GND
GND
GND
GND
TP3 TP5 TP7
1 BLK 1 BLK 1 BLK
GND
TP4 TP6 TP8
1 BLK 1 BLK 1 BLK
GND
User Guide
TERMINAL BLOCK DECOUPLING CAPACITORS
C2
4.7µF
C3
4.7µF
C4
4.7µF
GND
VLOGIC
RED
1
VLOGIC
OUT
VLOGIC_SOURCE
R2
0Ω
REFGND
AV
DD2
TP9 TP11
1 BLK 1 BLK
VLDO
ZENER CLAMPS VIN TO 15V IF A LARGER VOLTAGE IS APPLIED
TP10 TP12
1 BLK 1 BLK
Figure 17. AD5753
AVDD1-AVDD2-SHRT
2
1
AVDD1
1 RED
AV
OUT
DD1
C5
0.1µF
GND
BLK
1
GND
C6
AVSS
0.1µF
RED
1
AV
OUT
SS
AVDD2_
RED
1
AV
OUT
DD2
C7
0.1µF
AD5753 REFIN OPTIONS
ADR-REF
1 RED
ADR-REF
IN
REFOUT
1 RED
REFOUT
IN
IN
VIN = 3V - 15V
C8
C
1µF
D1
IN
A
REFGND
REFGND
Supplies and Reference Options
Rev. 0 | Page 15 of 22
AV
IN
DD2
JP2
2 1
REFIN
1 RED
REFIN
OUT
JP4
2 1
U1
6
2 VOUT
VIN
8
C9
DNC
0.1µF
ADR4525BRZ
REFGND
REFGND
UG-1492
ADR-REF
OUT
ADR-REF
C11
1µF