Related Manuals for Texas Instruments TPS54973EVM-017
Summary of Contents for Texas Instruments TPS54973EVM-017
- Page 1 TPS54973EVM 017 9 Amp, SWIFTE Regulator With Disabled Sink During Startup Evaluation Module User’s Guide September 2003 PMP Systems Power SLVU091...
- Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products & application solutions:...
- Page 3 EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods.
- Page 4 EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated...
- Page 5 About This Manual This user’s guide describes the characteristics, operation, and the use of the TPS54973EVM-017 evaluation module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.
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Page 7: Table Of Contents
Contents Contents Introduction ..............Background . - Page 8 ........1−2 TPS54973EVM-017 Performance Specification Summary ......
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Page 9: Introduction
Chapter 1 Introduction This chapter contains background information for the TPS54973 as well as support documentation for the TPS54973EVM-017 evaluation module (HPA0017). The TPS54973EVM-017 performance specifications are given, as well as modifications. Topic Page Background .......... -
Page 10: Background
Background 1.1 Background TPS54973EVM−017 evaluation module uses TPS54973 synchronous buck regulator with disabled sink during startup (DSDS) to provide an output voltage from 0.9 V to 2.5 V from a nominal 3.3-V input. Rated input voltage and output current ranges are listed in Table 1−1. This evaluation module is designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54973 regulator. -
Page 11: Performance Specification Summary
J4). Using the precharge circuitry on this EVM requires careful consideration of line and load conditions for proper operation and may limit the useful operating range of the TPS54973 device. Table 1−2. TPS54973EVM-017 Performance Specification Summary Parameters Test Conditions... -
Page 12: Modifications
Modifications 1.3 Modifications The TPS54973EVM-017 is designed to demonstrate the small size that can be attained when designing with the TPS54973, so many of the features which allow for extensive modifications have been omitted from this EVM. 1.3.1 Output Voltage... -
Page 13: Alternate Output Filters
1.3.3 Alternate Output Filters The TPS54973EVM-017 EVM also supports alternate output filter configurations by means of pads located on the back side of the PCB. The positions for C15, C16, and C17 provide space for up to three electrolytic type surface mount capacitors as an alternative to the ceramic types provided. -
Page 14: Input Capacitor
Modifications connector terminals, while leaving J3 open. Headers J5 and J6 are provided to select two, three, or four series diodes. Install a jumper across the header to bypass the adjacent diode. Care must be taken to use the correct number of diodes for the application. - Page 15 Test Setup and Results This chapter describes how to properly connect, setup, and use the TPS54973EVM-017 evaluation module. The chapter also includes test results typical for the TPS54973EVM-017 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and startup.
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Page 16: Input/Output Connections
Input/Output Connections 2.1 Input/Output Connections The TPS54973EVM−017 has the following three input/output connectors: VIN J2, VOUT J1, and PRECHG_IN J4. A diagram showing the connection points is shown in Figure 2−1. A power supply capable of supplying 8 A should be connected to J2 through a pair of 20 AWG wires. -
Page 17: Connection Diagram
Input/Output Connections Figure 2−1. Connection Diagram POWER SUPPLY Oscilloscope 3−4V, 8 A Optional Precharge Connection POWER SUPPLY Voltmeter Voltmeter 3−4 V, 8 A − − Load − 0 − 9A Optional Input Capacitor Test Setup and Results... -
Page 18: Efficiency
Efficiency 2.2 Efficiency The TPS54973EVM−017 efficiency peaks at a load current of about 1 A to 2 A and then decreases as the load current increases towards full load. Figure 2−2 shows the efficiency of the TPS54973 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures due to temperature variation in the drain-to-source resistance of the MOSFETs. -
Page 19: Power Dissipation
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a well designed board layout, allows the TPS54973EVM−017 EVM to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 9-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. -
Page 20: Output Voltage Regulation
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54973EVM−017 is shown in Figure 2−4, while the output voltage line regulation is shown in Figure 2−5. Measurements are shown for an ambient temperature of 25°C Figure 2−4. -
Page 21: Load Transients
Load Transients 2.5 Load Transients The TPS54973EVM−017 response to load transients is shown in Figure 2−6. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. -
Page 22: Output Voltage Ripple
Output Voltage Ripple Figure 2−8. Measured Loop Response, TPS54973, V = 4 V MEASURED LOOP RESPONSE Phase Gain −10 −30 −60 −20 −90 −30 −40 −120 −150 −50 −180 −60 10 k 100 k f − Frequency − Hz 2.7 Output Voltage Ripple The TPS54973EVM−017 output voltage ripple is shown in Figure 2−9. -
Page 23: Input Voltage Ripple
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54973EVM−017 output voltage ripple is shown in Figure 2−10. The input voltage is 3.3 V for the TPS54973. Output current for each device is the rated full load of 9 A. Figure 2−10. Input Voltage Ripple, TPS54973 V O (ac) 50 mV/div V phase 2 V/div... -
Page 24: Start Up
Start Up 2.9 Start Up The startup voltage waveforms of the TPS54973EVM−017 are shown in Figure 2−11 through Figure 2−15. Figure 2−11 shows the start up waveform with no precharge on the output. When V reaches the nominal 2.95-V UVLO threshold, the slow start capacitor C5 begins to charge. -
Page 25: Measured Start Up Waveform, Two Diode Precharge
Start Up Figure 2−12. Measured Start Up Waveform, Two Diode Precharge V I 500 mV/div V O 500 mV/div t − Time − 5 ms/div Figure 2−13. Measured Start Up Waveform, Three Diode Precharge V I 500 mV/div V O 500 mV/div t −... -
Page 26: Measured Start Up Waveform, Four Diode Precharge
Start Up Figure 2−14. Measured Start Up Waveform, Four Diode Precharge V I 500 mV/div V O 500 mV/div t − Time − 5 ms/div Figure 2−15 shows the start up waveform with the output precharged through four diodes and no load. Compare the precharge level to that in Figure 2−14 to see how start up load current affects the voltage drop across the diodes and the final precharge voltage. -
Page 27: Board Layout
Chapter 3 Board Layout This chapter provides a description of the TPS54973EVM-017 board layout and layer illustrations. Topic Page Layout ............ -
Page 28: Layout
Layout 3.1 Layout The board layout for the TPS54973EVM−017 is shown in Figure 3−1 through Figure 3−6. The topside layer of the TPS54973EVM−017 is laid out in a manner typical of a user application. The bottom layer of the TPS54973EVM−017 is designed to accommodate optional alternate output filter capacitors. -
Page 29: Internal Layer
Layout Figure 3−2. Internal Layer 2 Figure 3−3. Internal Layer 3 Board Layout... -
Page 30: Bottom Side Layout
Layout Figure 3−4. Bottom Side Layout Figure 3−5. Top Side Assembly... -
Page 31: Bottom Layer Assembly
Layout Figure 3−6. Bottom Layer Assembly Board Layout... -
Page 32: Schematic And Bill Of Materials
Chapter 4 Schematic and Bill of Materials The TPS54973EVM-017 schematic and bill of materials are presented in this chapter. Topic Page Schematic ........... . -
Page 33: Schematic
Schematic 4.1 Schematic The schematic for the TPS54973EVM−017 is shown in Figure 4−1. Figure 4−1. TPS54973EVM-017 Schematic TPS54973 71.5 kΩ SYNCH 22 µF 22 µF 22 µF SS/ENA 0.047 µF VBIAS 1 µF 10 kΩ PRECHG_IN PWRGD COMP 10 kΩ... -
Page 34: Bill Of Materials
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54973EVM−017 is listed in Table 4−1. Table 4−1. TPS54973EVM-017 Bill of Materials Count Ref Des Description Size Part Number Capacitor, POSCAP, 220 µF, 10 V, − 7343 (D)
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