Renesas RL78/I1A User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Microcontrollers
  5. RL78/I1A
  6. User manual
Renesas RL78/I1A User Manual

Renesas RL78/I1A User Manual

16-bit single-chip
Hide thumbs Also See for RL78/I1A:
1
2
3
4
5
Table Of Contents
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
Table of Contents

Advertisement

Quick Links

Download this manual
Cover
RL78/I1A
16
16-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.3.20 Sep 2017

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the RL78/I1A and is the answer not in the manual?

Questions and answers

Related Manuals for Renesas RL78/I1A

Summary of Contents for Renesas RL78/I1A

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/I1A manual is separated into two parts: this manual and the software edition (common to the RL78 Microcontroller). RL78/I1A RL78 Family User’s Manual...
  • Page 5 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.

  • Page 6: Table Of Contents

    CONTENTS CHAPTER 1 OUTLINE ..........................1 1.1 Features ............................1 1.2 List of Part Numbers ........................3 1.3 Pin Configuration (Top View) ......................4 1.3.1 20-pin products ..........................4 1.3.2 30-pin products ..........................5 1.3.3 38-pin products ..........................6 1.4 Pin Identification ..........................7 1.5 Block Diagram ..........................
  • Page 7 3.2.4 Special function registers (SFRs) ....................57 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......62 3.3 Instruction Address Addressing ....................75 3.3.1 Relative addressing ......................... 75 3.3.2 Immediate addressing ........................75 3.3.3 Table indirect addressing ........................ 76 3.3.4 Register indirect addressing ......................
  • Page 8 4.4.1 Writing to I/O port .......................... 105 4.4.2 Reading from I/O port ........................105 4.4.3 Operations on I/O port ........................105 4.4.4 Handling different potential (2.5 V, 3 V) ..................106 4.4.5 Handling different potential (2.5 V, 3 V) by using I/O buffers ............106 4.5 Register Settings When Using Alternate Function ..............
  • Page 9 5.6.7 Time required for switchover of CPU clock and system clock ............160 5.6.8 Conditions before clock oscillation is stopped ................161 CHAPTER 6 TIMER ARRAY UNIT ...................... 162 6.1 Functions of Timer Array Unit ....................163 6.1.1 Independent channel operation function ..................163 6.1.2 Simultaneous channel operation function ..................
  • Page 10 6.7 Timer Input (TI0n) Control ......................216 6.7.1 TI0n input circuit configuration ....................... 216 6.7.2 Noise filter ............................. 216 6.7.3 Cautions on channel input operation ..................... 217 6.8 Independent Channel Operation Function of Timer Array Unit ..........218 6.8.1 Operation as interval timer/square wave output ................218 6.8.2 Operation as external event counter .....................
  • Page 11 7.4.1 Counter basic operation ........................ 293 7.4.2 Default level and active level ......................293 7.4.3 Stop/restart operation ........................297 7.4.4 Batch overwrite operation ......................300 7.4.5 Standalone mode (period controlled by TKBCRn0) ............... 301 7.4.6 Standalone mode (period controlled by external trigger input) ............307 7.4.7 Simultaneous start/stop mode .......................
  • Page 12 8.3.2 Timer clock select register 2 (TPS2) ..................... 388 8.3.3 16-bit timer KC operation control register 0 (TKCCTL0) ..............389 8.3.4 16-bit timer KC output control register 00 (TKCIOC00) ..............390 8.3.5 16-bit timer KC output control register 01 (TKCIOC01) ..............391 8.3.6 16-bit timer KC output pin control register (TOETKC0) ..............
  • Page 13 9.4.5 1 Hz output of real-time clock ......................427 9.4.6 Example of watch error correction of real-time clock ..............428 CHAPTER 10 12-BIT INTERVAL TIMER .................... 433 10.1 Functions of 12-bit Interval Timer ................... 433 10.2 Configuration of 12-bit Interval Timer ..................433 10.3 Registers Controlling 12-bit Interval Timer ................
  • Page 14 12.4 A/D Converter Conversion Operations .................. 471 12.5 Input Voltage and Conversion Results .................. 473 12.6 A/D Converter Operation Modes ..................... 474 12.6.1 Software trigger mode (select mode, sequential conversion mode) ..........474 12.6.2 Software trigger mode (select mode, one-shot conversion mode) ..........475 12.6.3 Software trigger mode (scan mode, sequential conversion mode) ..........
  • Page 15 CHAPTER 14 COMPARATOR ......................514 14.1 Functions of Comparator ......................514 14.2 Configuration of Comparator ....................516 14.3 Registers Controlling Comparator ..................516 14.3.1 Peripheral enable register 2 (PER2) .................... 517 14.3.2 Comparator n control register (CnCTL) ..................517 4.3.3 Comparator and PGA internal reference voltage control register (CVRCTL) ........ 519 14.3.4 Comparator internal reference voltage select register m (CmRVM) ..........
  • Page 16 15.3.12 Serial output register m (SOm) ....................560 15.3.13 Serial output level register m (SOLm) ..................561 15.3.14 Serial standby control register 0 (SSC0) ................... 562 15.3.15 Input switch control register (ISC) ..................... 563 15.3.16 Noise filter enable register 0 (NFEN0) ..................564 15.3.17 Registers controlling port functions of serial I/O pins ..............
  • Page 17 16.3.2 Serial clock select register 4 (SPS4) ................... 682 16.3.3 Serial mode register 4n (SMR4n) ....................684 16.3.4 Serial communication operation setting register 4n (SCR4n) ............685 16.3.5 Higher 7 bits of the serial data register 4n (SDR4n) ..............687 16.3.6 Serial status register 4n (SSR4n) ....................
  • Page 18 17.3.2 IICA control register 00 (IICCTL00) ..................... 769 17.3.3 IICA status register 0 (IICS0) ....................... 774 17.3.4 IICA flag register 0 (IICF0) ......................776 17.3.5 IICA control register 01 (IICCTL01) ..................... 778 17.3.6 IICA low-level width setting register 0 (IICWL0) ................780 17.3.7 IICA high-level width setting register 0 (IICWH0) ................
  • Page 19 18.4.2 Multiplication (signed) operation ....................855 18.4.3 Multiply-accumulation (unsigned) operation ................856 18.4.4 Multiply-accumulation (signed) operation ..................858 18.4.5 Division operation ........................860 CHAPTER 19 DMA CONTROLLER ..................... 862 19.1 Functions of DMA Controller ....................862 19.2 Configuration of DMA Controller .................... 863 19.2.1 DMA SFR address register n (DSAn) ..................
  • Page 20 20.4 Interrupt Servicing Operations ....................904 20.4.1 Maskable interrupt request acknowledgment ................904 20.4.2 Software interrupt request acknowledgment ................907 20.4.3 Multiple interrupt servicing ......................907 20.4.4 Interrupt request hold ........................911 CHAPTER 21 STANDBY FUNCTION ....................912 21.1 Standby Function ........................912 21.2 Registers Controlling Standby Function ................
  • Page 21 25.3.1 Flash memory CRC operation function (high-speed CRC) ............962 25.3.1.1 Flash memory CRC control register (CRC0CTL) ............962 25.3.1.2 Flash memory CRC operation result register (PGCRCL) ........... 963 25.3.2 CRC operation function (general-purpose CRC) ................. 965 25.3.2.1 CRC input register (CRCIN) ..................965 25.3.2.2 CRC data register (CRCD) ..................
  • Page 22 28.2.6 Power supply ..........................996 28.3 Serial Programming Method ....................996 28.3.1 Serial programming procedure ....................996 28.3.2 Flash memory programming mode ....................997 28.3.3 Selecting communication mode ....................998 28.3.4 Communication commands ......................999 28.4 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) ..1001 28.5 Self-Programming ........................
  • Page 23 CHAPTER 32 ELECTRICAL SPECIFICATIONS (G: Industrial applications, T 40 to +105C) ............1040  32.1 Absolute Maximum Ratings ....................1041 32.2 Oscillator Characteristics ...................... 1043 32.2.1 X1, XT1 oscillator characteristics ....................1043 32.2.2 On-chip oscillator characteristics ....................1044 32.2.3 PLL characteristics ........................1044 32.3 DC Characteristics .........................
  • Page 24 33.5.2 Serial interface IICA ........................1113 33.6 Analog Characteristics ......................1115 33.6.1 A/D converter characteristics ..................... 1115 33.6.2 Temperature sensor/internal reference voltage characteristics ..........1118 33.6.3 Programmable gain amplifier ..................... 1119 33.6.4 Comparator ..........................1120 33.6.5 POR circuit characteristics ......................1121 33.6.6 LVD circuit characteristics ......................

  • Page 25: Chapter 1 Outline

    R01UH0169EJ0320 RL78/I1A Rev.3.20 RENESAS MCU Sep 29, 2017 CHAPTER 1 OUTLINE 1.1 Features Ο Operation clocks  1 to 32 MHz (when using high-speed on-chip oscillator clock)  32.768 kHz (when using subsystem clock) Ο General-purpose registers: (8-bit register × 8) × 4 banks Ο...
  • Page 26 RL78/I1A CHAPTER 1 OUTLINE Ο ROM, RAM capacities Flash ROM Data flash RL78/I1A 20 pins 30 pins 38 pins  64 KB 4 KB 4 KB Note R5F107AE R5F107DE  32 KB 4 KB 2 KB R5F1076C R5F107AC Note This is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3.)

  • Page 27: List Of Part Numbers

    = 40 to +125C R5F107DEMSP#V0, R5F107DEMSP#X0 Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 28: Pin Configuration (Top View)

    RL78/I1A CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 20-pin products  20-pin plastic LSSOP (4.4 x 6.5) P21/ANI1/AV P22/ANI2/CMP0P REFM P20/ANI0/AV P24/ANI4/CMP1P REFP P40/TOOL0 P25/ANI5/CMP2P RESET P147/CMPCOM/ANI18/(CMP3P) P137/INTP0 P10/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4) P122/X2/EXCLK P11/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0) P121/X1 P200/TKBO00/INTP22 REGC P201/TKBO01 P202/TKBO10/(INTP21) P203/TKBO11/TKCO02/(INTP20) ...

  • Page 29: 30-Pin Products

    RL78/I1A CHAPTER 1 OUTLINE 1.3.2 30-pin products  30-pin plastic LSSOP (7.62 mm (300)) P20/ANI0/AV P21/ANI1/AV REFP REFM P03/RxD1/CMP5P/ANI16 P22/ANI2/CMP0P P02/TxD1/ANI17 P24/ANI4/CMP1P P120/ANI19 P25/ANI5/CMP2P P40/TOOL0 P26/ANI6/CMP3P P27/ANI7/CMP4P RESET P137/INTP0 P147/CMPCOM/ANI18 P10/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4) P122/X2/EXCLK P11/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0) P121/X1 P200/TKBO00/INTP22 REGC P201/TKBO01 P202/TKBO10/(INTP21) P203/TKBO11/TKCO02/(INTP20) P31/TI03/TO03/INTP4...

  • Page 30: 38-Pin Products

    RL78/I1A CHAPTER 1 OUTLINE 1.3.3 38-pin products  38-pin plastic SSOP (7.62 mm (300)) P20/ANI0/AV P21/ANI1/AV REFP REFM P03/RxD1/CMP5P/ANI16 P22/ANI2/CMP0P P02/TxD1/ANI17 P24/ANI4/CMP1P P120/ANI19 P25/ANI5/CMP2P P40/TOOL0 P26/ANI6/CMP3P RESET P27/ANI7/CMP4P P124/XT2/EXCLKS P147/CMPCOM/ANI18 P123/XT1 P10/SO00/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4) P137/INTP0 P11/SI00/RxD0/TKCO01/INTP21/SDAA0/(TI07)/(DALIRxD4)/(TxRx4)/(INTP0) P122/X2/EXCLK P12/SCK00/(TKCO03) P121/X1 P200/TKBO00/INTP22 REGC P201/TKBO01...

  • Page 31: Pin Identification

    RL78/I1A CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI2, REGC: Regulator Capacitance ANI4 to ANI7, RESET: Reset ANI16 to ANI19: Analog Input RTC1HZ: Real-time Clock Correction Clock Analog Reference Voltage Minus (1 Hz) Output REFM Analog Reference Voltage Plus...

  • Page 32: Block Diagram

    RL78/I1A CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 20-pin products TIMER ARRAY UNIT (8ch) PORT 1 P10, P11 P20 to P22, PORT 2 P24, P25 PORT 4 P121, P122 PORT 12 PORT 13 P137 PORT 14 P147 (TI07)/RxD0/P11(LIN-bus, DMX512) PORT 20...

  • Page 33: 30-Pin Products

    RL78/I1A CHAPTER 1 OUTLINE 1.5.2 30-pin products TIMER ARRAY PORT 0 P02, P03 UNIT (8ch) PORT 1 P10, P11 P20 to P22, PORT 2 P24 to P27 PORT 3 TI03/TO03/P31 PORT 4 PORT 7 P120 PORT 12 P121, P122 (TI07)/RxD0/P11(LIN-bus, DMX512)

  • Page 34: 38-Pin Products

    RL78/I1A CHAPTER 1 OUTLINE 1.5.3 38-pin products TIMER ARRAY PORT 0 P02, P03, P05, P06 UNIT (8ch) PORT 1 P10 to P12 P20 to P22, PORT 2 P24 to P27 PORT 3 P30, P31 TI03/TO03/P31 PORT 4 PORT 7 P75 to P77...

  • Page 35: Outline Of Functions

    RL78/I1A CHAPTER 1 OUTLINE 1.6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR1) is set to 00H. (1/3) Item 20-pin 30-pin 38-pin R5F1076C R5F107AC R5F107AE R5F107DE Code flash memory (KB)
  • Page 36 RL78/I1A CHAPTER 1 OUTLINE (2/3) Item 20-pin 30-pin 38-pin R5F1076C R5F107AC, R5F107AE R5F107DE Timer Watchdog timer 1 channel Real-time clock 1 channel Notes 1, 2 (RTC) 12-bit interval timer 1 channel (IT)  RTC output 1 Hz (subsystem clock: = 32.768 kHz)
  • Page 37 RL78/I1A CHAPTER 1 OUTLINE (3/3) Item 20-pin 30-pin 38-pin R5F1076C R5F107AC, R5F107AE R5F107DE Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.) • Power-down-reset: 1.50 V (TYP.)  Rising edge: Voltage detector 2.81 V to 4.06 V (6 stages)  Falling edge: 2.75 V to 3.98 V (6 stages)

  • Page 38: Chapter 2 Pin Functions

    RL78/I1A CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Function The I/O buffer power supply for pins is provided by V R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 39: 20-Pin Products

    RL78/I1A CHAPTER 2 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. 2.1.1 20-pin products Function Pin Type After Reset Alternate Function Function Name Release 8-1-2 Input port TxD0/TKCO00/INTP20/ Port 1. SCLA0/(DALITxD4) 2-bit I/O port.

  • Page 40: 30-Pin Products

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.1.2 30-pin products (1/2) Function Pin Type After Reset Alternate Function Function Name Release 7-3-2 Analog input TxD1/ANI17 Port 0. port 2-bit I/O port. 8-18-1 RxD1/CMP5P/ANI16 Input of P03 can be set to TTL input buffer.
  • Page 41 RL78/I1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type After Reset Alternate Function Function Name Release 7-1-1 Input port INTP11 Port 7. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port.

  • Page 42: 38-Pin Products

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.1.3 38-pin products (1/2) Function Pin Type After Reset Alternate Function Function Name Release 7-3-2 Analog input TxD1/ANI17 Port 0. port 4-bit I/O port. 8-18-1 RxD1/CMP5P/ANI16 Input of P03 can be set to TTL input buffer.
  • Page 43 RL78/I1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type After Reset Alternate Function Function Name Release 7-1-1 Input port INTP9 Port 7. 3-bit I/O port. INTP10 Input/output can be specified in 1-bit units. INTP11 Use of an on-chip pull-up resistor can be specified by a software setting at input port.

  • Page 44: Functions Other Than Port Pins

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other than Port Pins 2.2.1 Functions for each product (1/2) Function Name 38-pin 30-pin 20-pin    ANI0    ANI1    ANI2    ANI4  ...
  • Page 45 RL78/I1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Name 38-pin 30-pin 20-pin    RESET    RxD0    RxD1    TxD0    TxD1    SCK00    SI00 ...

  • Page 46: Description Of Functions

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.2.2 Description of functions Function Name Function ANI0 to ANI7, Input A/D converter analog input ANI16 to ANI19 (see Figure 12-44 Analog Input Pin Connection) CMP0P to CMP5P Input Comparator 0 to 5 analog inputs...
  • Page 47 RL78/I1A CHAPTER 2 PIN FUNCTIONS Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows. Table 2-1. Relationships Between P40/TOOL0 and Operation Mode After Reset Release P40/TOOL0 Operating mode Normal operation mode Flash memory programming mode For details, see 28.3 Serial Programming Method.

  • Page 48: Connection Of Unused Pins

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.3 Connection of Unused Pins Table 2-2 shows the connections of unused pins. Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function. Table 2-2. Connection of Unused Pins (38-pin Products) (1/2)
  • Page 49 RL78/I1A CHAPTER 2 PIN FUNCTIONS Table 2-2. Connection of Unused Pins (38-pin Products) (2/2) Pin Name Recommended Connection of Unused Pins P120 Input: Independently connect to V or V via a resistor. Output: Leave open. P121 Input Independently connect to V or V via a resistor.

  • Page 50: Block Diagrams Of Pins

    RL78/I1A CHAPTER 2 PIN FUNCTIONS 2.4 Block Diagrams of Pins Figures 2-1 to 2-12 show the block diagrams of the pins described in 2.1.1 20-pin products to 2.1.3 38-pin products. Figure 2-1. Pin Block Diagram for Pin Type 2-1-1 RESET RESET Figure 2-2.
  • Page 51 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-3. Pin Block Diagram for Pin Type 2-2-1 Clock generator OSCSEL/ OSCSELS Alternate function P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function EXCLK, OSCSEL/ EXCLKS, OSCSELS N-ch P-ch Alternate function P121/X1/Alternate function P123/XT1/Alternate function Remark For alternate functions, see 2.1 Port Function.
  • Page 52 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-4. Pin Block Diagram for Pin Type 4-3-1 ADPC 0: Analog input ADPC 1: Digital I/O ADPC3 to ADPC0 PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) P-ch A/D converter N-ch R01UH0169EJ0320 Rev.3.20...
  • Page 53 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-5. Pin Block Diagram for Pin Type 4-18-1 ADPC 0: Analog input 1: Digital I/O ADPC PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) P-ch A/D converter N-ch Comparator input PGA input R01UH0169EJ0320 Rev.3.20...
  • Page 54 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-6. Pin Block Diagram for Pin Type 7-1-1 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1. For alternate functions, see 2.1 Port Function.
  • Page 55 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-7. Pin Block Diagram for Pin Type 7-1-2 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Caution The input buffer is enabled even if the type 7-1-2 pin is operating as an output when the N-ch open drain output mode is selected by the corresponding bit in the port output mode register (POMxx).
  • Page 56 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-8. Pin Block Diagram for Pin Type 7-1-6 Alternate function PU register (PUmn) P-ch PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) register (POMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 57 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-9. Pin Block Diagram for Pin Type 7-3-1 PU register P-ch (PUmn) PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 58 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-10. Pin Block Diagram for Pin Type 7-3-2 Alternate function PU register (PUmn) P-ch PMC register (PMCmn) PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) register (POMmn) Alternate function (SAU) Alternate function...
  • Page 59 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-11. Pin Block Diagram for Pin Type 7-9-1 Alternate function PU register (PUmn) P-ch PMC register (PMCmn) PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU)
  • Page 60 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-12. Pin Block Diagram for Pin Type 8-1-2 Alternate function PU register (PUmn) PIM register (PIMmn) PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Cautions 1.
  • Page 61 RL78/I1A CHAPTER 2 PIN FUNCTIONS Figure 2-13. Pin Block Diagram for Pin Type 8-18-1 Alternate function PU register (PUmn) PMC register (PMCmn) PIM register (PIMmn) PORT PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) register (POMmn) P-ch A/D converter...

  • Page 62: Chapter 3 Cpu Architecture

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/I1A can access a 1 MB address space. Figures 3-1 and 3-2 show the memory maps. R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...
  • Page 63 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F1076C, R5F107AC) F F F F F H 0 7 F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H...
  • Page 64 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F107AE, R5F107DE) F F F F F H 0 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H...
  • Page 65 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 0 F F F F H...
  • Page 66 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Number Address Value Block Number...

  • Page 67: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/I1A products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM...
  • Page 68 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) Vector Table Address Interrupt Source 20-pin 30-pin 38-pin    0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE    0004H INTWDTI    0006H INTLVI ...
  • Page 69 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) Vector Table Address Interrupt Source 20-pin 30-pin 38-pin    0042H INTTM04    0044H INTTM05    0046H INTTM06    0048H INTTM07  ...

  • Page 70: Mirror Area

    CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/I1A mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
  • Page 71 RL78/I1A CHAPTER 3 CPU ARCHITECTURE  Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 72: Internal Data Memory Space

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/I1A products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM 2048  8 bits (FF700H to FFEFFH) R5F1076C, R5F107AC 4096  8 bits (FEF00H to FFEFFH)

  • Page 73: Special Function Register (Sfr) Area

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned.

  • Page 74: Data Memory Addressing

    Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/I1A, based on operability and other considerations. In particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-4 and 3-5 show correspondence between data memory and addressing.
  • Page 75 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Correspondence Between Data Memory and Addressing (R5F1076C, R5F107AC) F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H 256 bytes F F F 1 F H...
  • Page 76 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing (R5F107AE, R5F107DE) F F F F F H SFR addressing Special function register (SFR) F F F 2 0 H F F F 1 F H 256 bytes...

  • Page 77: Processor Registers

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/I1A products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
  • Page 78 RL78/I1A CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.

  • Page 79: General-Purpose Registers

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

  • Page 80: And Cs Registers

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H.

  • Page 81: Special Function Registers (Sfrs)

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 82 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    FFF00H Port register 0    FFF01H Port register 1 ...
  • Page 83 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    FFF44H Serial data register 02 TXD1 SDR02 0000H    FFF45H ...
  • Page 84 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    FFFA0H Clock operation mode control register    FFFA1H Clock operation status control register ...
  • Page 85 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    FFFD0H Interrupt request flag register 2 IF2L   FFFD1H IF2H ...

  • Page 86: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
  • Page 87 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (1/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0010H A/D converter mode register 2 ADM2  ...
  • Page 88 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F00E0H Multiplication/division data register C (L) MDCL 0000H ...
  • Page 89 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0120H Serial channel enable status register 0 SE0L 0000H ...
  • Page 90 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0196H Timer mode register 03 TMR03 0000H F0197H ...
  • Page 91 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0230H IICA control register 00 IICCTL00   ...
  • Page 92 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0564H Window comparator function setting CMPWDC register  ...
  • Page 93 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (7/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F05AAH Serial output enable register 4 SOE4L SOE4 0000H ...
  • Page 94 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (8/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0610H 16-bit timer KB dithering count register 01 TKBDNR01 ...
  • Page 95 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (9/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0640H 16-bit timer KB compare register 10 TKBCR10 0000H F0641H ...
  • Page 96 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (10/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0668H 16-bit timer KB output control register 11 TKBIOC11 ...
  • Page 97 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (11/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F0692H 16-bit timer KB trigger register 2 TKBTRG2 ...
  • Page 98 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (12/12) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit    F06D0H 16-bit timer KC compare register 0 TKCCR0 0000H ...

  • Page 99: Instruction Address Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: 128 to +127 or 32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.

  • Page 100: Register Indirect Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.

  • Page 101: Addressing For Processing Data Addresses

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word.

  • Page 102: Direct Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)

  • Page 103: Short Direct Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format]...

  • Page 104: Sfr Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format]...

  • Page 105: Register Indirect Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description  [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) ...

  • Page 106: Based Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
  • Page 107 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-26. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory array <2> Offset of data <2> byte <1>...
  • Page 108 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of ES:[HL + byte], ES:[DE + byte] ES: [HL + byte], ES: [DE + byte] <1> <2> <3> <1> <2> <3> XFFFFH Instruction code <2> Target <3> Target memory OP-code array Offset...
  • Page 109 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-31. Example of ES:word[BC] ES: word [BC] <1> <2> <3> XFFFFH Array of Instruction code Target memory <3> word-sized <3> Offset data OP-code rp(BC) <2> Low Addr. Address of a word within an array <2>...

  • Page 110: Based Indexed Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address.

  • Page 111: Stack Addressing

    RL78/I1A CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
  • Page 112 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of POP POP rp <1> <2> SP + 2 <1> SP + 1 (SP+1) Stack Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
  • Page 113 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-37. Example of RET <1> SP+4 <1> SP+3 (SP+3) Instruction code (SP+2) Stack SP+2 OP-code area (SP+1) SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
  • Page 114 RL78/I1A CHAPTER 3 CPU ARCHITECTURE Figure 3-39. Example of RETI, RETB RETI, RETB <1> SP + 4 <1> (SP+3) SP + 3 Instruction code (SP+2) SP + 2 Stack OP-code (SP+1) area SP + 1 <3> (SP) <2> F0000H Stack addressing is specified <1>.

  • Page 115: Chapter 4 Port Functions

    CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/I1A microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS.

  • Page 116: Port 0

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P02, P03, P05, P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).

  • Page 117: Port 2

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input, internal reference voltage inputs of A/D converter and comparator, reference voltage input of PGA, and analog input of the comparator.

  • Page 118: Port 13

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 12 P120 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When the P120 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).

  • Page 119: Registers Controlling Port Function

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers.  Port mode registers (PMxx)  Port registers (Pxx)  Pull-up resistor option registers (PUxx)  Port input mode registers (PIMxx)  Port output mode registers (POMxx) ...
  • Page 120 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-3. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx Registers and Bits Mounted on Each Product (2/3) Port Bit Name PMxx PUxx PIMxx POMxx PMCxx Register Register Register Register Register Register     ...
  • Page 121 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-3. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx Registers and Bits Mounted on Each Product (3/3) Port Bit Name PMxx PUxx PIMxx POMxx PMCxx Register Register Register Register Register Register     ...

  • Page 122: Port Mode Registers (Pmxx)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.

  • Page 123: Port Registers (Pxx)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is...

  • Page 124: Pull-Up Resistor Option Registers (Puxx)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to normal output mode (POMmn = 0) and input mode (PMmn = 1) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.

  • Page 125: Port Input Mode Registers (Pimxx)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode registers (PIMxx) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 126: Port Mode Control Registers (Pmcxx)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers (PMCxx) These registers set the digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH.

  • Page 127: A/D Port Configuration Register (Adpc)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.7 A/D port configuration register (ADPC) This register switches the ANI0/P20, ANI1/P21, ANI2/CMP0P/P22, ANI4/CMP1P/P24 to ANI7/CMP4P/P27 pins, and PGAOUT pin (internal pin) to digital I/O of port or analog input of A/D converter, programmable gain amplifier, or comparator.

  • Page 128: Peripheral I/O Redirection Register (Pior1)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.3.8 Peripheral I/O redirection register (PIOR1) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.

  • Page 129: Port Function Operations

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

  • Page 130: Handling Different Potential (2.5 V, 3 V)

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.4.4 Handling different potential (2.5 V, 3 V) When connecting an external device operating on a different potential (2.5 V or 3 V), it is possible to connect the I/O pins of general ports by changing V to accord with the power supply of the connected device.
  • Page 131 RL78/I1A CHAPTER 4 PORT FUNCTIONS (3) Setting procedure when using I/O pins of IICA0 functions <1> Externally pull up the P10 and P11 pins to be used (on-chip pull-up resistor cannot be used). <2> After reset release, the port mode is the input mode (Hi-Z).

  • Page 132: Register Settings When Using Alternate Function

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.5 Register Settings When Using Alternate Function 4.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog input, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog input or digital input/output.

  • Page 133: Register Settings For Alternate Function Whose Output Function Is Not Used

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.5.2 Register settings for alternate function whose output function is not used When the output of an alternate function of the pin is not used, the following settings should be made. Note that when the peripheral I/O redirection function is the target, the output can be switched to another pin by setting the peripheral I/O redirection register (PIOR1).

  • Page 134: Register Setting Examples For Used Port And Alternate Functions

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Table 4-5. The registers used to control the port functions should be set as shown in Table 4-5. See the following remark for legends used in Table 4-5.
  • Page 135 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (1/7) Pin Name Used Function PIOR× POM×× PMC×× PM×× P×× Alternate Function Output 20-pin 30-pin 38-pin Function SAU Output Other than Name Function ...
  • Page 136 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (2/7) Pin Name Used Function PIOR× POM×× PMC×× PM×× P×× Alternate Function Output 20-pin 30-pin 38-pin Function Name SAU Output Other than Function ...
  • Page 137 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (3/7) Pin Name Used Function ADPC ADM2 PM×× P×× 20-pin 30-pin 38-pin Function Name   Input ADPC = 01H  ...
  • Page 138 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (4/7) Pin Name Used Function PIOR× POM×× PMC×× PM×× P×× Alternate Function Output 20-pin 30-pin 38-pin Function SAU Output Other than SAU...
  • Page 139 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (5/7) Pin Name Used Function P×× 20-pin 30-pin 38-pin (EXCLK,OSCSEL, EXCLKS, OSCSELS) Function Name     P121 P121 Input 00xx/10 xx/11 xx ...
  • Page 140 RL78/I1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Setting Examples of Registers and Output Latches When Using Pin Function (7/7) Pin Name Used Function PIOR× POM×× PMC×× PM×× P×× Alternate Function Output 20-pin 30-pin 38-pin Function SAU Output Other than Name...

  • Page 141: Cautions When Using Port Function

    The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/I1A. <1> The Pn register is read in 8-bit units.

  • Page 142: Notes On Specifying The Pin Settings

    RL78/I1A CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR1).

  • Page 143: Chapter 5 Clock Generator

        Note The frequency at which the RL78/I1A can operate depends on the operating ambient temperature. = 40 to +105°C) and For details, see CHAPTER 32 ELECTRICAL SPECIFICATIONS (T = 40 to +125°C). CHAPTER 33 ELECTRICAL SPECIFICATIONS (T An external main system clock (f = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin.
  • Page 144 RL78/I1A CHAPTER 5 CLOCK GENERATOR The main system clock, the range of frequencies that can be used by the power supply voltage is different. Thus, depending on whether the option byte (000C2H) is COMODE0 or MODE1, it is necessary to set the flash operation voltage mode.

  • Page 145: Configuration Of Clock Generator

    RL78/I1A CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency XT1 clock oscillation frequency : External subsystem clock frequency Low-speed on-chip oscillator clock frequency 5.2 Configuration of Clock Generator The clock generator includes the following hardware.
  • Page 146 RL78/I1A CHAPTER 5 CLOCK GENERATOR R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...
  • Page 147 RL78/I1A CHAPTER 5 CLOCK GENERATOR Caution When using the PLL output function, only 4 MHz can be selected as the oscillation frequency. Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency High-speed system clock frequency...

  • Page 148: Registers Controlling Clock Generator

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following ten registers are used to control the clock generator.  Clock operation mode control register (CMC)  System clock control register (CKC)  Clock operation status control register (CSC) ...
  • Page 149 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin pin operation mode...
  • Page 150 RL78/I1A CHAPTER 5 CLOCK GENERATOR Cautions 6. Although the maximum system clock frequency is 32 MHz, the maximum frequency of the X1 oscillator is 20 MHz. 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption.

  • Page 151: System Clock Control Register (Ckc)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 152: Clock Operation Status Control Register (Csc)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 153: Oscillation Stabilization Time Counter Status Register (Ostc)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-2. Stopping Clock Method Clock Condition Before Stopping Clock Setting of CSC (Invalidating External Clock Input) Register Flags CPU and peripheral hardware clocks operate with a clock X1 clock MSTOP = 1 other than the high-speed system clock.
  • Page 154 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status...

  • Page 155: Oscillation Stabilization Time Select Register (Osts)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
  • Page 156 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz  ...

  • Page 157: Pll Control Register (Pllctl)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.6 PLL control register (PLLCTL) This register controls the PLL function. When the PLL function is used, select only 4 MHz for the high-speed system clock or high-speed on-chip oscillator clock. Stop PLL function when the regulator is in the low-consumption current mode The PLLCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 158: Peripheral Enable Registers 0 To 2 (Per0 To Per2)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.7 Peripheral enable registers 0 to 2 (PER0 to PER2) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
  • Page 159 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-8. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H Symbol <7> <5> <4> <2> <0> PER0 RTCEN ADCEN IICA0EN SAU0EN TAU0EN IICA0EN Control of serial interface IICA input clock supply Stops input clock supply.
  • Page 160 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-10. Format of Peripheral Enable Register 2 (PER2) Address: F0509H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER2 PGACMPEN TKBPA2EN TKBPA1EN TKBPA0EN TKC0EN TKB2EN Note TKB1EN TKB0EN PGACMPEN Control of comparator/programmable gain amplifier input clock supply Stops input clock supply.

  • Page 161: Subsystem Clock Supply Mode Control Register (Osmc)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.8 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock.

  • Page 162: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H).

  • Page 163: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.3.10 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.

  • Page 164: System Clock Oscillator

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
  • Page 165 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-15. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock 32.768 EXCLKS External clock Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-14 and 5-15 to avoid an adverse effect from wiring capacitance.
  • Page 166 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-15 shows examples of incorrect resonator connection. Figure 5-16. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
  • Page 167 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-16. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched...

  • Page 168: High-Speed On-Chip Oscillator

    5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/I1A. The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).

  • Page 169: Clock Generator Operation

     PLL output clock f The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/I1A. When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-17.
  • Page 170 RL78/I1A CHAPTER 5 CLOCK GENERATOR Figure 5-17. Clock Generator Operation When Power Supply Voltage Is Turned On Lower limit of the operating voltage range VPOR Power-on reset signal At least 10 µs <1> RESET pin Switched by software Reset <3>...

  • Page 171: Controlling Clock

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).

  • Page 172: Example Of Setting X1 Oscillation Clock

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by...

  • Page 173: Example Of Setting Xt1 Oscillation Clock

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by...

  • Page 174: Example Of Setting Pll Circuit

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.4 Example of setting PLL circuit After setting the high-speed system clock and high-speed on-chip oscillator clock (see 5.6.1 Example of setting high-speed on-chip oscillator and 5.6.2 Example of setting X1 oscillation clock), use the PLL control register (PLLCTL) to control the PLL circuit.

  • Page 175: Cpu Clock Status Transition Diagram

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.5 CPU clock status transition diagram Figure 5-18 shows the CPU clock status transition diagram of this product. Figure 5-18. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up Power ON X1 oscillation/EXCLK input: Stops (input port mode)
  • Page 176 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/6) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
  • Page 177 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/6) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register...
  • Page 178 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/6) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register...
  • Page 179 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/6) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS...
  • Page 180 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/6) (10)  CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed on-chip oscillator clock (PLL mode) (K)  CPU clock changing from high-speed system clock (C) to high-speed system clock (PLL mode) (N)
  • Page 181 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (6/6) (13)  STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B)  STOP mode (I) set while CPU is operating with high-speed system clock (C)

  • Page 182: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.6 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock (1/2) CPU Clock...
  • Page 183 RL78/I1A CHAPTER 5 CLOCK GENERATOR Table 5-4. Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change XT1 clock High-speed on- Oscillation of high-speed on-chip oscillator XT1 oscillation can be stopped (XTSTOP = chip oscillator...

  • Page 184: Time Required For Switchover Of Cpu Clock And System Clock

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.7 Time required for switchover of CPU clock and system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the high- speed on-chip oscillator clock and the high-speed system clock).

  • Page 185: Conditions Before Clock Oscillation Is Stopped

    RL78/I1A CHAPTER 5 CLOCK GENERATOR 5.6.8 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Before stopping the clock oscillation, check the conditions before the clock oscillation is stopped.

  • Page 186: Chapter 6 Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.

  • Page 187: Functions Of Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.

  • Page 188: Simultaneous Channel Operation Function

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (5) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
  • Page 189 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.

  • Page 190: Lin-Bus Supporting Function (Channel 7 Only)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.1.3 LIN-bus supporting function (channel 7 only) Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 and the count value of the timer is captured at the rising edge.

  • Page 191: Configuration Of Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer/counter register 0n (TCR0n) Register Timer data register 0n (TDR0n) Timer input...
  • Page 192 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2. Timer I/O Pins provided in Each Product Timer array unit I/O Pins of Each Product...
  • Page 193 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Entire Configuration of Timer Array Unit (Example: 38-pin Products) Timer clock select register 0 (TPS0) PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Prescaler Peripheral enable Selector Selector register 0...
  • Page 194 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit Interrupt signal from master channel Note 1 CK00 Timer controller Output TCLK Note 3 TO0n controller CK01 Output latch...
  • Page 195 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channel 5 of Timer Array Unit Interrupt signal from the master channel CK00 Timer controller Output TCLK Note TO05 controller CK01 Output latch Mode (Pxx) PMxx selection Interrupt...

  • Page 196: Timer/Counter Register 0N (Tcr0N)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer/counter register 0n (TCR0n) The TCR0n register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.

  • Page 197: Timer Data Register 0N (Tdr0N)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register 0n (TDR0n) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MD0n3 to MD0n0 bits of timer mode register 0n (TMR0n).

  • Page 198: Registers Controlling Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers.  Peripheral enable register 0 (PER0)  Timer clock select register 0 (TPS0)  Timer mode register 0n (TMR0n) ...

  • Page 199: Peripheral Enable Register 0 (Per0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 200: Timer Clock Select Register 0 (Tps0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register 0 (TPS0) The TPS0 register is a 16-bit register that is used to select two types or four types of operation clocks (CK00, CK01, CK02, CK03) that are commonly supplied to each channel. CK00 is selected by using bits 3 to 0 of the TPS0 register, and CK01 is selected by using bits 7 to 4 of the TPS0 register.
  • Page 201 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register 0 (TPS0) (1/2) Address: F01B6H, F01B7H After reset: 0000H Symbol TPS0 Selection of operation clock (CK0k) Note (k = 0, 1) = 2 MHz = 5 MHz f...
  • Page 202 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register 0 (TPS0) (2/2) Address: F01B6H, F01B7H After reset: 0000H Symbol TPS0 Note Selection of operation clock (CK02) = 2 MHz = 5 MHz f = 10 MHz f...

  • Page 203: Timer Mode Register 0N (Tmr0N)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register 0n (TMR0n) The TMR0n register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
  • Page 204 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register 0n (TMR0n) (1/4) Address: F0190H, F0191H (TMR00) ) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST (n = 2, 4, 6 ) ER0n Symbol TMR0n...
  • Page 205 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register 0n (TMR0n) (2/4) Address: F0190H, F0191H (TMR00) ) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST (n = 2, 4, 6 ) ER0n Symbol TMR0n...
  • Page 206 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register 0n (TMR0n) (3/4) Address: F0190H, F0191H (TMR00) ) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST (n = 2, 4, 6 ) ER0n Symbol TMR0n...
  • Page 207 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register 0n (TMR0n) (4/4) Address: F0190H, F0191H (TMR00) ) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMR0n MAST (n = 2, 4, 6 ) ER0n Symbol TMR0n...

  • Page 208: Timer Status Register 0N (Tsr0N)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register 0n (TSR0n) The TSR0n register indicates the overflow status of the counter of channel n. The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B).

  • Page 209: Timer Channel Enable Status Register 0 (Te0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register 0 (TE0) The TE0 register is used to enable or stop the timer operation of each channel. Each bit of the TE0 register corresponds to each bit of the timer channel start register 0 (TS0) and the timer channel stop register 0 (TT0).

  • Page 210: Timer Channel Start Register 0 (Ts0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register 0 (TS0) The TS0 register is a trigger register that is used to clear timer/counter register 0n (TCR0n) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is set to 1.

  • Page 211: Timer Channel Stop Register 0 (Tt0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register 0 (TT0) The TT0 register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is cleared to 0.

  • Page 212: Timer Input Select Register 0 (Tis0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 5 timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 213: Timer Output Enable Register 0 (Toe0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register 0 (TOE0) The TOE0 register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n).

  • Page 214: Timer Output Register 0 (To0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register 0 (TO0) The TO0 register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel.

  • Page 215: Timer Output Level Register 0 (Tol0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register 0 (TOL0) The TOL0 register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1).

  • Page 216: Timer Output Mode Register 0 (Tom0)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register 0 (TOM0) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.

  • Page 217: Input Switch Control Register (Isc)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to set whether to assign TI07 and INTP0 pins to P11/RxD0 pin. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 218: Noise Filter Enable Register 1 (Nfen1)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.

  • Page 219: Registers Controlling Port Functions Of Pins To Be Used For Timer I/O

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.3.15 Registers controlling port functions of pins to be used for timer I/O Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx) and port register (Pxx)). For details, see 4.3.1 Port mode registers (PMxx) and 4.3.2 Port registers (Pxx).

  • Page 220: Basic Rules Of Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
  • Page 221 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Example TAU0 Channel group 1 CK00 Channel 2: Master (Simultaneous channel operation function) Channel 3: Slave Channel group 2 (Simultaneous channel operation function) Channel 4: Master CK01 Channel 5: Slave * The operating clock of channel group 1 may be different from that of channel group 2.

  • Page 222: 8-Bit Timer Operation Function Overview (Only Channels 1 And 3)

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.4.2 8-bit timer operation function overview (only channels 1 and 3) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.

  • Page 223: Operation Of Counter

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n TCLK (TMR0n).
  • Page 224 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TI0n pin is selected (CCS0n = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TI0n pin and synchronizes...

  • Page 225: Start Timing Of Counter

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register 0n (TCR0n) becomes enabled to operation by setting of TS0n bit of timer channel start register 0 (TS0). Operations from count operation enabled state to timer count Register 0n (TCR0n) count start is shown in Table 6-6.

  • Page 226: Operation Of Counter

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the initial value until count clock generation.
  • Page 227 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register 0n (TCR0n) holds its initial value while operation is stopped (TE0n = 0). <2> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
  • Page 228 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until count clock generation.
  • Page 229 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation. <3> Rising edge of the TI0n input is detected.
  • Page 230 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit of timer channel start register 0 (TS0). <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.

  • Page 231: Channel Output (To0N Pin) Control

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TO0n pin) Control 6.6.1 TO0n pin output circuit configuration Figure 6-30. Output Circuit Configuration <5> TO0n register Interrupt signal of the master channel (INTTM0n) TO0n pin Interrupt signal of the slave channel...

  • Page 232: To0N Pin Output Setting

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TO0n pin output setting The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer operation start. Figure 6-31. Status Transition from Timer Output Setting to Operation Start...

  • Page 233: Cautions On Channel Output Operation

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TO0, TOE0, and TOL0 during timer operation Since the timer operations (operations of timer/counter register 0n (TCR0n) and timer data register 0n (TDR0n))
  • Page 234 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TO0n pin and output level after timer operation start The change in the output level of the TO0n pin when timer output register 0 (TO0) is written while timer output is disabled (TOE0n = 0), the initial level is changed, and then timer output is enabled (TOE0n = 1) before port output is enabled, is shown below.
  • Page 235 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output)) When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0 (TOL0) setting.
  • Page 236 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TO0n pin in slave channel output mode (TOM0n = 1) (a) When timer output level register 0 (TOL0) setting has been changed during timer operation When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TO0n pin change condition.
  • Page 237 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-35. Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTM0n Internal reset Master signal channel TO0n pin/ TO0n Toggle Toggle Internal set signal 1 clock delay INTTM0p Slave channel Internal reset signal...

  • Page 238: Collective Manipulation Of To0N Bit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TO0n bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register 0 (TS0). Therefore, the TO0n bit of all the channels can be manipulated collectively.

  • Page 239: Timer Interrupt And To0N Pin Output At Operation Start

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer interrupt and TO0n pin output at operation start In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to generate a timer interrupt at count start.

  • Page 240: Timer Input (Ti0N) Control

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TI0n) Control 6.7.1 TI0n input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller.

  • Page 241: Cautions On Channel Input Operation

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.

  • Page 242: Independent Channel Operation Function Of Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed intervals.
  • Page 243 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Block Diagram of Operation as Interval Timer/Square Wave Output CK01 Note Operation clock Timer counter Output CK00 TO0n pin register 0n (TCR0n) controller Interrupt Timer data Interrupt signal TS0n controller register 0n (TDR0n) (INTTM0n) Note When channels 1 and 3, the clock can be selected from CK00, CK01, CK02 and CK03.
  • Page 244 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register 0n (TMR0n) TMR0n Note CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
  • Page 245 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode)
  • Page 246 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 Power-on status.
  • Page 247 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TO0n pin output level Clears the TO0n bit to 0 after the value to stop be held is set to the port register.

  • Page 248: Operation As External Event Counter

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an interrupt.
  • Page 249 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Example of Basic Timing of Operation as External Event Counter TS0n TE0n TI0n TCR0n 0000H TDR0n 0003H 0002H INTTM0n 4 events 4 events 3 events Remarks 1. n: Channel number (n = 3, 5, 6, 7) The TI07 pin can be used for P11/RxD0 pin by setting bit 1 (ISC1) in the input switch control register (ISC) to 1.
  • Page 250 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register 0n (TMR0n) TMR0n Note CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0...
  • Page 251 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode).
  • Page 252 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.

  • Page 253: Operation As Input Pulse Interval Measurement

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as input pulse interval measurement The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured. In addition, the count value can be captured by using software operation (TS0n = 1) as a capture trigger while the TE0n bit is set to 1.
  • Page 254 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0) TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n 0000H INTTM0n Remarks 1. n: Channel number (n = 3, 5, 6, 7) The TI07 pin can be used for P11/RxD0 pin by setting bit 1 (ISC1) in the input switch control register (ISC) to 1.
  • Page 255 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Set Contents of Registers to Measure Input Pulse Interval (1/2) (a) Timer mode register 0n (TMR0n) TMR0n Note CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0...
  • Page 256 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Set Contents of Registers to Measure Input Pulse Interval (2/2) (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode. TOM0n Note TMR06: MASTER0n bit...
  • Page 257 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.

  • Page 258: Operation As Input Signal High-/Low-Level Width Measurement

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus and DMX512, read TI0n as RxD0 in the following descriptions. By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TI0n can be measured.
  • Page 259 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CK01 Note Operation clock Timer counter CK00 register 0n (TCR0n) TNFEN0n Timer data Interrupt Noise Edge Interrupt signal TI0n pin register 0n (TDR0n)
  • Page 260 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (1/2) (a) Timer mode register 0n (TMR0n) TMR0n Note CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1...
  • Page 261 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (2/2) (e) Timer output mode register 0 (TOM0) Bit n TOM0 0: Sets master channel output mode. TOM0n Note TMR06:...
  • Page 262 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 Power-on status.

  • Page 263: Operation As Delay Counter

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as delay counter It is possible to start counting down when the valid edge of the TI0n pin input is detected (an external event), and then generates INTTM0n (a timer interrupt) after any specified interval.
  • Page 264 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Example of Basic Timing of Operation as Delay Counter TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n INTTM0n Remarks 1. n: Channel number (n = 3, 5, 6, 7) The TI07 pin can be used for P11/RxD0 pin by setting bit 1 (ISC1) in the input switch control register (ISC) to 1.
  • Page 265 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register 0n (TMR0n) TMR0n Note CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 Operation mode of channel n...
  • Page 266 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode).
  • Page 267 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 Power-on status.

  • Page 268: Simultaneous Channel Operation Function Of Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the start trigger with software operation.
  • Page 269 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 TS0n Timer data Interrupt Interrupt signal register 0n (TDR0n) controller...
  • Page 270 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Example of Basic Timing of Operation as One-Shot Pulse Output Function Note 1 Note 2 Note 2 TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n Note 1 TS0p TE0p FFFFH...
  • Page 271 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register 0n (TMR0n) TMR0n CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
  • Page 272 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register 0p (TMR0p) TMR0p Note CKS0p1 CKS0p0 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 MD0p3...
  • Page 273 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable registers 0 Power-on status.
  • Page 274 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0p (slave) bits of timer channel start register 0 (TS0) are set to 1 at the same time.

  • Page 275: Operation As Pwm Function

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
  • Page 276 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 Timer data Interrupt Interrupt signal TS0n register 0n (TDR0n) controller (INTTM0n)
  • Page 277 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as PWM Function TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H channel TDR0p TO0p INTTM0p Remarks 1. n: Maste channel number (n = 0, 2, 4) p: Slave channel number (p = 3, 5, 6, where n <...
  • Page 278 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) TMR0n CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0...
  • Page 279 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register 0p (TMR0p) TMR0p Note CKS0p1 CKS0p0 CCS0p STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 MD0p3 MD0p2 MD0p1...
  • Page 280 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 Power-on status.
  • Page 281 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TS0n (master) and TS0p (slave) bits of timer...

  • Page 282: Operation As Multiple Pwm Output Function

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
  • Page 283 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs) Master channel (interval timer mode) CK01 Operation clock Timer counter register 0n (TCR0n) CK00 Timer data Interrupt Interrupt signal...
  • Page 284 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Basic Timing of Operation as Multiple PWM Output Function (Output Two Types of PWMs) TS0n TE0n FFFFH Master TCR0n channel 0000H TDR0n TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave 0000H...
  • Page 285 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Remarks 1. n: Maste channel number (n = 0, 2, 4) p: Slave channel number q: Slave channel number (p, q = 3, 5, 6, where n < p < q  6, and p and q are integers greater than n) 2.
  • Page 286 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) TMR0n CKS0n1 CKS0n0 CCS0n STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2...
  • Page 287 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (1/2) (a) Timer mode register 0p, 0q (TMR0p, TMR0q) TMR0p Note CKS0p1...
  • Page 288 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs) (2/2) (e) Timer output mode register 0 (TOM0) Bit q Bit p TOM0 1: Sets the slave channel output mode.
  • Page 289 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.
  • Page 290 RL78/I1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Hardware Status Operation (Sets the TOE0p and TOE0q (slave) bits to 1 only when start resuming operation.) The TS0n bit (master), and TS0p and TS0q (slave) bits of...

  • Page 291: Cautions When Using Timer Array Unit

    RL78/I1A CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output Depends on products, a pin is assigned a timer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status.

  • Page 292: Chapter 7 16-Bit Timers Kb0, Kb1, And Kb2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 16-bit timers KB0, KB1 and KB2 are timers that can generate PWM output which is suitable for power sources and lighting control. The number of channels of the 16-bit timers differs, depending on the product.
  • Page 293 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (7) Forced output stop function 1 (by interlocking with the comparator) Timer output can be fixed to Hi-Z, high, or low level directly (not via the CPU) and asynchronously with the operation clock f of the 16-bit timer KBn and KC0 circuit when a trigger source occurs (comparator 0 to 5 output).

  • Page 294: Configuration Of 16-Bit Timers Kb0, Kb1, And Kb2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.2 Configuration of 16-bit Timers KB0, KB1, and KB2 16-bit timers KB0, KB1, and KB2 include the following hardware. Table 7-1. Configuration of 16-bit Timers KB0, KB1, and KB2 Item Configuration...
  • Page 295 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-1 shows a block diagram. Figure 7-1. Block Diagram of 16-bit Timer KBn Timer clock select register 2 (TPS2) Peripheral enable TKB2EN TKB1EN TKB0EN register 2 (PER2) TPS212 TPS211 TPS210...

  • Page 296: 16-Bit Timer Kb Compare Registers N0 To N3 (Tkbcrn0 To Tkbcrn3)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.2.1 16-bit timer KB compare registers n0 to n3 (TKBCRn0 to TKBCRn3) TKBCRnm can be refreshed (writing the same value) and its value can be rewritten while the timer is counting (TKBCEn = 1).

  • Page 297: Registers Controlling 16-Bit Timers Kb0, Kb1, And Kb2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3 Registers Controlling 16-bit Timers KB0, KB1, and KB2 16-bit timers KB0, KB1, and KB2 are controlled by the following registers.  Peripheral enable register 2 (PER2)  Timer clock select register 2 (TPS2) ...

  • Page 298: Peripheral Enable Register 2 (Per2)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.1 Peripheral enable register 2 (PER2) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 299: Timer Clock Select Register 2 (Tps2)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.2 Timer clock select register 2 (TPS2) The TPS2 register is a 16-bit register that is used to select two types of operation clocks (CK20, CK21) that are commonly supplied to timers KB0, KB1, KB2, and KC0 from external prescaler. CK21 is selected by using bits 6 to 4 of the TPS2 register, and CK20 is selected by using bits 2 to 0.

  • Page 300: 16-Bit Timer Kb Operation Control Register N0 (Tkbctln0)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.3 16-bit timer KB operation control register n0 (TKBCTLn0) TKBCTLn0 is a register that controls the count operation and sets the count clock of 16-bit timer. TKBCTLn0 can be set by a 16-bit memory manipulation instruction.
  • Page 301 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-6. Format of 16-bit Timer KB Operation Control Register n0 (TKBCTLn0) (2/2) TKBSTSn1 TKBSTSn0 Selection of timer KBn count start trigger Does not use trigger input. External interrupt signal (INTP20)

  • Page 302: 16-Bit Timer Kb Operation Control Register N1 (Tkbctln1)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.4 16-bit timer KB operation control register n1 (TKBCTLn1) TKBCTLn1 is a register that controls the count operation and sets the count clock of 16-bit timer. TKBCTLn1 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 303: 16-Bit Timer Kb Output Control Register N0 (Tkbiocn0)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.5 16-bit timer KB output control register n0 (TKBIOCn0) TKBIOCn0 is a register that setting the default level/active level in 16-bit timer KBn output (TKBOnp). TKBIOCn0 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 304: 16-Bit Timer Kb Output Control Register N1 (Tkbiocn1)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.6 16-bit timer KB output control register n1 (TKBIOCn1) TKBIOCn1 is a register that controls disable/enable timer control in 16-bit timer KBn output (TKBOnp). TKBIOCn1 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 305: 16-Bit Timer Kb Flag Register N (Tkbflgn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.7 16-bit timer KB flag register n (TKBFLGn) TKBFLGn is a register with status flags for 16-bit timer KBn. TKBFLGn can be read by a 1-bit or 8-bit memory manipulation instruction.

  • Page 306: 16-Bit Timer Kb Trigger Register N (Tkbtrgn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.8 16-bit timer KB trigger register n (TKBTRGn) TKBTRGn is a trigger register used for batch overwriting of the compare register for 16-bit timer KBn. TKBTRGn can be written by a 1-bit or 8-bit memory manipulation instruction.

  • Page 307: 16-Bit Timer Kb Flag Clear Trigger Register N (Tkbclrn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.9 16-bit timer KB flag clear trigger register n (TKBCLRn) TKBCLRn is a register used to clear flags in the 16-bit timer KB flag register n (TKBFLGn). TKBCLRn can be written by a 1-bit or 8-bit memory manipulation instruction.

  • Page 308: 16-Bit Timer Kb Dithering Count Registers N0, N1 (Tkbdnrn0, Tkbdnrn1)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.10 16-bit timer KB dithering count registers n0, n1 (TKBDNRn0, TKBDNRn1) TKBDNRnp is a register that is used by the PWM dithering function for TKBOnp output. When the values in this register of the higher 4 bits are N (N = 0H to FH), the active period for N times during each 16- period cycle of PWM output is output to one count clock extended.

  • Page 309: 16-Bit Timer Kb Compare 1L & Dithering Count Register N0 (Tkbcrldn0)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.11 16-bit timer KB compare 1L & dithering count register n0 (TKBCRLDn0) TKBCRLDn0 is a register that stores the “lower 8 bits of TKBCRn1 register” values in its higher 8 bits and the “TKBDNRn0 register”...

  • Page 310: 16-Bit Timer Kb Smooth Start Initial Duty Registers N0, N1 (Tkbsirn0, Tkbsirn1)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.13 16-bit timer KB smooth start initial duty registers n0, n1 (TKBSIRn0, TKBSIRn1) TKBSIRnp is a register that sets the default duty for the PWM output smooth start function for TKBOnp output.

  • Page 311: 16-Bit Timer Kb Maximum Frequency Limit Setting Register N (Tkbmfrn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.15 16-bit timer KB maximum frequency limit setting register n (TKBMFRn) TKBMFRn is a register that sets the minimum period for the timer restart of external trigger. When the counter (TKBCNTn) value is smaller than this TKBMFRn value, if trigger input is detected, the trigger is held pending, and the counter (TKBCNTn) is cleared (restart) after counting to the value set to TKBMFRn.

  • Page 312: Peripheral Function Switch Register 0 (Pfsel0)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.16 Peripheral function switch register 0 (PFSEL0) PFSEL0 selects function setting I/O in peripheral function and 16-bit timers KB0, KB1, and KB2. Bits 0 and 1 use external interrupts INTP20 and INTP21 either for PWM control of 16-bit timers KB0, KB1, and KB2 or for clearing stop mode.

  • Page 313: Port Mode Register 20 (Pm20)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.3.17 Port mode register 20 (PM20) This register specifies input or output mode for port 20 in 1-bit units. When using the P200/TKBO00/INTP22, P201/TKBO01, P202/TKBO10/(INTP21), P203/TKBO11/TKCO02/(INTP20), P204/TKBO20/TKCO03, and P205/TKBO21/TKCO04/DALITxD4 pins for timer output, set PM200 to PM205 and the output latches of P200 to P205 to 0.

  • Page 314: Operation Of 16-Bit Timers Kb0, Kb1 And Kb2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4 Operation of 16-bit Timers KB0, KB1 and KB2 Operation specifications of 16-bit timers KB0, KB1 and KB2 described below.  Counter basic operation (See 7.4.1)  Default level and active level (See 7.4.2)
  • Page 315 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-21. Timer KB Operation Setting Example (Operation Start Flow) Start of setup Set bits TKB0EN to TKB2EN and start supply of clock to timer PER2 setting KB to be used.
  • Page 316 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-22. Timer KB Operation Setting Example (Operation Stop Flow) Start of timer stop process Timer count stops and timer KB output becomes fixed output at the TKBCEm  0 set default level.

  • Page 317: Counter Basic Operation

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.1 Counter basic operation (1) Count start operation In any mode, the 16-bit counter of timer KB starts its counting from initial value of FFFFH. It increments the counter from FFFFH to 0000H, 0001H, 0002H, 0003H and so on.
  • Page 318 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) TKBTOEnp switched from “0” to “1” When TKBTOEnp is changed from 0 to 1 before the value of counter TKBCNTn matches with the value of compare register TKBCRnp, while the timer counter is in operation, the timer output generated becomes the PWM waveform in accordance with the TKBTOLnp setting at the timing when it matches.
  • Page 319 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) TKBTOEnp switched from “1” to “0” (a) Basic timing TKBOnp is default level set by TKBTODnp after 1 f when TKBTOEnp is switched from “1” to “0”. KBKC Figure 7-27. Figure of Timing of Default and Active Level (TKBTOEn0 Switched from “1”...
  • Page 320 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (c) When the operation of TKBTOEnp is simultaneous with generation of timer count clock TKBOnp is set by the matching of TKBCNTn = TKBCRnm in case when the operation of TKBTOEnp is simultaneous with generation of timer count clock.

  • Page 321: Stop/Restart Operation

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.3 Stop/restart operation Stop and start of operation of 16-bit timer KB is available by controlling TKBCEn. 16-bit timer KB is reset and stop operation by changing TKBCEn from “1” to “0”.
  • Page 322 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Count operation start timing When TKBCEn is switched from “0” to “1” counting operation starts after the progress of the minimum 1 f to the KBKC maximum 1 f INTTMKBn is output at counting operation start timing.
  • Page 323 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 When TKBCEn is switched from “1” to “0” counting operation is stopped after the progress of minimum 1 f KBKC Before the generation of 1 f , INTTMKBn is not output even matching of TKBCNTn = TKBCRn0 being generated.

  • Page 324: Batch Overwrite Operation

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.4 Batch overwrite operation TMKB compare register np (TKBCRnp) for timer KB has, as shown in Figure 7-36, two stages. Therefore, its value does not become effective immediately even if any value is set to TKBCRnp by a program. The value set to TKBCRnp at any timing is transferred at once to buffer registers at the time when the counter starts running or when transfer trigger occurs, and it is actually used for any comparison operation.

  • Page 325: Standalone Mode (Period Controlled By Tkbcrn0)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.5 Standalone mode (period controlled by TKBCRn0) (1) Outline of functions In standalone operation mode, the period is defined by setting value of TKBCRn0, then TKBOn0 is generated by TKBCRn0 and TKBCRn1, and then TKBOn1 is generated by TKBCRn2 and TKBCRn3.
  • Page 326 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Outline of operation Figure 7-38 shows the timing sample for standalone mode. Figure 7-38. Timing Sample for Standalone Mode (Period Controlled by TKBCRn0) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) <1>...
  • Page 327 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) Operation of batch overwrite (at starting the counting operation) Compare register of the timers KB0, KB1 and KB2 have function which updates internal buffer register simultaneously at the starting of counter operation caused by count clock which is generated after overwriting “1” to TKBCEn bit.
  • Page 328 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) Batch overwrite function: Update buffer during counting operation Compare register of the timers KB0, KB1 and KB2 has a function which updates internal buffer register simultaneously at the next counter clear (TKBCNTn and TKBCRn0 matched), identifying the writing “1” to TKBRDTn bit as batch overwriting trigger.
  • Page 329 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-40. Batch Overwrite Function: Figure of the Timing of Buffer Updating During Counting Operation TKBCEn FFFFH a1 + 1 (TKBCRn0 + 1) a2 + 1 (TKBCRn3) TKBCNTn (TKBCRn2) (TKBCRn1) 0000H...
  • Page 330 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (5) Sample of register setting details at standalone mode (period controlled by TKBCRn0) bit No.   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0 Setting bit No.   TKBCTLn0 TKBMFEn...

  • Page 331: Standalone Mode (Period Controlled By External Trigger Input)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.6 Standalone mode (period controlled by external trigger input) (1) Outline of functions By standalone mode, period can be controlled not only by TKBCRn0 but also by external trigger input. Input signals selected by TKBSTSn1 and TKBSTSn0 bits of 16-bit timer KB operation control register are used to detect external trigger input (Timer restart function).
  • Page 332 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-41. Configuration of Standalone Mode (Period Controlled by External Trigger Input) Clear CK21 16-bit timer counter KBn External trigger Controller Trigger (TKBCNTn) CK20 Interrupt INTTMKBn controller TKBCRn0 Output TKBOn0 controller...
  • Page 333 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Batch overwrite function (period controlled by external trigger input, buffer updating during counting operation (TKBTSEn bit set to 1)) In standalone mode of period controlled by external trigger input, counter clear and compare register batch overwrite is implemented at the timing when external trigger input is detected after writing “1”...
  • Page 334 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-42. Batch Overwrite Function: Figure of Standalone for External Trigger Input Factor and the Timing of Buffer Updating During Counting Operation (TKBTSEn Bit Set to 1) TKBCEn External trigger FFFFH...
  • Page 335 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) Batch overwrite function (period controlled by external trigger input, buffer updating during counting operation (TKBTSEn bit clear to 0)) This is an example of the case where TKBTSEn bit in TKBCTLn0 register is set to “0” during standalone operation under the periodic control by external trigger input.
  • Page 336 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-43. Batch Overwrite Function: Figure of standalone for External Trigger Input Factor and the Timing of Buffer Updating during Counting Operation (TKBTSEn bit clear to 0) TKBCEn External trigger FFFFH...
  • Page 337 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) Sample of register setting details at standalone mode (period controlled by external trigger input)   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0   TKBMFEn TKBIRSn1 TKBIRSn0 TKBTSEn TKBSTSn1 TKBSTSn0 ...

  • Page 338: Simultaneous Start/Stop Mode

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.7 Simultaneous start/stop mode (1) Outline of functions Slave timer KBm can be start/stop simultaneously by synchronization with count start/stop of master timer KB when master/slave is configured using multiple KBn timers.
  • Page 339 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Operation mode combination available for simultaneous start/stop mode Shows the operation mode available for simultaneous start/stop mode. Master: Operation Mode TKBMDn1, TKBSTSn1, Setting TKBMDn0 TKBSTSn0 Available Standalone mode (period controlled by TKBCRn0)
  • Page 340 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) Simultaneous start/stop mode Master: Sample of register setting details at standalone mode (period controlled by TKBCRn0)   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0   TKBMFEn TKBIRSn1 TKBIRSn0...
  • Page 341 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) Simultaneous start/stop mode Slave: Sample of register setting details at standalone mode (period controlled by TKBCRn0)   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0   TKBMFEn TKBIRSn1 TKBIRSn0...
  • Page 342 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (5) Simultaneous start/stop mode Master: Sample of register setting details at standalone mode (period controlled by external trigger input)   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0   TKBMFEn...
  • Page 343 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (6) Simultaneous start/stop mode Slave: Sample of register setting details at standalone mode (period controlled by external trigger input)   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0   TKBMFEn...
  • Page 344 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (7) Configuration of simultaneous start/stop mode (period controlled by TKBCR00) Figure 7-44 shows configuration of simultaneous start/stop mode. Figure 7-44. Configuration of Simultaneous Start & Stop Mode (Period Controlled by TKBCR00)
  • Page 345 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (8) Outline of operation Figure 7-45 shows timing sample for simultaneous start & stop mode. Figure 7-45. Timing Sample for Simultaneous Start/Stop Mode (Period Controlled by TKBCR00) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) Master operation <2>...
  • Page 346 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 The following describes an operational example of simultaneous start/stop mode. The following descriptions are linked with <1> to <3> in Figure 7-45. <1> When the master TKBCE0 is set to 1, the master 16-bit timer counter KB0 (TKBCNT0) and the slave 16-bit timer counter KBm (TKBCNTm) change from FFFFH to 0000H upon synching with the count clock and they start upward counting.

  • Page 347: Synchronous Start/Clear Mode

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.8 Synchronous start/clear mode Slave timer KBm can be started and cleared simultaneously by synchronization with timings of start/stop of counting by KB0 Master timer, counter clearing and batch overwriting when master/slave is configured using multiple KBn timers.
  • Page 348 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Operation mode combination available for synchronous start/clear mode Shows the operation mode available for synchronous start/clear mode. Master: Operation Mode TKBMD01, TKBSTS01, Setting TKBMD00 TKBSTS00 Available Standalone mode (period controlled by TKBCR00)
  • Page 349 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Synchronous start/clear mode: List of register setting by master bit No.   TKBCTL00 TKBGTE01 TKBSSE01 TKBDIE01 TKBGTE00 TKBSSE00 TKBDIE00 Setting bit No.   TKBCTL00 TKBMFE0 TKBIRS01 TKBIRS00 TKBTSE0...
  • Page 350 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) Simultaneous start/clear mode: List of register setting by slave bit No.   TKBCTLm0 TKBGTEm1 TKBSSEm1 TKBDIEm1 TKBGTEm0 TKBSSEm0 TKBDIEm0 Setting bit No.   TKBCTLm0 TKBMFEm TKBIRSm1 TKBIRSm0 TKBTSEm...
  • Page 351 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) Configuration of synchronous start/clear mode (period controlled by master) Figure 7-46 shows configuration of synchronous start/clear mode. Figure 7-46. Configuration of Synchronous Start/Clear Mode (Period Controlled by Master) Master channel...
  • Page 352 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (5) Outline of operation Figure 7-47 shows timing sample for Synchronous start/clear mode. Figure 7-47. Timing Sample for Synchronous Start/Clear Mode (Period Controlled by Master) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) Master operation <4>...
  • Page 353 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 The following describes an operational example of synchronous start/clear mode. The following descriptions are linked with <1> to <4> in Figure 7-47. <1> When the master TKBCE0 is set to 1, the master 16-bit timer counter KB0 (TKBCNT0) and the slave 16-bit timer counter KBm (TKBCNTm) change from FFFFH to 0000H upon synching with the count clock and they start upward counting.
  • Page 354 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-48. Timing Sample for Synchronous Start/Clear Mode (Period Controlled by Master) (at Batch Overwrite) Master operation TKBCE0 FFFFH a1 + 1 (TKBCR00 + 1) (TKBCR03) a2 + 1 TKBCNT0 (TKBCR02)

  • Page 355: Interleave Pfc (Power Factor Correction) Output Mode

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.4.9 Interleave PFC (Power Factor Correction) output mode This is the mode that can generate a signal as interleave output that controls PFC circuit which regulates the harmonic current of the power source.
  • Page 356 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-49. Operation Outline of Basic Operation for Interleave PFC Mode (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn “H”...
  • Page 357 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Output condition of TKBOn1 at interleave PFC There are output conditions for TKBOn1 output which are controlled according to the table below. Condition Judgment Status 1 Judgment Status 2 Judgment Status 3...
  • Page 358 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-50. Figure of Timing of Interleave PFC Mode (Operation for Conditions No. 1 and No. 2) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0))
  • Page 359 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-51. Figure of Timing of Interleave PFC Mode (Below T/2s No. 3 and No. 4) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn "H"...
  • Page 360 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-52. Figure of Timing of Interleave PFC Mode (Operation for Condition No. 5) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn "H"...
  • Page 361 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-53. Figure of Timing of Interleave PFC Mode (Operation for Conditions No. 6) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn “H”...
  • Page 362 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-54. Figure of Timing of Interleave PFC Output Mode (Operation for Conditions No. 7) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn “H”...
  • Page 363 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-55. Figure of Timing of Interleave PFC Output Mode (Operation for Conditions No. 8 to 9) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn “H”...
  • Page 364 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-56. Figure of Timing of Interleave PFC Output Mode (Operation for Conditions No. 10 and No. 11) (at Default Value of Output Is Low Level (TKBTODnp = 0) and Active Level Is High Level (TKBTOLnp = 0)) TKBCEn “H”...
  • Page 365 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-57. Figure of Timing of Interleave PFC Output Mode (In Case When INTP21 Input Was Detected During TKBOn1 Output) TKBCEn "H" INTP20 INTP21 T(=previous TKBCNTn)/2 + 1 T(=previous TKBCNTn)/2 + 1...
  • Page 366 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-58. Figure of Timing of Interleave PFC Output Mode (Output of TKBOn1 Is at the Width of the Previous Output Width and Exceeds Period of Status Maintenance) TKBCEn “H” INTP20...
  • Page 367 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) List of register setting at interleave PFC output mode bit No.   TKBCTLn0 TKBGTEn1 TKBSSEn1 TKBDIEn1 TKBGTEn0 TKBSSEn0 TKBDIEn0 Setting bit No.   TKBCTLn0 TKBMFEn TKBIRSn1 TKBIRSn0 TKBTSEn...

  • Page 368: Option Function Of 16-Bit Timers Kb0, Kb1 And Kb2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5 Option Function of 16-bit Timers KB0, KB1 and KB2 Option function can be added to timers KB0, KB1 and KB2. The following table shows available option for each operation modes for timer KB0, KB1 and KB2.

  • Page 369: A/D Conversion Start Timing Signal Output Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.1 A/D conversion start timing signal output function An A/D conversion start timing signal output can be generated by setting the 16-bit timer KB trigger compare register n (TKBTGCRn). Thereby, the 16-bit timer KBn and A/D conversion start timing can be synchronized.
  • Page 370 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-60. A/D Conversion Start Timing Signal Output Function for Standalone Mode (Period Controlled by External Trigger Input) TKBCEn External T rigger FFFFH a + 1 TKBCRn0 + 1 TKBCRn3 TKBCNTn...

  • Page 371: Pwm Output Dithering Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.2 PWM output dithering function 16-bit timer KB is available for high resolution PWM output using PWM output dithering function. Having 16 periods of PWM period as standard, 16 times higher PWM output is available for average resolution through extension of active period by 1 count clock at n period (n = 0 to 15) during 16 periods.
  • Page 372 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-62. Figure of Waveform at Dithering Operation TKBCEn FFFFH a + 1 TKBCRn0 + 1 TKBCRn3 TKBCNTn TKBCRn2 TKBCRn1 0000H INTTMKBn (When TKBTOLn0=0) TKBOn0 TKBOn1 (When TKBTOLn0=1) TKBOn0 TKBOn1 Figure 7-63. Figure of Waveform at Dithering Operation...
  • Page 373 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-64. Figure of Waveform at Dithering Operation (When TKBCRn3 = TKBCRn0+1) TKBCEn FFFFH a + 1 TKBCRn0 + 1 TKBCRn3 TKBCNTn TKBCRn2 TKBCRn1 0000H INTTMKBn (When TKBTOLn0=0) TKBOn0 not : +1...
  • Page 374 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Available for operation mode This shows enable or disable status under each mode that is specified by TKBCTLn0 register (TKBSTSn1 and TKBSTSn0 bit) and TKBCTLn1 register (TKBMDn1 and TKBMDn0 bit).

  • Page 375: Pwm Output Smooth Start Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.3 PWM output smooth start function Timer KB0, KB1 and KB2 own PMW output smooth start function corresponding to rush current control and over- voltage prevention. PWM output smooth start function begins at timer start timing. PWM output smooth start function is initiated by the timer start timing.
  • Page 376 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Overwrite during the operation (TKBCEn = 1) of TKBSIRn0/TKBSIRn1/TKBSSRn0/TKBSSRn1 registers Overwrite during the operation (TKBCEn = 1) is available for TKBSIRn0/TKBSIRn1/TKBSSRn0/TKBSSRn1. TKBSIRn0/TKBSIRn1/TKBSSRn0/TKBSSRn1 own buffer and batch overwriting is available via writing “1” to TKBRDTn bit.
  • Page 377 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) To Combine PWM output smooth start function with PWM output dithering function PWM output dithering function is invalid during the execution of PWM output smooth start function (TKBSSFnp = 1).

  • Page 378: Pwm Output Gate Function (Without Combining With Pwm Output Smooth Start Function)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.4 PWM output gate function (without combining with PWM output smooth start function) With this function, during high-level period of 16-bit timer KC0 output (TKCO00 to TKCO05), PWM pulse is output from the output terminal of TKBOnp 16-bit timer KB0 to KB2.
  • Page 379 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Operation mode available for PMW output gate function Output gate function can be used under the following operational modes. Operation Mode TKBMDn1, TKBSTSn1, Setting Available TKBMDn0 TKBSTSn0 Standalone mode (period controlled by TKBCRn0)

  • Page 380: Pwm Output Gate Function (Combining With Pwm Output Smooth Start Function)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.5 PWM output gate function (combining with PWM output smooth start function) The functions PWM output gate and PWM output smooth start can be combined. When soft-start is also used at the same time, PWM pulse is generated from TKBOnp output pin of 16-bit timers KB0 to KB2 synching with the period of 16-bit timers KB0 to KB2 after detecting rising edge of timer KC0 output (TKCO00 to TKCO05) of 16-bit timer KC.
  • Page 381 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (1) Operation mode and additional function available for PMW output gate function Output gate function can be used under the following operational modes. Operation Mode TKBMDn1, TKBSTSn1, Setting Available TKBMDn0 TKBSTSn0...

  • Page 382: Maximum Frequency Limit Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.5.6 Maximum frequency limit function Timers KB0, KB1 and KB2 are a function that regulates the minimum period of the counter clear (maximum frequency) in the periodic control by external trigger or interleaved PFC output mode.
  • Page 383 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Operation Mode Available for Maximum Frequency Limit Function Operation Mode TKBMDn1, TKBSTSn1, Setting Available TKBMDn0 TKBSTSn0 Standalone mode (period controlled by TKBCRn0) × Standalone mode (period controlled by external trigger input)

  • Page 384: Forced Output Stop Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6 Forced Output Stop Function Forced output stop function is a function to protect power supply, etc. If any abnormal situation that occurs in a power circuit configured outside of a micro-computer leads to over-voltage of over-current, making voltage or current sense signal into INTP20/comparator can protect the circuit by maintaining the timer output high impedance or fixed output state without being intermediated by a CPU’s program control.

  • Page 385: Forced Output Stop Function 1 And 2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.1 Forced output stop function 1 and 2 There are two ways of controls in forced output stop function. Forced output stop function 1 can select fixed level output or high-impedance output, and forced output stop function 2 can only set fixed level output. Then the difference of the control method is shown.
  • Page 386 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Table 7-4. External Trigger Assignment List of Forced Output Stop Function 1 TKBO00 TKBO01 TKBO10 TKBO11 TKBO20 TKBO21       Comparator 0     ...

  • Page 387: Configuration Of Forced Output Stop Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.2 Configuration of forced output stop function Forced output stop function includes the following hardware. Table 7-6. Configuration of Forced Output Stop Function Item Configuration Control registers Peripheral enable register 2 (PER2)

  • Page 388: Registers Controlling Forced Output Stop Function

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.3 Registers controlling forced output stop function Forced output stop function is controlled by the following registers.  Peripheral enable register 2 (PER2)  Forced output stop function control register n0 (TKBPACTLn0) ...

  • Page 389: Forced Output Stop Function Control Registers N0, N1 (Tkbpactln0, Tkbpactln1)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.3.2 Forced output stop function control registers n0, n1 (TKBPACTLn0, TKBPACTLn1) TKBPACTLnp is a register that selects the signal to be used as the trigger to control the forced output stop function of the TKBOnp pin, and to select the pin for setting forced output stop mode.
  • Page 390 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-73. Format of Forced Output Stop Function Control Register 0p (TKBPACTL0p) (2/2) TKBPAHZS0p0 Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger.
  • Page 391 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-74. Format of Forced Output Stop Function Control Register 1p (TKBPACTL1p) (1/2) Address: F0670H (TKBPACTL10), F0672H (TKBPACTL11) After reset: 0000H Symbol TKBPACTL1p TKBPAFXS1p3 TKBPAFXS1p2 TKBPAFXS1p1 TKBPAFXS1p0 TKBPAFCM1p TKBPAHZS1p2 TKBPAHZS1p1 TKBPAHZS1p0 TKBPAHCM1p1 TKBPAHCM1p0 TKBPAMD1p1 TKBPAMD1p0...
  • Page 392 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-74. Format of Forced Output Stop Function Control Register 1p (TKBPACTL1p) (2/2) TKBPAHCM1p1 TKBPAHCM1p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when forced output stop function release trigger (TKBPAHTT1p) = 1 is written, regardless of the trigger signal level.
  • Page 393 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-75. Format of Forced Output Stop Function Control Register 2p (TKBPACTL2p) (1/2) Address: F06B0H (TKBPACTL20) , F06B2H (TKBPACTL21) After reset: 0000H Symbol TKBPACTL2p TKBPAFXS2p3 TKBPAFXS2p2 TKBPAFXS2p1 TKBPAFXS2p0 TKBPAFCM2p TKBPAHZS2p2 TKBPAHZS2p1 TKBPAHZS2p0 TKBPAHCM2p1 TKBPAHCM2p0 TKBPAMD2p1 TKBPAMD2p0...
  • Page 394 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 Figure 7-75. Format of Forced Output Stop Function Control Register 2p (TKBPACTL2p) (2/2) TKBPAHCM2p1 TKBPAHCM2p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when forced output stop function release trigger (TKBPAHTT2p) = 1 is written, regardless of the trigger signal level.

  • Page 395: Forced Output Stop Function Control Register N2 (Tkbpactln2)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.3.3 Forced output stop function control register n2 (TKBPACTLn2) TKBPACTLn2 is a register that enables or disables the forced output stop function of the TKBOnp pin. TKBPACTLn2 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 396: Forced Output Stop Function Flag Register (Tkbpaflgn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.3.4 Forced output stop function flag register (TKBPAFLGn) TKBPAFLGn is a register with status flags for forced output stop function of the TKBOnp pin. TKBPAFLGn can be read by a 1-bit or 8-bit memory manipulation instruction.

  • Page 397: Forced Output Stop Function 1 Start Trigger Register N (Tkbpahfsn)

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.6.3.5 Forced output stop function 1 start trigger register n (TKBPAHFSn) TKBPAHFSn is the start trigger register used by forced output stop function 1 of the TKBOnp pin. TKBPAHFSn can be written by a 1-bit or 8-bit memory manipulation instruction.

  • Page 398: Operation Of Forced Output Stop Function 1

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.7 Operation of Forced Output Stop Function 1 Timer output can be fixed to Hi-Z, high, or low level directly (not via the CPU) and asynchronously with the operation clock f of the 16-bit timer KBn and KC0 circuit when a trigger source occurs (comparator 0 to 5 output).

  • Page 399: Software Cancel Operation For Forced Output Stop Function 1

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.7.2 Software cancel operation for forced output stop function 1 The table below shows the start trigger (TKBPAHTSnp bit for TKBPAHFSn register) setting to start forced output stop function 1. Table 7-9. Operation of Start Trigger (TKBPAHTSnp Bit) of Forced Output Stop Function 1...

  • Page 400: Basic Operation Of Forced Output Stop Function 1

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.7.3 Basic operation of forced output stop function 1 This shows the operations of forced output function 1 with different setting of TKBPAHCMnp1 and TKBPAHCMnp0 registers. The trigger signal that initiates the forced output stop function 1 (forced output stop input 1) is an OR output of the trigger signal selected by TKBPAHZSnp0 to TKBPAHZSnp2 bits of forced output stop function control register np (TKBPACTLnp) and TKBPAHTSnp bit of the trigger register n (TKBPAHFSn) that initiates forced output stop function 1.
  • Page 401 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Forced output stop function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 0, 1 Figure 7-81. Forced Output Stop Function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 0, 1 “TKBPAHTTnp = 1” “TKBPAHTTnp = 1”...
  • Page 402 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (3) Forced output stop function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 1, 0 Figure 7-82. Forced Output Stop Function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 1, 0 “TKBPAHTTnp = 1” Count Period Overwrite...
  • Page 403 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (4) Forced output stop function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 1, 1 Figure 7-83. Forced Output Stop Function 1 at TKBPAHCMnp1, TKBPAHCMnp0 = 1, 1 “TKBPAHTTnp = 1” “TKBPAHTTnp = 1”...

  • Page 404: Operation Of Forced Output Stop Function 2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.8 Operation of Forced Output Stop Function 2 Timer output can be fixed to high or low level directly (not via the CPU) and asynchronously with the operation clock of the 16-bit timer KBn and KC0 circuit when a trigger source occurs (comparator 0 to 5 output, INTP20). The forced...

  • Page 405: Basic Operation Of Forced Output Stop Function 2

    RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 7.8.2 Basic operation of forced output stop function 2 This shows the operations of forced output function 2 with different setting of TKBPAFCMnp bits. The trigger signal that initiates the forced output stop function 2 (forced output stop input 2) is the trigger signal selected by TKBPAFXSnp0 to TKBPAFXSnp3 bits of forced output stop function control register np.
  • Page 406 RL78/I1A CHAPTER 7 16-BIT TIMERS KB0, KB1, AND KB2 (2) Forced output stop function 2 at TKBPAFCMnp0 = 1 Figure 7-85. Forced Output Stop Function 2 at TKBPAFCMnp0 = 1 Count Period (1 Period) Counter Timer KBn Output Forced Output...

  • Page 407: Chapter 8 16-Bit Timer Kc0

    CHAPTER 8 16-BIT TIMER KC0 8.1 Functions of 16-bit Timer KC0 16-bit timer KC0 is mounted onto all RL78/I1A microcontroller products. 16-bit timer KC0 is a timer with six outputs, enabling the generation of up to six PWM outputs. In addition, gate control can be implemented for up to six PWM outputs by interlocking with timers KB0, KB1, and KB2.
  • Page 408 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 Figure 8-1 shows a block diagram. Figure 8-1. Block Diagram of 16-bit Timer KC0 Timer clock select register 2 (TPS2) Peripheral enable register 2 (PER2) TKC0EN PRS212PRS211 PRS210 PRS202 PRS201 PRS200 KBKC Prescaler CK21...

  • Page 409: 16-Bit Timer Kc Compare Register 0 (Tkccr0)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.2.1 16-bit timer KC compare register 0 (TKCCR0) TKCCR0 is setting to period of timer KC. TKCCR0 can be refreshed (writing the same value) and its value can be rewritten while the timer is counting (TKCCE0 = 1).

  • Page 410: Registers Controlling 16-Bit Timer Kc0

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3 Registers Controlling 16-bit Timer KC0 16-bit timer KC0 is controlled by the following registers.  Peripheral enable register 2 (PER2)  Timer clock select register 2 (TPS2)  16-bit timer KC operation control register 0 (TKCCTL0) ...

  • Page 411: Peripheral Enable Register 2 (Per2)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.1 Peripheral enable register 2 (PER2) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 412: Timer Clock Select Register 2 (Tps2)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.2 Timer clock select register 2 (TPS2) The TPS2 register is a 16-bit register that is used to select two types of operation clocks (CK20, CK21) that are commonly supplied to timers KB0, KB1, KB2, and KC0 from external prescaler. CK21 is selected by using bits 6 to 4 of the TPS2 register, and CK20 is selected by using bits 2 to 0.

  • Page 413: 16-Bit Timer Kc Operation Control Register 0 (Tkcctl0)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.3 16-bit timer KC operation control register 0 (TKCCTL0) TKCCTL0 is a register that controls the count operation and sets the count clock of 16-bit timer. TKCCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 414: 16-Bit Timer Kc Output Control Register 00 (Tkcioc00)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.4 16-bit timer KC output control register 00 (TKCIOC00) TKCIOC00 is a register that setting default/active level of TKCO0m in 16-bit timer KC0 output. TKCIOC00 can be set by a 16-bit memory manipulation instruction.

  • Page 415: 16-Bit Timer Kc Output Control Register 01 (Tkcioc01)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.5 16-bit timer KC output control register 01 (TKCIOC01) TKCIOC01 is the register that sets the functionality of making 16-bit timer KC0 output as PWM output gate function of 16-bit timer KB and TKCO0p output.

  • Page 416: 16-Bit Timer Kc Output Flag Register 0 (Tkctof0)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.7 16-bit timer KC output flag register 0 (TKCTOF0) TKCTOF0 is the monitor flag register for TKCO0m among the 16-bit timer KC0 outputs. TKCTOF0 can be read by a 1-bit or 8-bit memory manipulation instruction.

  • Page 417: 16-Bit Timer Kc Trigger Register 0 (Tkctrg0)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.9 16-bit timer KC trigger register 0 (TKCTRG0) TKCTRG0 is a trigger register used for batch overwriting of the compare register for 16-bit timer KC0. TKCTRG0 can be written by a 1-bit or 8-bit memory manipulation instruction.

  • Page 418: Port Mode Registers 1, 20 (Pm1, Pm20)

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.3.10 Port mode registers 1, 20 (PM1, PM20) These registers specify input or output mode for port 1 or 20 in 1-bit units. When using the P10/TKCO00/INTP20/SO00/TxD0/SCLA0/(DALITxD4), P11/TKCO01/INTP21/SI00/RxD0/SDAA0/ (DALIRxD4)/(TI07)/(TxRx4), P12/(TKCO03)/SCK00, P203/TKCO02/TKBO11/(INTP20), P204/TKCO03/TKBO20, P205/ TKCO04/TKBO21/DALITxD4, and P206/TKCO05/DALIRxD4/TxRx4/INTP23 pins for timer output, set PM10 to PM12 and PM203 to PM206 and the output latches of P10 to P12 and P203 to P206 to 0.

  • Page 419: Operation Of 16-Bit Timer Kc0

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.4 Operation of 16-bit Timer KC0 Figure 8-14. Timer KC Operation Setting Example (Operation Start Flow) Start of setup (Set the operation of Set the operation of timer KB when using simultaneous start / stop mode function.
  • Page 420 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 Figure 8-15. Timer KC Operation Setting Example (Operation Stop Flow) Start of timer stop process Timer count stops and timer KC output becomes fixed output at the TKBCE0  0 set default level. (TKBCE0  0)

  • Page 421: Pwm Output Function

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.4.1 PWM output function 16-bit timer KC0 can output six PWM waveforms with same period and different duty values can be output. Duty can be set individually within range of 0% to 100% and the TKCO0m period and Duty can be calculated using the following formula.
  • Page 422 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 (1) Batch overwrite function: Update buffer at starting the counting operation Compare register of the timer KC0 have function which update internal buffer register simultaneously at the starting of counter operation caused by count clock which is generated after overwriting “1” to TKCCE0 bit. Batch overwrite is generated without writing “1”...
  • Page 423 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 (2) Batch overwrite function: Update buffer during counting operation Compare register of the timer KC0 has a function which update internal buffer register simultaneously at the next counter clear (TKCCNT0 and TKCCR0 matched), identifying the writing “1” to TKCRDT0 bit as batch overwriting trigger.

  • Page 424: Stop/Restart Operation

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.4.2 Stop/restart operation Stop and restart of operation of 16-bit timer KC0 will be available by controlling TKCCE0. (1) 16-bit timer KC0 will be reset and stop operation by changing TKCCE0 from “1” to “0”.
  • Page 425 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 Figure 8-22. Count Operation Start Timing KBKC When TKCCE0 is switched from “0” to “1”, counting operation will start after the progress of TKCCE0 the minimum 1 f to the maximum 1 f KBKC...

  • Page 426: Default Level And Active Level

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.4.3 Default level and active level Default level and active level settings are available for timer KC output by 16-bit timer KC output control register 00 (TKCIOC00). When TKCTOE0m is switched from “1” to “0”, default level is output for TKCO0m according to TKCTOD0m setting.
  • Page 427 RL78/I1A CHAPTER 8 16-BIT TIMER KC0 Figure 8-26. TKCTOE0m Switched from “1” to “0” KBKC TKCO0m will be default level set by TKCTOD0m after 1 f time when TKCTOE0m is switched KBKC from “1” to “0”. TKCTOE0m TKCCNT0 00aa 00ab...

  • Page 428: Simultaneous Start & Stop Mode

    RL78/I1A CHAPTER 8 16-BIT TIMER KC0 8.4.4 Simultaneous start & stop mode Slave timer KC0 can be start/stop simultaneously by synchronization with count start/stop of master timer KB0 when master/slave is configured using 16-bit timer KB0/KC0. Select “Standalone Operation Mode (TKBMDn1, TKBMDn0 = 0, 0)” for master and “Simultaneous Start & Stop Mode (TKCMD0 = 1)”...

  • Page 429: Chapter 9 Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK CHAPTER 9 REAL-TIME CLOCK 9.1 Functions of Real-time Clock The real-time clock has the following features.  Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
  • Page 430 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Figure 9-1. Block Diagram of Real-time Clock Real-time clock control register 1 Real-time clock control register 0 Operation speed mode WUTMM WALE WALIE WAFG RIFG RWST RWAIT RTCE RCLOE1 AMPM control register (OSMC) RTC1HZ Alarm week...

  • Page 431: Registers Controlling Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0) • Subsystem clock supply mode control register (OSMC) • Real-time clock control register 0 (RTCC0) •...

  • Page 432: Peripheral Enable Register 0 (Per0)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 433: Subsystem Clock Supply Mode Control Register (Osmc)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the real-time clock count clock (f In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
  • Page 434 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Figure 9-4. Format of Real-time Clock Control Register 0 (RTCC0) Address: FFF9DH After reset: 00H Symbol <7> <5> RTCC0 RTCE RCLOE1 AMPM RTCE Real-time clock operation control Stops counter operation. Starts counter operation. RCLOE1 RTC1HZ pin output control Disables output of the RTC1HZ pin (1 Hz).

  • Page 435: Real-Time Clock Control Register 1 (Rtcc1)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 436 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Figure 9-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RWST Wait status flag of real-time clock Counter is operating. Mode to read or write counter value This status flag indicates whether the setting of the RWAIT bit is valid.

  • Page 437: Second Count Register (Sec)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows.

  • Page 438: Hour Count Register (Hour)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours.
  • Page 439 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Table 9-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 9-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1)

  • Page 440: Day Count Register (Day)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows.

  • Page 441: Week Count Register (Week)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.

  • Page 442: Month Count Register (Month)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.

  • Page 443: Watch Error Correction Register (Subcud)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16-bit) to the second count register (SEC) (reference value: 7FFFH).

  • Page 444: Alarm Minute Register (Alarmwm)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.

  • Page 445: Port Mode Register 3 (Pm3)

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm 12-Hour Display 24-Hour Display Sunday Friday Hour Hour Minute Minute Hour Hour Minute Minute Monday Tuesday Saturday Thursday Wednesday Every day, 0:00 a.m. Every day, 1:30 a.m.

  • Page 446: Real-Time Clock Operation

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4 Real-time Clock Operation 9.4.1 Starting operation of real-time clock Figure 9-19. Procedure for Starting Operation of Real-time Clock Start Note 1 RTCEN = 1 Supplies input clock. RTCE = 0 Stops counter operation. Setting WUTMMCK0...

  • Page 447: Shifting To Halt/Stop Mode After Starting Operation

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the INTRTC interrupt has occurred.

  • Page 448: Reading/Writing Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 9-21. Procedure for Reading Real-time Clock Start Stops SEC to YEAR counters.
  • Page 449 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Figure 9-22. Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register.

  • Page 450: Setting Alarm Of Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 9-23. Alarm processing Procedure Start Match operation of alarm is invalid. WALE = 0 alarm match interrupts is valid.

  • Page 451: Hz Output Of Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4.5 1 Hz output of real-time clock Figure 9-24. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Setting port Sets P30 = 0 and PM30 = 0. RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz).

  • Page 452: Example Of Watch Error Correction Of Real-Time Clock

    RL78/I1A CHAPTER 9 REAL-TIME CLOCK 9.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16-bit) is calculated by using the following expression.
  • Page 453 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz – 131.2 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H).
  • Page 454 RL78/I1A CHAPTER 9 REAL-TIME CLOCK R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...
  • Page 455 RL78/I1A CHAPTER 9 REAL-TIME CLOCK Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H).
  • Page 456 RL78/I1A CHAPTER 9 REAL-TIME CLOCK R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 457: Chapter 10 12-Bit Interval Timer

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER CHAPTER 10 12-BIT INTERVAL TIMER 10.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode.

  • Page 458: Registers Controlling 12-Bit Interval Timer

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER 10.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Subsystem clock supply mode control register (OSMC) • Interval timer control register (ITMC) 10.3.1 Peripheral enable register 0 (PER0)

  • Page 459: Subsystem Clock Supply Mode Control Register (Osmc)

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER 10.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer or real-time clock operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.

  • Page 460: Interval Timer Control Register (Itmc)

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER 10.3.3 Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction.

  • Page 461: 12-Bit Interval Timer Operation

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER 10.4 12-bit Interval Timer Operation 10.4.1 12-bit interval timer operation timing The count value specified for the ITMCMP11 to ITMCMP0 bits is used as an interval to operate a 12-bit interval timer that repeatedly generates interrupt requests (INTIT).

  • Page 462: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From Halt/Stop

    RL78/I1A CHAPTER 10 12-BIT INTERVAL TIMER 10.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.

  • Page 463: Chapter 11 Watchdog Timer

    RL78/I1A CHAPTER 11 WATCHDOG TIMER CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (f The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
  • Page 464 RL78/I1A CHAPTER 11 WATCHDOG TIMER Figure 11-1. Block Diagram of Watchdog Timer WDTINT of option Interval time controller Interval time interrupt  byte (000C0H) (Count value overflow time 3/4 + 1/2 f WDCS2 to WDCS0 of option byte (000C0H) Internal...

  • Page 465: Register Controlling Watchdog Timer

    RL78/I1A CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 11.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.

  • Page 466: Operation Of Watchdog Timer

    RL78/I1A CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H).  Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 27).

  • Page 467: Setting Overflow Time Of Watchdog Timer

    RL78/I1A CHAPTER 11 WATCHDOG TIMER 11.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...
  • Page 468 RL78/I1A CHAPTER 11 WATCHDOG TIMER The window open period can be set is as follows. Table 11-4. Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Period of Watchdog Timer Setting prohibited Note 100% <R> Note When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to...

  • Page 469: Setting Watchdog Timer Interval Interrupt

    RL78/I1A CHAPTER 11 WATCHDOG TIMER 11.4.4 Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% + 1/2f of the overflow time is reached.

  • Page 470: Chapter 12 A/D Converter

    RL78/I1A CHAPTER 12 A/D CONVERTER CHAPTER 12 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. 20-pin 30-pin, 38-pin Analog input channels 6 ch 11 ch (ANI0 to ANI2, ANI4, ANI5, ANI8) (ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19) Caution Most of the following descriptions in this chapter use the 38-pin as an example.
  • Page 471 RL78/I1A CHAPTER 12 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger mode Software trigger Conversion is started by software. Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger. Hardware trigger wait mode...
  • Page 472 RL78/I1A CHAPTER 12 A/D CONVERTER R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 473: Configuration Of A/D Converter

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI2, ANI4 to ANI7 and ANI16 to ANI19 pins These are the analog input pins of the eleven channels of the A/D converter. They input analog signals to be converted into digital signals.
  • Page 474 RL78/I1A CHAPTER 12 A/D CONVERTER (6) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).

  • Page 475: Registers Controlling A/D Converter

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers.  Peripheral enable register 0 (PER0)  A/D converter mode register 0 (ADM0)  A/D converter mode register 1 (ADM1)  A/D converter mode register 2 (ADM2) ...

  • Page 476: Peripheral Enable Register 0 (Per0)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 477: A/D Converter Mode Register 0 (Adm0)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 478 RL78/I1A CHAPTER 12 A/D CONVERTER Table 12-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Table 12-2. Setting and Clearing Conditions for ADCS Bit A/D Conversion Mode...
  • Page 479 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Note 2 Conversion start time Conversion Conversion Conversion Conversion operation standby stopped standby Software ADCS Note 1...
  • Page 480 RL78/I1A CHAPTER 12 A/D CONVERTER Cautions 3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion stopped/conversion standby status). 4. To complete A/D conversion, specify at least the following time as the hardware trigger interval:...
  • Page 481 RL78/I1A CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (1/4) (1) When there is no A/D power supply stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode Conversion...
  • Page 482 RL78/I1A CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (2/4) (2) When there is no A/D power supply stabilization wait time Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode Conversion...
  • Page 483 RL78/I1A CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (3/4) (3) When there is A/D power supply stabilization wait time Note 1 Normal mode 1, 2 (hardware trigger wait mode A/D Converter Mode Register 0 Mode Conversion Number of...
  • Page 484 RL78/I1A CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (4/4) (4) When there is A/D power supply stabilization wait time Note 1 Low-voltage mode 1, 2 (hardware trigger wait mode A/D Converter Mode Register 0 Mode Conversion Number of...
  • Page 485 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) 1 is written to ADCS or ADS is rewritten. ADCS Sampling timing INTAD Sampling Successive conversion Sampling Successive conversion Conversion start...

  • Page 486: A/D Converter Mode Register 1 (Adm1)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 487: A/D Converter Mode Register 2 (Adm2)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or  side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode.
  • Page 488 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP ADRCK Checking the upper limit and lower limit conversion result values The interrupt signal (INTAD) is output when the ADLL register ...

  • Page 489: 10-Bit A/D Conversion Result Register (Adcr)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of...

  • Page 490: Analog Input Channel Specification Register (Ads)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 491 RL78/I1A CHAPTER 12 A/D CONVERTER Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Set a channel to be set the analog input by ADPC and PMCx registers in the input mode by using port mode registers 0, 2, 12, and 14 (PM0, PM2, PM12, PM14).

  • Page 492: Conversion Result Comparison Upper Limit Setting Register (Adul)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12-8).

  • Page 493: A/D Test Register (Adtes)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or  side reference voltage for the converter, an analog input channel (ANIxx), the temperature sensor output voltage, the internal reference voltage (1.45 V), or PGAOUT as the target for A/D conversion.

  • Page 494: Registers Controlling Port Function Of Analog Input Pins

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.3.11 Registers controlling port function of analog input pins Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control registers (PMCxx), and A/D port configuration register (ADPC)). For details, see 4.3.1...

  • Page 495: A/D Converter Conversion Operations

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
  • Page 496 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-15. Conversion Operation of A/D Converter (Software Trigger Mode) ← ADCS 1 or ADS rewrite Conversion time Sampling time A/D converter SAR clear Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.

  • Page 497: Input Voltage And Conversion Results

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI2, ANI4 to ANI7, ANI16 to ANI19, PGAOUT) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.

  • Page 498: A/D Converter Operation Modes

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 12.7 A/D Converter Setup Flowchart. 12.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...

  • Page 499: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 500: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 501: Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 502: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 503: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 504: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 505: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 506: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.

  • Page 507: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.

  • Page 508: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 509: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.

  • Page 510: A/D Converter Setup Flowchart

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 511: Setting Up Software Trigger Mode

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7.1 Setting up software trigger mode Figure 12-29. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input.

  • Page 512: Setting Up Hardware Trigger No-Wait Mode

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7.2 Setting up hardware trigger no-wait mode Figure 12-30. Setting up Hardware Trigger No-wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.

  • Page 513: Setting Up Hardware Trigger Wait Mode

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7.3 Setting up hardware trigger wait mode Figure 12-31. Setting up Hardware Trigger Wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.

  • Page 514: Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and one-shot conversion mode) Figure 12-32. Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected Start of setup...

  • Page 515: Setting Up Test Mode

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.7.5 Setting up test mode Figure 12-33. Setting up Test Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.  ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.

  • Page 516: Snooze Mode Function

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode function, A/D conversion can be performed without operating the CPU.
  • Page 517 RL78/I1A CHAPTER 12 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
  • Page 518 RL78/I1A CHAPTER 12 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
  • Page 519 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-37. Flowchart for Setting up SNOOZE Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.

  • Page 520: How To Read A/D Converter Characteristics Table

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 521 RL78/I1A CHAPTER 12 A/D CONVERTER (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero- scale error and full-scale error are 0.

  • Page 522: Cautions For A/D Converter

    RL78/I1A CHAPTER 12 A/D CONVERTER 12.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
  • Page 523 RL78/I1A CHAPTER 12 A/D CONVERTER Figure 12-44. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV REFP or equal to or lower than AV and V may enter, clamp with REFM a diode with a small V value (0.3 V or lower).
  • Page 524 RL78/I1A CHAPTER 12 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite.
  • Page 525 RL78/I1A CHAPTER 12 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-46. Internal Equivalent Circuit of ANIn Pin ANIn Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pins R1 [k]...

  • Page 526: Chapter 13 Programmable Gain Amplifier

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER A circuit of programmable gain amplifier is incorporated in RL78/I1A. The number of analog input channels corresponding to programmable gain amplifier differs, depending on the product. 20-pin 30-pin, 38-pin...

  • Page 527: Registers Used In Operational Amplifier

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER Figure 13-1. Block Diagram of Operational Amplifier Operational amplifier ANI2/CMP0P/P22 ANI4/CMP1P/P24 To A/D converter ANI5/CMP2P/P25 (analog input channel: PGAOUT) ANI6/CMP3P/P26 ANI7/CMP4P/P27 ANI16/CMP5P/RxD1/P03 ANI18/(CMP3P)/CMPCOM/P147 PGAINS2 PGAINS1 PGAINS0 PGAEN PGAVG1PGAVG0 Programmable gain amplifier Programmable gain amplifier...

  • Page 528: Peripheral Enable Register 2 (Per2)

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.1 Peripheral enable register 2 (PER2) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 529: Programmable Gain Amplifier Control Register

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.2 Programmable gain amplifier control register (PGACTL) PGACTL controls the operations of programmable gain amplifier. The PGACTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 530: Programmable Gain Amplifier Input Channel Select Register

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.3 Programmable gain amplifier input channel select register (PGAINS) This register selects the input channel for the programmable gain amplifier. The PGAINS register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 531: A/D Port Configuration Register (Adpc)

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.4 A/D port configuration register (ADPC) This register switches the ANI0/P20, ANI1/P21, ANI2/CMP0P/P22, ANI4/CMP1P/P24 to ANI7/CMP4P/P27 pins, and PGAOUT pin (internal pin) to digital I/O of port or analog input of A/D converter, programmable gain amplifier, or comparator.

  • Page 532: Port Mode Control Registers 0, 14 (Pmc0, Pmc14)

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.5 Port mode control registers 0, 14 (PMC0, PMC14) These registers are used to set the digital I/O/analog input of port 0 or 14 in 1-bit units. To use the ANI16/CMP5P/RxD1/P03 or ANI18/CMPCOM/P147 pin as an analog input pin, set the PMC03 or PMC147 bit to 1.

  • Page 533: Port Mode Registers 0, 2, 14 (Pm0, Pm2, Pm14)

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.6 Port mode registers 0, 2, 14 (PM0, PM2, PM14) When using ANI2/CMP0P/P22, ANI4/CMP1P/P24 ANI7/CMP4P/P27, ANI16/CMP5P/RxD1/P03, ANI18/CMPCOM/P147 pin for an analog input port, set the PM22, PM24 to PM27, PM03, or PM147 bit to 1. The output latches of P22, P24 to P27, P03, and P147 at this time may be 0 or 1.
  • Page 534 RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER The functions of the ANI2/CMP0P/P22, ANI4/CMP1P/P24 to ANI7/CMP4P/P27 pins, and PGAOUT/P23 pin (internal pin) can be selected by using the A/D port configuration register (ADPC) and PM2 register. Table 13-2. Setting Functions of ANI2/CMP0P/P22, ANI4/CMP1P/P24 to ANI7/CMP4P/P27 Pins,...

  • Page 535: Comparator And Pga Internal Reference Voltage Control Register (Cvrctl)

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.3.7 Comparator and PGA internal reference voltage control register (CVRCTL) This register is used to control the internal reference voltage of the comparator, and to select the sources of the internal reference voltage and the comparator/GND of programmable gain amplifier.

  • Page 536: Operation Of Programmable Gain Amplifier

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.4 Operation of Programmable Gain Amplifier The analog voltage input from the CMP0P to CMP5P and CMPCOM pins is amplified within the microcontroller. The gain can be selected from four types (4, 8, 16, and 32).

  • Page 537: Setting Procedure Of Programmable Gain Amplifier

    RL78/I1A CHAPTER 13 PROGRAMMABLE GAIN AMPLIFIER 13.5 Setting Procedure of Programmable Gain Amplifier Figure 13-9. Operation Setting Flow Chart of Programmable Gain Amplifier (PGA) (Using PGA Output as Analog Input of A/D Converter) PGA setting  PGACMPEN bit of PER2 is set.

  • Page 538: Chapter 14 Comparator

    RL78/I1A CHAPTER 14 COMPARATOR CHAPTER 14 COMPARATOR The number of channels of the comparator differs, depending on the product. 20-pin 30-pin, 38-pin Channels (analog 4 ch 6 ch input channels) (ANI2/CMP0P, ANI4/CMP1P, ANI5/CMP2P, (ANI2/CMP0P, ANI4/CMP1P to ANI7/CMP4P, ANI18/(CMP3P)/(CMPCOM)) ANI16/CMP5P, P147/CMPCOM/ANI18)) Caution Most of the following descriptions in this chapter use the 38-pin products as an example.
  • Page 539 RL78/I1A CHAPTER 14 COMPARATOR Figure 14-1. Block Diagram of Comparator Peripheral function switch register 0 (PFSEL0) PNFEN Comparator rising edge enable register (CMPEGP0) External interrupt INTP20, INTP21 control block STEN1 STEN0 Comparator falling edge enable register (CMPEGN0) CEGP7 CEGN7 CEGP6...

  • Page 540: Configuration Of Comparator

    RL78/I1A CHAPTER 14 COMPARATOR 14.2 Configuration of Comparator The comparator includes the following hardware. Table 14-1. Configuration of Comparator Item Configuration Comparator main unit Comparator MAX. 6 ch Programmable gain amplifier input Internal reference voltage 3 and external CAPCOM input...

  • Page 541: Peripheral Enable Register 2 (Per2)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.1 Peripheral enable register 2 (PER2) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
  • Page 542 RL78/I1A CHAPTER 14 COMPARATOR Figure 14-3. Format of Comparator n Control Register (CnCTL) (2/2) Address: F0552H (C0CTL), F0553H (C1CTL), F0554H (C2CTL) After reset: 00H F0555H (C3CTL), F0556H (C4CTL), F0557H (C5CTL) Symbol <7> <1> CnCTL CMPnEN CnDFS1 CnDFS0 CnMODSEL1 CnMODSEL0 CnOE...

  • Page 543: Comparator And Pga Internal Reference Voltage Control Register (Cvrctl)

    RL78/I1A CHAPTER 14 COMPARATOR 4.3.3 Comparator and PGA internal reference voltage control register (CVRCTL) This register is used to control the internal reference voltage of the comparator, and to select the sources of the internal reference voltage and the comparator/GND of programmable gain amplifier.

  • Page 544: Comparator Internal Reference Voltage Select Register M (Cmrvm)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.4 Comparator internal reference voltage select register m (CmRVM) This register is used to set the internal reference voltage level of comparator. The CmRVM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 545: Register 0 (Cmpegn0)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.5 Comparator rising edge enable register 0 (CMPEGP0), comparator falling edge enable register 0 (CMPEGN0) These registers are used to set the valid edges of comparator n detection interrupt signal (INTCMPn) and external interrupts (INTP20, INTP21).

  • Page 546: Comparator Output Monitor Register (Cmpmon)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.6 Comparator output monitor register (CMPMON) This register indicates the level of the timer forced output stop request signal, which is a comparator output signal. The CMPMON register can only be read by a 1-bit or 8-bit memory manipulation instruction.

  • Page 547: Window Comparator Function Setting Register (Cmpwdc)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.7 Window comparator function setting register (CMPWDC) The window comparator function selects a single input voltage for two comparators so that the input voltage can be compared to two reference voltages. The CMPWDC register controls the selection of input signals when using this window comparator function.

  • Page 548: Comparator Input Switch Control Register (Cmpsel) (20-Pin Products Only)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.8 Comparator input switch control register (CMPSEL) (20-pin products only) This register is used to set the input signal for comparator 3. The CMPSEL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 549: A/D Port Configuration Register (Adpc)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.10 A/D port configuration register (ADPC) This register switches the ANI0/P20, ANI1/P21, ANI2/CMP0P/P22, and ANI4/CMP1P/P24 to ANI7/CMP4P/P27 pins to digital I/O of port or analog input of A/D converter, programmable gain amplifier, or comparator. When using the programmable gain amplifier or comparator, use the ADPC register to select the CMP0P/ANI2/P22 and CMP1P/ANI4/P24 to CMP4P/ANI7/P27 pins as analog inputs.

  • Page 550: Peripheral Function Switch Register 0 (Pfsel0)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.11 Peripheral function switch register 0 (PFSEL0) Bits 0 and 1 of the PFSEL0 register use external interrupts INTP20 and INTP21 either for PWM control of 16-bit timers KB0, KB1, and KB2 or for clearing STOP mode.
  • Page 551 RL78/I1A CHAPTER 14 COMPARATOR Notes 1. When the interrupt for CMP0 and CMP2 is used, adopt a function used with the interrupt input signal. When the CMP0 and CMP2 are used as a trigger of the timer KB forced output stop function, set CMPnSTEN = 1.

  • Page 552: Port Mode Control Registers 0, 14 (Pmc0, Pmc14)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.12 Port mode control registers 0, 14 (PMC0, PMC14) These registers are used to set the digital I/O/analog input of port 0 or 14 in 1-bit units. To use the CMP5P/ANI16/RxD1/P03 or CMPCOM/ANI18/P147 pin as an analog input pin, set the PMC03 or PMC147 bit to 1.

  • Page 553: Port Mode Registers 0, 2, 14 (Pm0, Pm2, Pm14)

    RL78/I1A CHAPTER 14 COMPARATOR 14.3.13 Port mode registers 0, 2, 14 (PM0, PM2, PM14) When using CMP0P/ANI2/P22, CMP1P/ANI4/P24 CMP4P/ANI7/P27, CMP5P/ANI16/RxD1/P03, CMPCOM/ANI18/P147 pin for an analog input port, set the PM22, PM24 to PM27, PM03, or PM147 bit to 1. The output latches of P22, P24 to P27, P03, and P147 at this time may be 0 or 1.
  • Page 554 RL78/I1A CHAPTER 14 COMPARATOR The functions of the CMP0P/ANI2/P22 and CMP1P/ANI4/P24 to CMP4P/ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC) and PM2 register. Table 14-2. Setting Functions of CMP0P/ANI2/P22 and CMP1P/ANI4/P24 to CMP4P/ANI7/P27 Pins ADPC...

  • Page 555: Setting Procedure Of Comparator

    RL78/I1A CHAPTER 14 COMPARATOR 14.4 Setting Procedure of Comparator Figure 14-15. Operation Setting Flow Chart 1 of Comparator (CMP) (Using Timer Forced Output Stop Request Signal by INTCMPn, CMPn) Start Setting of the forced  Setting of the forced output stop function output stop function See 7.6 Forced Output Stop Function.
  • Page 556 RL78/I1A CHAPTER 14 COMPARATOR Figure 14-16. Operation Setting Flow Chart 2 of Comparator (CMP) (Using Timer Forced Output Stop Request Signal by INTPm, INTPm (Using Edge Circuit only)) Start  Setting of the forced output stop function Forced output stop setting See 7.6 Forced Output Stop Function.
  • Page 557 RL78/I1A CHAPTER 14 COMPARATOR Figure 14-17. Operation End Flow Chart of Comparator Operation end process start  Timer KB operation stop Timer KB stop setting Clear TKBPACEnp to 0  Forced output stop operation stop CMPEGP0, CMPEGN0 setting  Setting of comparator’s rising/descent operation...

  • Page 558: Caution For Using Timer Kb Simultaneous Operation Function

    RL78/I1A CHAPTER 14 COMPARATOR 14.5 Caution for Using Timer KB Simultaneous Operation Function In addition to their use as an external interrupt input, the INTP2m pin output and the comparator output signal can be used as a trigger for functions that operate simultaneously with timer KB, such as the forced output stop function and timer restart function.
  • Page 559 RL78/I1A CHAPTER 14 COMPARATOR Table 14-5. Relationship of Comparator 0 and 2 Functions, Register Settings, and Active Signal Width Peripheral Enable Edge Setting Necessary Active Signal width to Operate Each Function Function Register Setting Registers Interrupt Forced Output Stop Timer Restart ...
  • Page 560 RL78/I1A CHAPTER 14 COMPARATOR Table 14-6. Relationship of Comparator 1, 3, 4, and 5 Functions, Register Settings, and Active Signal Width Peripheral Enable Edge Setting Necessary Active Signal Width to Operate Each Function Function Register Setting Registers Interrupt Forced Output Stop Timer Restart ...

  • Page 561: Chapter 15 Serial Array Unit 0

    Serial array unit 0 has up to four serial channels. Each channel can achieve 3-wire serial (CSI) and UART communication. Function assignment of each channel supported by the RL78/I1A is as shown below.  20-pin products Channel Used as CSI Used as UART ...

  • Page 562: Functions Of Serial Array Unit 0

    CHAPTER 15 SERIAL ARRAY UNIT 0 15.1 Functions of Serial Array Unit 0 Each serial interface supported by the RL78/I1A has the following features. 15.1.1 3-wire serial I/O (CSI00) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.

  • Page 563: Uart (Uart0, Uart1)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.1.2 UART (UART0, UART1) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.

  • Page 564: Configuration Of Serial Array Unit 0

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.2 Configuration of Serial Array Unit 0 The serial array unit 0 includes the following hardware. Table 15-1. Configuration of Serial Array Unit 0 Item Configuration Note 1 Shift register 8 bits or 9 bits...
  • Page 565 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-1 shows the block diagram of the serial array unit 0. Figure 15-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) register 0 (NFEN0) SNFEN...

  • Page 566: Shift Register

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.2.1 Shift register This is an 9-bit register that converts parallel data into serial data or vice versa. Note 1 In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used During reception, it converts data input to the serial pin into parallel data.
  • Page 567 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-2. Format of Serial Data Register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) FFF10H (SDR00) SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 15.3 Registers Controlling Serial Array Unit 0.

  • Page 568: Registers Controlling Serial Array Unit 0

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3 Registers Controlling Serial Array Unit 0 Serial array unit 0 is controlled by the following registers.  Peripheral enable register 0 (PER0)  Serial clock select register m (SPSm)  Serial mode register mn (SMRmn) ...

  • Page 569: Peripheral Enable Register 0 (Per0)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 570: Serial Clock Select Register M (Spsm)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.

  • Page 571: Serial Mode Register Mn (Smrmn)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI or UART), and an interrupt source.

  • Page 572: Serial Communication Operation Setting Register Mn (Scrmn)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-6. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03) After reset: 0020H Symbol SMRmn Note Note Controls inversion of level of receive data of channel n in UART mode Falling edge is detected as the start bit.
  • Page 573 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03) After reset: 0087H Symbol SCRmn SLCm DLSm Note 1 Note 2 Setting of operation mode of channel n Disable communication.
  • Page 574 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03) After reset: 0087H Symbol SCRmn SLCm DLSm Note 1 Note 2 Setting of parity bit in UART mode...

  • Page 575: Higher 7 Bits Of The Serial Data Register Mn (Sdrmn)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00 and...
  • Page 576 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Cautions 1. Be sure to clear bit 8 of the SDR02 and SDR03 to “0”. 2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used. 3. When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation instruction (SDRmn[15:9] are all cleared to 0).

  • Page 577: Serial Flag Clear Trigger Register Mn (Sirmn)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.

  • Page 578: Serial Status Register Mn (Ssrmn)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error.
  • Page 579 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-10. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03) After reset: 0000H Symbol SSRmn FEFm Note FEFmn Note Framing error detection flag of channel n No error occurs.

  • Page 580: Serial Channel Start Register M (Ssm)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).

  • Page 581: Serial Channel Stop Register M (Stm)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).

  • Page 582: Serial Channel Enable Status Register M (Sem)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.

  • Page 583: Serial Output Enable Register M (Soem)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.

  • Page 584: Serial Output Register M (Som)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.

  • Page 585: Serial Output Level Register M (Solm)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode.

  • Page 586: Serial Standby Control Register 0 (Ssc0)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.14 Serial standby control register 0 (SSC0) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data.

  • Page 587: Input Switch Control Register (Isc)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.15 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus and DMX512 communication operation by UART0 in coordination with an external interrupt and the timer array unit.

  • Page 588: Noise Filter Enable Register 0 (Nfen0)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.

  • Page 589: Registers Controlling Port Functions Of Serial I/O Pins

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.3.17 Registers controlling port functions of serial I/O pins When using the serial array unit set the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control register (PMCxx)).

  • Page 590: Operation Stop Mode

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode.

  • Page 591: Stopping The Operation By Channels

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 15-23. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.

  • Page 592: Operation Of 3-Wire Serial I/O (Csi00) Communication

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5 Operation of 3-Wire Serial I/O (CSI00) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception]  Data length of 7 or 8 bits ...
  • Page 593 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 The channels supporting 3-wire serial I/O (CSI00) are channels 0.  20-pin products Channel Used as CSI Used as UART  UART0 (supporting LIN-bus, DMX512)      30-pin products Channel...

  • Page 594: Master Transmission

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.1 Master transmission Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SO00...
  • Page 595 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
  • Page 596 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-25. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 597 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-26. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
  • Page 598 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation (Essential) Slave ready? completed Disable data output and clock output of Port manipulation...
  • Page 599 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-transmission mode) Figure 15-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 600 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, see Figure 15-25. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 601 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous transmission mode) Figure 15-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <6> STmn SEmn SDRmn Transmit data 2...
  • Page 602 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, see Figure 15-25. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 603: Master Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.2 Master reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Target channel...
  • Page 604 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
  • Page 605 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. SOEm SOEm2 SOEm0 ...
  • Page 606 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-33. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 607 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable clock output of the target channel by setting a port register and a...
  • Page 608 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-reception mode) Figure 15-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 2 Receive data 3...
  • Page 609 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 15-33. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data...
  • Page 610 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous reception mode) Figure 15-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
  • Page 611 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, see Figure 15-33. buffer empty (Select interrupt) SAU default setting <1> Setting storage area of the receive data, number of communication data...

  • Page 612: Master Transmission/Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.3 Master transmission/reception Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 Target channel Channel 0 of SAU0 Pins used SCK00, SI00, SO00...
  • Page 613 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
  • Page 614 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 615 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 616 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
  • Page 617 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed. preparations? Disable data output and clock output of...
  • Page 618 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-transmission/reception mode) Figure 15-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 1...
  • Page 619 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-45. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 15-41. SAU default setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data...
  • Page 620 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous transmission/reception mode) Figure 15-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn STmn <8> SEmn Receive data 3...
  • Page 621 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, see Figure 15-41. <1> SAU default setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data...

  • Page 622: Slave Transmission

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.4 Slave transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 623 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
  • Page 624 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 625 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-49. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 626 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-50. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
  • Page 627 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-51. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? (master) Disable data output of the target channel by setting a port register and a port...
  • Page 628 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-transmission mode) Figure 15-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2...
  • Page 629 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, see Figure 15-49. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data...
  • Page 630 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous transmission mode) Figure 15-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn STmn <6> SEmn SDRmn Transmit data 1...
  • Page 631 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, see Figure 15-49. <1> SAU default setting (Select buffer empty interrupt) Setting transmit data Set storage area and the number of data for transmit data...

  • Page 632: Slave Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.5 Slave reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 633 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
  • Page 634 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) …The Register that not used in this mode.
  • Page 635 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-57. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 636 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-59. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master (Essential) preparations? Disable clock output of the target channel by setting a port register and a...
  • Page 637 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-reception mode) Figure 15-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1...
  • Page 638 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, see Figure 15-57. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data...

  • Page 639: Slave Transmission/Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.6 Slave transmission/reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 Target channel...
  • Page 640 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
  • Page 641 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
  • Page 642 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
  • Page 643 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
  • Page 644 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port...
  • Page 645 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-transmission/reception mode) Figure 15-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2...
  • Page 646 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-67. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 15-63. SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data...
  • Page 647 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous transmission/reception mode) Figure 15-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3...
  • Page 648 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, see Figure 15-63. <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data...

  • Page 649: Snooze Mode Function

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input.
  • Page 650 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-71. Flowchart of SNOOZE Mode Operation (Once Startup) SNOOZE mode operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) <1> Write 1 to STm0 bit SMRm0, SCRm0: Communication setting...
  • Page 651 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) SNOOZE mode operation (continuous startup) Figure 15-72. Timing Chart of SNOOZE Mode Operation (Continuous Startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal operation STOP mode SNOOZE mode...
  • Page 652 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-73. Flowchart of SNOOZE Mode Operation (Continuous Startup) SNOOZE mode operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) Write 1 to STm0 bit <1> SMRm0, SCRm0: Communication setting...

  • Page 653: Calculating Transfer Clock Frequency

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00) communication can be calculated by the following expressions. (1) Master ) frequency of target channel} ÷ (SDRmn[15:9] + 1)  2 [Hz]...
  • Page 654 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Table 15-2. Selection of Operation Clock For 3-Wire Serial I/O Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz...

  • Page 655: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O (Csi00)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00) communication is described in Figure 15-74. Figure 15-74. Processing Procedure in Case of Overrun Error...

  • Page 656: Operation Of Uart (Uart0, Uart1) Communication

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6 Operation of UART (UART0, UART1) Communication This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
  • Page 657 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 UART0 uses channels 0 and 1. UART1 uses channels 2 and 3. • 20-pin products Channel Used as CSI Used as UART − UART0 (supporting LIN-bus, DMX512) − − − − • 30-pin products...

  • Page 658: Uart Transmission

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6.1 UART transmission UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
  • Page 659 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-75. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn2 MDmn1 MDmn0 Operation clock (f...
  • Page 660 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-75. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm0 SOm2 SOm0 ×...
  • Page 661 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-76. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 662 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-77. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
  • Page 663 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-78. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? or communication operation completed Disable data output of the target channel (Selective)
  • Page 664 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow (in single-transmission mode) Figure 15-79. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1...
  • Page 665 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-80. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, see Figure 15-76. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 666 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (4) Processing flow (in continuous transmission mode) Figure 15-81. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SSmn <6> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3...
  • Page 667 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-82. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART8:0 communication For the initial setting, see Figure 15-76. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 668: Uart Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6.2 UART reception UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 669 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) Register setting Figure 15-83. Example of Contents of Registers for UART Reception of UART (UART0, UART1) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
  • Page 670 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-83. Example of Contents of Registers for UART Reception of UART (UART0, UART1) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. CKOm2 CKOm0 SOm2 SOm0 ×...
  • Page 671 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Operation procedure Figure 15-84. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock.
  • Page 672 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-86. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait Completing master until completes its communication (Essential) preparations? operation. Re-set the register to change the operation...
  • Page 673 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Processing flow Figure 15-87. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 3 Receive data 2 Receive data 1...
  • Page 674 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-88. Flowchart of UART Reception Starting UART communication For the initial setting, see Figure 15-84. SAU default setting (setting to mask for error interrupt) Setting storage area of the receive data, number of communication...

  • Page 675: Snooze Mode Function

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation.
  • Page 676 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Table 15-3. Baud Rate Setting for UART Reception in SNOOZE Mode High-speed On-chip Baud Rate for UART Reception in SNOOZE Mode Oscillator (f Baud Rate of 4800 bps Operation Clock SDRmn Maximum Minimum Permissible...
  • Page 677 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated.
  • Page 678 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
  • Page 679 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-91. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start Does TSFmn = 0 on all channels? The operation of all channels is also stopped to switch to the Writing 1 to the STmn bit <1>...
  • Page 680 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 15-89 Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 15-90 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0).
  • Page 681 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? Clear the all error flags SIRm1 = 0007H The operation of all channels is also stopped to switch to Writing 1 to the STmn bit <1>...
  • Page 682 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore,...

  • Page 683: Calculating Baud Rate

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0, UART1) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
  • Page 684 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Table 15-4. Selection of Operation Clock For UART Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz...
  • Page 685 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (2) Baud rate error during transmission The baud rate error of UART (UART0, UART1) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
  • Page 686 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0, UART1) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.

  • Page 687: Procedure For Processing Errors That Occurred During Uart (Uart0, Uart1)

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.6.5 Procedure for processing errors that occurred during UART (UART0, UART1) communication The procedure for processing errors that occurred during UART (UART0, UART1) communication is described in Figures 15-95 and 15-96. Figure 15-95. Processing Procedure in Case of Parity Error or Overrun Error...

  • Page 688: Lin Communication Operation

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.7 LIN Communication Operation 15.7.1 LIN transmission Of UART transmission, UART0 supports LIN communication. For LIN transmission, channel 0 of unit 1 is used. UART UART0 UART1 Support of LIN communication Supported Not supported −...
  • Page 689 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
  • Page 690 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 <R> Figure 15-98. Flowchart for LIN Transmission Starting LIN Operation of the hardware (reference) communication Transmitting wakeup signal frame (80H → TXD0) Wakeup signal frame generation Transmitting wakeup TSF00 = 0? TxD0 8-bit length...

  • Page 691: Lin Reception

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.7.2 LIN reception Of UART reception, UART0 supports LIN communication. For LIN reception, channel 1 of unit 0 is used. UART UART0 UART1 Support of LIN communication Supported Not supported − Target channel Channel 1 −...
  • Page 692 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 <R> Figure 15-99. Reception Operation of LIN Protected Wakeup signal Break field Sync field Data field Data field Checksum identifier frame field field LIN Bus Header Response Data Checksum Break Data reception reception...
  • Page 693 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-100. Flowchart for LIN Reception Status of LIN bus signal and operation of Starting LIN communication the hardware Wakeup signal frame Wait for wakeup frame Generate INTP0? RxD0 pin Note signal Edge detection...
  • Page 694 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 Figure 15-101 shows the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0).
  • Page 695 RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 The peripheral functions used for the LIN communication operation are as follows. <Peripheral functions used> • External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication •...

  • Page 696: Dmx512 Communication Operation

    RL78/I1A CHAPTER 15 SERIAL ARRAY UNIT 0 15.8 DMX512 Communication Operation Of UART reception, UART0 supports DMX512 communication. For DMX512 reception, channel 1 is used. UART UART0 UART1 Support of DMX512 Supported Not supported communication − Target channel Channel 1 −...

  • Page 697: Chapter 16 Serial Array Unit 4 (Dali/Uart4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Channels 0 and 1 of serial array unit 4 function as a DALI/UART4 support to master and slave of DALI communications. DALI/UART4, like UART0 and UART1, can also be used for UART communications.
  • Page 698 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) DALI mode This mode is used to perform data transmission/reception as master and slave of DALI (Digital Addressable Lighting Interface). See 16.6.1 DALI transmission or 16.6.2 DALI reception for details. DALI reception is not supported in the SNOOZE mode.

  • Page 699: Configuration Of Serial Array Unit 4 (Dali/Uart4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.2 Configuration of Serial Array Unit 4 (DALI/UART4) The serial array unit 4 (DALI/UART4) includes the following hardware. Table 16-1. Configuration of Serial Array Unit 4 (DALI/UART4) Item Configuration Shift register 9 bits...
  • Page 700 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-1 shows the block diagram of the serial array unit 4 (DALI/UART4). Figure 16-1. Block Diagram of Serial Array Unit 4 (DALI/UART4) Serial output register 4 (SO4) Noise filter enable register 3 (NFEN3)

  • Page 701: Shift Register

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin.

  • Page 702: Dali Transmit Data Registers H4, L4 (Sdth4, Sdtl4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.2.3 DALI transmit data registers H4, L4 (SDTH4, SDTL4) The SDTH4, SDTL4 registers are the transmit data register (16 bits) of DALI. Of the transmit data sent to the shift register during DALI communications, bits 15 to 0 are set in the SDTL4 register and bits 23 to 16 are set in the SDTH4 register.

  • Page 703: Dali Receive Data Registers H4, L4 (Sdch4, Sdcl4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.2.4 DALI receive data registers H4, L4 (SDCH4, SDCL4) The SDCH4, SDCL4 registers are the receive data register (16 bits) of DALI. When DALI is received, parallel data that was converted in the shift register is written starting from LSB of the SDCL4 register.

  • Page 704: Registers Controlling Serial Array Unit 4 (Dali/Uart4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3 Registers Controlling Serial Array Unit 4 (DALI/UART4) Serial array unit 4 (DALI/UART4) is controlled by the following registers.  Peripheral enable register 1 (PER1)  Serial clock select register 4 (SPS4) ...

  • Page 705: Peripheral Enable Register 1 (Per1)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.1 Peripheral enable register 1 (PER1) PER1 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.

  • Page 706: Serial Clock Select Register 4 (Sps4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.2 Serial clock select register 4 (SPS4) The SPS4 register is a 16-bit register that is used to select operation clock (CK40) that are commonly supplied to each channel. Rewriting the SPS4 register is prohibited when the register is in operation (when SE4n = 1).
  • Page 707 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-6. Format of Serial Clock Select Register 4 (SPS4) Address: F05A6H, F05A7H After reset: 0000H Symbol SPS4 Section of operation clock (CK40) Note = 4 MHz (not using PLL) = 16 MHz (using PLL)

  • Page 708: Serial Mode Register 4N (Smr4N)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.3 Serial mode register 4n (SMR4n) The SMR4n register is a register that sets an operation mode of channel n. It is also used to set a start trigger and select an interrupt source. This register is also used to invert the level of the receive data.

  • Page 709: Serial Communication Operation Setting Register 4N (Scr4N)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.4 Serial communication operation setting register 4n (SCR4n) The SCR4n register is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
  • Page 710 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-8. Format of Serial Communication Operation Setting Register 4n (SCR4n) (2/2) Address: F0598H, F0599H (SCR40), F059AH, F059BH (SCR41) After reset: 0087H Symbol SCR4n Note Selection of data transfer sequence Inputs/outputs data with MSB first.

  • Page 711: Higher 7 Bits Of The Serial Data Register 4N (Sdr4N)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.5 Higher 7 bits of the serial data register 4n (SDR4n) The SDR4n register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR4n...

  • Page 712: Serial Status Register 4N (Ssr4N)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.6 Serial status register 4n (SSR4n) The SSR4n register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, manchester framing error, parity error, and overrun error.
  • Page 713 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-10. Format of Serial Status Register 4n (SSR4n) (2/3) Address: F0580H, F0581H (SSR40), F0582H, F0583H (SSR41) After reset: 0000H Symbol SSR4n MFEF Note Note Note Buffer register status indication flag of channel n Valid data is not stored in the SDR4n register.
  • Page 714 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-10. Format of Serial Status Register 4n (SSR4n) (3/3) Address: F0580H, F0581H (SSR40), F0582H, F0583H (SSR41) After reset: 0000H Symbol SSR4n MFEF Note Note Note Overrun error detection flag of channel n No error occurs.

  • Page 715: Serial Flag Clear Trigger Register 4N (Sir4N)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.7 Serial flag clear trigger register 4n (SIR4n) The SIR4n register is a trigger register that is used to clear each error flag of channel n. When each bit (MFECT4n, FECT4n, PECT4n, OVCT4n) of this register is set to 1, the corresponding bit (MFEF4n, FEF4n, PEF4n, OVF4n) of serial status register 4n is cleared to 0.

  • Page 716: Serial Channel Start Register 4 (Ss4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.8 Serial channel start register 4 (SS4) The SS4 register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SS4n), the corresponding bit (SE4n) of serial channel enable status register 4 (SE4) is set to 1 (Operation is enabled).

  • Page 717: Serial Channel Stop Register 4 (St4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.9 Serial channel stop register 4 (ST4) The ST4 register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (ST4n), the corresponding bit (SE4n) of serial channel enable status register 4 (SE4) is cleared to 0 (operation is stopped).

  • Page 718: Serial Channel Enable Status Register 4 (Se4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.10 Serial channel enable status register 4 (SE4) The SE4 register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register 4 (SS4), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register 4 (ST4), the corresponding bit is cleared to 0.

  • Page 719: Serial Output Enable Register 4 (Soe4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.11 Serial output enable register 4 (SOE4) The SOE4 register is a register that is used to enable or stop output of the serial communication operation of channel 0. Channel 0 that enables serial output cannot rewrite by software the value of the SO40 bit of serial output register 4 (SO4) to be described below, and a value reflected by a communication operation is output from the serial data output pin.

  • Page 720: Serial Output Register 4 (So4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.12 Serial output register 4 (SO4) The SO4 register is a buffer register for serial output of channel 0. The value of the SO40 bit of this register is output from the serial data output pin of channel 0.

  • Page 721: Serial Output Level Register 4 (Sol4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.13 Serial output level register 4 (SOL4) The SOL4 register is a register that is used to set inversion of the data output level of channel 0. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOE40 = 1).

  • Page 722: Serial Standby Control Register 4 (Ssc4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.14 Serial standby control register 4 (SSC4) The SSC4 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving UART4 serial data. The SSC4 register can be set by a 16-bit memory manipulation instruction.

  • Page 723: Serial Option Control Register 4 (Soc4)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.15 Serial option control register 4 (SOC4) The SOC4 register is used to control the DALI/UART4 communication mode. The SOC4 register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears the SOC4 register to 0000H.

  • Page 724: Noise Filter Enable Register 3 (Nfen3)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.17 Noise filter enable register 3 (NFEN3) The NFEN3 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.

  • Page 725: Port Mode Registers 1, 20 (Pm1, Pm20)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.19 Port mode registers 1, 20 (PM1, PM20) This register sets input/output of port 1, 20 in 1-bit units. When using the port (PM10/SO00/TxD0/TKCO00/INTP20/SCLA0/(DALITxD4), P205/DALITxD4/TKBO21/TKCO04) to be shared with the serial data output pin for serial data output, set the PM10 and PM205 bits of the port mode registers (PM1, PM20) to 0.

  • Page 726: Peripheral I/O Redirection Register (Pior1)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.3.20 Peripheral I/O redirection register (PIOR1) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.

  • Page 727: Operation Stop Mode

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.4 Operation Stop Mode Serial array unit 4 (DALI/UART4) has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface 4 can be used as port function pins in this mode.

  • Page 728: Stopping The Operation By Channels

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 16-26. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register 4 (ST4) …...

  • Page 729: Communication Operation Of Uart

    CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.5 Communication Operation of UART 16.5.1 UART transmission UART transmission is an operation to transmit data from the RL78/I1A to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
  • Page 730 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) Register setting Figure 16-27. Example of Contents of Registers for UART Transmission (1/2) (a) Serial option control register 4 (SOC4) Setting of UART/DALI communication mode 0: UART mode setting (b) Serial mode register 4n (SMR4n)
  • Page 731 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-27. Example of Contents of Registers for UART Transmission (2/2) (f) Serial output register 4 (SO4) … Sets only the bits of the target channel. SO40 Note 0: Serial data output value is “0”...
  • Page 732 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Operation procedure Figure 16-28. Initial Setting Procedure for UART Transmission Starting initial setting Release the DALI/UART4 unit from the Setting the PER1 register reset status and start clock supply. Set the operation clock.
  • Page 733 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-29. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSF4n = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the ST4n bit of the target channel.
  • Page 734 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-30. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? or communication operation completed Disable data output of the target channel...
  • Page 735 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (3) Processing flow (in single-transmission mode) Figure 16-31. Timing Chart of UART Transmission (in Single-Transmission Mode) SS4n ST4n SE4n SDR4n Transmit data 1 Transmit data 2 Transmit data 3 DALITxD4 pin Transmit data 2...
  • Page 736 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-32. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, see Figure 16-28. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag...
  • Page 737 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (4) Processing flow (in continuous transmission mode) Figure 16-33. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SS4n <6> ST4n SE4n SDR4n Transmit data 1 Transmit data 2 Transmit data 3...
  • Page 738 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-34. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, see Figure 16-28. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag...

  • Page 739: Uart Reception

    CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.5.2 UART reception UART reception is an operation wherein the RL78/I1A asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 740 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) Register setting Figure 16-35. Example of Contents of Registers for UART Reception (1/2) (a) Serial option control register 4 (SOC4) Setting of UART/DALI communication mode 0: UART mode setting (b) Serial mode register 4n (SMR4n)
  • Page 741 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-35. Example of Contents of Registers for UART Reception (2/2) (f) Serial output register 4 (SO4) … The register that not used in this mode. SO40  (g) Serial output enable register 4 (SOE4) …The register that not used in this mode.
  • Page 742 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Operation procedure Figure 16-36. Initial Setting Procedure for UART Reception Starting initial setting Release the DALI/UART4 unit from the Setting the PER1 register reset status and start clock supply. Setting the SPS4 register Set the operation clock.
  • Page 743 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-38. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait Completing master until completes its communication (Essential) preparations? operation. Re-set the register to change the operation...
  • Page 744 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (3) Processing flow Figure 16-39. Timing Chart of UART Reception SS4n ST4n SE4n Receive data 3 SDR4n Receive data 1 Receive data 2 DALIRxD4 pin Receive data 3 Receive data 1 Receive data 2...
  • Page 745 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-40. Flowchart of UART Reception Starting UART communication For the initial setting, see Figure 16-36. (setting to mask for error interrupt) SAU default setting Setting storage area of the receive data, number of communication...

  • Page 746: Snooze Mode Function

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.5.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation.
  • Page 747 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Table 16-2. Baud Rate Setting for UART Reception in SNOOZE Mode High-speed On-chip Baud Rate for UART Reception in SNOOZE Mode Oscillator (f Baud Rate of 4800 bps Operation Clock SDRmn Maximum...
  • Page 748 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSREq) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSRq) will be generated.
  • Page 749 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
  • Page 750 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-43. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start Does TSFmn = 0 on all channels? The operation of all channels is also stopped to switch to the Writing 1 to the STmn bit <1>...
  • Page 751 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 16-41 Timing Chart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1) and Figure 16-42 Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0).
  • Page 752 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-45. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? Clear the all error flags SIRm1 = 0007H The operation of all channels is also stopped to switch to Writing 1 to the STmn bit <1>...
  • Page 753 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore,...

  • Page 754: Dali Mode

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.6 DALI Mode This mode is used to perform data transmission/reception as master and slave of DALI (Digital Addressable Lighting Interface). DALI performs communication using the following protocol. Caution See the latest standard specifications with regard to DALI communications standards.
  • Page 755 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) Data structure <1> Bit definition A falling edge is bit-defined as “0” and a rising edge as “1”, because DALI communication uses Manchester code. If no communication is performed, DALI communication is fixed to the high level.
  • Page 756 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Transmission/reception timing rules <1> Timing in the frame  s 10%) for both Forward and Backward frames. The DALI bit width is one bit (= 833.3 Figure 16-49. Timing in the Frame...

  • Page 757: Dali Transmission

    CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.6.1 DALI transmission DALI transmission is an operation to transmit data from the RL78/I1A to another device asynchronously (start-stop synchronization). Of two channels used for DALI, the even channel is used for DALI transmission.
  • Page 758 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) Register setting Figure 16-51. Example of Contents of Registers for DALI Transmission (1/2) (a) Serial option control register 4 (SOC4) Setting of UART/DALI communication mode 1: DALI mode setting (b) Serial mode register 4n (SMR4n)
  • Page 759 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-51. Example of Contents of Registers for DALI Transmission (2/2) (f) Serial output level register 4 (SOL4) … Sets only the bits of the target channel. SOL4 SOL40 0: Non-reverse transmission 1: Reverse transmission (g) Serial output register 4 (SO4) …...
  • Page 760 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Operation procedure Figure 16-52. Initial Setting Procedure for DALI Transmission Starting initial setting Release the DALI/UART4 unit from the Setting the PER1 register reset status and start clock supply. Set the operation clock.
  • Page 761 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-53. Procedure for Stopping DALI Transmission Starting setting to stop Write 1 to the ST4n bit of the target Setting the ST4 register channel. Set the SOE4n bit to 0 and stop the Setting the SOE4 register output.
  • Page 762 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-54. Procedure for Resuming DALI Transmission Starting setting for resumption Disable data output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. Re-set the register to change the...
  • Page 763 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (3) Processing flow Figure 16-55. Timing Chart of DALI Transmission SS4n ST4n SE4n SDTH4, SDTL4 Transmit data 1 Transmit data 2 Transmit data 3 DALITxD4 pin Transmit data 2 Transmit data 1...
  • Page 764 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-56. Flowchart of DALI Transmission Starting DALI communication Setting the DALIEN bit of the PER1 register to 1 Setting operation clock by the SPS4 register SOC4: Setting DALI mode Specify the initial settings while the...

  • Page 765: Dali Reception

    CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.6.2 DALI reception DALI reception is an operation wherein the RL78/I1A asynchronously receives data from another device (start-stop synchronization). For DALI reception, the odd-number channel of the two channels used for DALI is used. The SMR register of both the odd- and even-numbered channels must be set.
  • Page 766 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (1) Register setting Figure 16-57. Example of Contents of Registers for DALI Reception (1/2) (a) Serial option control register 4 (SOC4) Setting of UART/DALI communication mode 1: DALI mode setting (b) Serial mode register 4n (SMR4n)
  • Page 767 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-57. Example of Contents of Registers for DALI Reception (2/2) (f) DALI receive data register (SDCHm, SDCLm) SDCHm SDCLm (g) Serial output register 4 (SO4) …The register that not used in this mode.
  • Page 768 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Operation procedure Figure 16-58. Initial Setting Procedure for DALI Reception Starting initial setting Release the DALI/UART4 unit from the Setting the PER1 register reset status and start clock supply. Setting the SPS4 register Set the operation clock.
  • Page 769 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-60. Procedure for Resuming DALI Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Re-set the register to change the operation...
  • Page 770 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (3) Processing flow Figure 16-61. Timing Chart of DALI Reception SS4n ST4n SE4n Receive data 3 SDCH4, SDCL4 Receive data 1 Receive data 2 DALIRxD4 pin Receive data 1 Receive data 3...
  • Page 771 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-62. Flowchart of DALI Reception Starting DALI communication Setting the DALIEN bit of the PER1 register to 1 Setting operation clock by the SPS4 register Specify the initial settings SOC4: Setting DALI mode.

  • Page 772: Standby Function (Only Dali/Uart4 Reception)

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.7 Standby Function (Only DALI/UART4 Reception) (1) Returning from STOP & HALT modes (when DALI is received) DALI can be received after wakeup from a STOP mode by using the interrupt function of the INTPx input. As a result, power-saving reception waiting can be realized.
  • Page 773 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-64. Flowchart of Returning from STOP Mode for Reception Setting start DALI reception <1> For the default setting, see Figure 16-58. default setting Setting INTP21/INTP23 interrupt <2> EGP21 = 0, EGN21 = 1...

  • Page 774: Single-Wire Data Mode

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.8 Single-wire Data Mode When the SUCTL0 bit in the single-wire data control register (SUCTL) is set to 1, single-wire DALI/UART4 communications can be executed. When the single-wire method is selected, the P206/TxRx4/TKCO05/DALIRxD4/INTP23 pin is shared for transmission and reception.

  • Page 775: Calculating Baud Rate

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.9 Calculating Baud Rate (1) Baud rate calculation expression The baud rate for DALI/UART4 communication can be calculated by the following expressions. UART communication (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDR4n[15:9] + 1) ÷ 2 [bps]...
  • Page 776 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Table 16-3. Selection of Operation Clock For DALI/UART4 Note SPS4 Register Operation Clock (f PRSm03 PRSm02 PRSm01 PRSm00 = 4MHz (not using PLL) = 16MHz (using PLL) = 32 MHz (using PLL)
  • Page 777 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (2) Baud rate error during transmission The baud rate error of DALI/UART4 communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
  • Page 778 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4)  UART communication UART Baud Rate = 32 MHz (Target Baud Rate) Operation Clock (f SDR4n[15:9] Calculated Baud Rate Error from Target Baud Rate 300 bps 300.48 bps +0.16 % 600 bps 600.96 bps...
  • Page 779 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) (3) Permissible baud rate range for reception (in the UART communication) The permissible baud rate range for reception during DALI/UART4 communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.

  • Page 780: Procedure For Processing Errors That Occurred During Dali/Uart4

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.10 Procedure for Processing Errors That Occurred During DALI/UART4 Communication The procedure for processing errors that occurred during DALI/UART4 communication is described in Figure 16-67 and Figure 16-68. Figure 16-67. Processing Procedure in Case of Parity Error or Overrun Error...

  • Page 781: Dmx512 Communication Operation

    RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) 16.11 DMX512 Communication Operation UART4 supports DMX512 communication. UART UART4 Support of DMX512 Supported communication Target channel Channel 1 Pins used DALIRxD4 Interrupt INTSRDL4 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
  • Page 782 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-69. Reception Operation of DMX512 Break (88 µs to 1 s) Channel 1 Start code <4> <5> DALIRxD4 pin <1> Mark break Time between frame (8 µs to 1 s) (0 s to 1 s) DALI/UART4 reception communication <2>...
  • Page 783 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) State <4> (StartCode received) - INTSRDL4 interrupt generated by start code reception Check data; if 1s data is not 0, go to state <1>. If there is receive error (INTSREDL4), clear error and go to state (1).
  • Page 784 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) Figure 16-70 shows the configuration of a port that manipulates reception of DMX512. The BREAK signal transmitted from the master of DMX512 is received by detecting an edge of an external interrupt (INTP0).
  • Page 785 RL78/I1A CHAPTER 16 SERIAL ARRAY UNIT 4 (DALI/UART4) The peripheral functions used for the DMX512 communication operation are as follows. <Peripheral functions used>  External interrupt (INTP0); BREAK signal detection Usage: To detect an edge of the BREAK signal and the start of communication ...

  • Page 786: Chapter 17 Serial Interface Iica

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA CHAPTER 17 SERIAL INTERFACE IICA Caution Most of the following descriptions in this chapter use the 38-pin products as an example. 17.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes.
  • Page 787 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 (IICCTL00) Control-circuit for STOP mode IICE0...
  • Page 788 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-2 shows a serial bus configuration example. Figure 17-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU1 Master CPU2 SDAA0 SDAA0 Slave CPU1 Slave CPU2 Serial clock SCLA0...

  • Page 789: Configuration Of Serial Interface Iica

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 17-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register 0 (IICA0) Slave address register 0 (SVA0) Control registers...
  • Page 790 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (2) Slave address register 0 (SVA0) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVA0 register can be set by an 8-bit memory manipulation instruction.
  • Page 791 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.

  • Page 792: Registers Controlling Serial Interface Iica

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following registers. • Peripheral enable register 0 (PER0) • IICA control register 00 (IICCTL00) • IICA flag register 0 (IICF0) • IICA status register 0 (IICS0) •...

  • Page 793: Iica Control Register 00 (Iicctl00)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3.2 IICA control register 00 (IICCTL00) This register is used to enable/stop I C operations, set wait timing, and set other I C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period.
  • Page 794 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Stop operation.
  • Page 795 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-6. Format of IICA Control Register 00 (IICCTL00) (2/4) SPIE0 Note 1 Enable/disable generation of interrupt request when stop condition is detected Disable Enable If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
  • Page 796 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-6. Format of IICA Control Register 00 (IICCTL00) (3/4) Notes 1, 2 Start condition trigger STT0 Do not generate a start condition. When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master).
  • Page 797 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-6. Format of IICA Control Register 00 (IICCTL00) (4/4) Note Stop condition trigger SPT0 Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing  For master reception: Cannot be set to 1 during transfer.

  • Page 798: Iica Status Register 0 (Iics0)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3.3 IICA status register 0 (IICS0) This register indicates the status of I The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period.
  • Page 799 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) ...

  • Page 800: Iica Flag Register 0 (Iicf0)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) ...
  • Page 801 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-8. Format of IICA Flag Register 0 (IICF0) Note Address: FFF52H After reset: 00H <7> <6> <1> <0> Symbol IICF0 STCF0 IICBSY0 STCEN0 IICRSV0 STCF0 STT0 clear flag Generate start condition Start condition generation unsuccessful: clear the STT0 flag...

  • Page 802: Iica Control Register 01 (Iicctl01)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3.5 IICA control register 01 (IICCTL01) This register is used to set the operation mode of I C and detect the statuses of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
  • Page 803 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) The SCLA0 pin was detected at low level. The SCLA0 pin was detected at high level.

  • Page 804: Iica Low-Level Width Setting Register 0 (Iicwl0)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to set the low-level width (t ) of the SCLA0 pin signal that is output by serial interface IICA and to control the SDAA0 pin signal.

  • Page 805: Port Mode Register 1 (Pm1)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.3.8 Port mode register 1 (PM1) This register sets the input/output of port 1 in 1-bit units. When using P10/SCLA0/SO00/TxD0/TKCO00/INTP20/(DALITxD4) clock P11/SDAA0/SI00/RxD0/TKCO01/INTP21/(TI07)/(DALIRxD4)/(TxRx4) pin as serial data I/O, clear PM10 and PM11, and the output latches of P10 and P11 to 0.

  • Page 806: I 2 C Bus Mode Functions

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.4 I C Bus Mode Functions 17.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 ..This pin is used for serial clock input and output.

  • Page 807: Setting Transfer Clock By Using Iicwl0 And Iicwh0 Registers

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side Transfer clock = IICWL0 + IICWH0 + f At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.

  • Page 808: I 2 C Bus Definitions And Control Methods

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 17-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.

  • Page 809: Addresses

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.

  • Page 810: Acknowledge (Ack)

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.

  • Page 811: Stop Condition

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.

  • Page 812: Wait

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
  • Page 813 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-21. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock...

  • Page 814: Canceling Wait

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.7 Canceling wait The I C usually cancels a wait state by the following processing.  Writing data to the IICA shift register 0 (IICA0)  Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait) ...

  • Page 815: Interrupt Request (Intiica0) Generation Timing And Wait Control

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 17-2.

  • Page 816: Address Match Detection Method

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.9 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received.

  • Page 817: Arbitration

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
  • Page 818 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Table 17-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing During address transmission At falling edge of eighth or ninth clock following byte transfer Note 1 Read/write data after address transmission...

  • Page 819: Wakeup Function

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match.
  • Page 820 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-24. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICA0 = 1? WUP0 = 0 Wait Waits for 5 cycles of f Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
  • Page 821 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-25. When Operating as Master Device after Releasing STOP Mode Other than by INTIICA0 START SPIE0 = 1 WUP0 = 1 Waits for 3 cycles of f Wait STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0.

  • Page 822: Communication Reservation

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
  • Page 823 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-26 shows the communication reservation timing. Figure 17-26. Communication Reservation Timing Write to Program processing STT0 = 1 IICA0 Set SPD0 Hardware processing Communication reservation STD0 INTIICA0 SCLA0 SDAA0 Generate by master device with bus mastership...
  • Page 824 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-28. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Note 1 Secures wait time by software.
  • Page 825 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.

  • Page 826: Cautions

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.5.15 Cautions (1) When STCEN = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.

  • Page 827: Communication Operations

    This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/I1A looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave.
  • Page 828 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 17-29. Master Operation in Single-master System START Initializing I C bus Note Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 17.3.8 Port mode register 1 (PM1)).
  • Page 829 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 17-30. Master Operation in Multi-master System (1/3) START Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 17.3.8 Port mode register 1 (PM1)).
  • Page 830 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-30. Master Operation in Multi-master System (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Note Secure wait time by software. Wait MSTS0 = 1? INTIICA0 interrupt occurs? Waits for bus release (communication being reserved).
  • Page 831 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-30. Master Operation in Multi-master System (3/3) Starts communication Writing IICA0 (specifies an address and transfer direction). INTIICA0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1? ACKE0 = 1...
  • Page 832 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
  • Page 833 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.

  • Page 834: Timing Of I C Interrupt Request (Intiica0) Occurrence

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed.
  • Page 835 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
  • Page 836 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1   AD6 to AD0 R/W ACK D7 to D0...
  • Page 837 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B...
  • Page 838 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0001×110B...
  • Page 839 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
  • Page 840 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0...
  • Page 841 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 842 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0...
  • Page 843 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
  • Page 844 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0...
  • Page 845 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK...
  • Page 846 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1...
  • Page 847 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×:...
  • Page 848 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B...
  • Page 849 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B...
  • Page 850 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
  • Page 851 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B...
  • Page 852 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
  • Page 853 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1  AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B...
  • Page 854 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1  AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B...

  • Page 855: Timing Charts

    RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA 17.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
  • Page 856 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-33. Example of Master to Slave Communication (When 9-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICA0 <2>...
  • Page 857 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 17-33 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (SDAA0 = 0 and SCLA0 = 1) is generated once the bus data line goes low (SDAA0 = 0).
  • Page 858 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-33. Example of Master to Slave Communication (When 9-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side Note 1 Note 1 IICA0 <5>...
  • Page 859 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 17-33 are explained below. Note <3> If the address received matches the address of a slave device , that slave device sends an ACK by hardware to the master device.
  • Page 860 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-33. Example of Master to Slave Communication (When 9-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ Stop condition Master side Note 1 IICA0 <9>...
  • Page 861 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 17-33 are explained below. <7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
  • Page 862 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-33. Example of Master to Slave Communication (When 9-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICA0 <iii> ACKD0...
  • Page 863 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The following describes the operations in Figure 17-33 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <ii> are performed. These steps return the processing to step <3>, the data transmission step.
  • Page 864 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-34. Example of Slave to Master Communication (When 8-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICA0 <2> ACKD0...
  • Page 865 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 17-34 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0).
  • Page 866 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-34. Example of Slave to Master Communication (When 8-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICA0 ACKD0 (ACK detection) WTIM0 <5>...
  • Page 867 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 17-34 are explained below. Note <3> If the address received matches the address of a slave device , that slave device sends an ACK by hardware to the master device.
  • Page 868 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA Figure 17-34. Example of Slave to Master Communication (When 8-clock and 9-clock Wait Is Selected for Master, 9-clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side IICA0...
  • Page 869 RL78/I1A CHAPTER 17 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 17-34 are explained below. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer).

  • Page 870: Chapter 18 Multiplier And Divider/Multiply-Accumulator

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits  16 bits = 32 bits (unsigned) • 16 bits  16 bits = 32 bits (signed) •...
  • Page 871 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 18-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator Internal bus Multiply- Multiplication result (product) or accumulation Division multiplication result (product) while in Division result Multiplication/division result result multiply-accumulator mode control register (MDUC) (accumulated) (quotient)

  • Page 872: Multiplication/Division Data Register A (Mdah, Mdal)

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.2.1 Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode.

  • Page 873: Multiplication/Division Data Register B (Mdbl, Mdbh)

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.2.2 Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode.

  • Page 874: Multiplication/Division Data Register C (Mdcl, Mdch)

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.2.3 Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode.
  • Page 875 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. • Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDAL (bits 15 to 0)  MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] •...

  • Page 876: Register Controlling Multiplier And Divider/Multiply-Accumulator

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). 18.3.1 Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator.
  • Page 877 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 18-5. Format of Multiplication/Division Control Register (MDUC) Address: F00E8H After reset: 00H Note 1 Symbol <7> <6> <3> <2> <1> <0> MDUC DIVMODE MACMODE MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM Operation mode selection...

  • Page 878: Operations Of Multiplier And Divider/Multiply-Accumulator

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4 Operations of Multiplier and Divider/Multiply-Accumulator 18.4.1 Multiplication (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH).

  • Page 879: Multiplication (Signed) Operation

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH).

  • Page 880: Multiply-Accumulation (Unsigned) Operation

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH).
  • Page 881 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 18-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2  3 + 3 = 9  32767  2 + 4294901762 = 0 (Over Flow Generated)) Operation clock <1> MDUC MDSM L MDCH 0000H...

  • Page 882: Multiply-Accumulation (Signed) Operation

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4>...
  • Page 883 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 18-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2  3 + (4) = 2  32767  (1) + (2147483647) = 2147450882 (Overflow Occurs.)) Operation clock <1> MDUC MDSM L <3> <9> <3>...

  • Page 884: Division Operation

    RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL).
  • Page 885 RL78/I1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 886: Chapter 19 Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER CHAPTER 19 DMA CONTROLLER The RL78/I1A has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.

  • Page 887: Configuration Of Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 19-1. Configuration of DMA Controller Item Configuration  DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers  DMA RAM address registers 0, 1 (DRA0, DRA1) ...

  • Page 888: Dma Ram Address Register N (Dran)

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see table 19-2) can be set to this register.

  • Page 889: Dma Byte Count Register N (Dbcn)

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).

  • Page 890: Registers Controlling Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers.  DMA mode control register n (DMCn)  DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) R01UH0169EJ0320 Rev.3.20...

  • Page 891: Dma Mode Control Register N (Dmcn)

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
  • Page 892 RL78/I1A CHAPTER 19 DMA CONTROLLER Figure 19-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1)

  • Page 893: Dma Operation Control Register N (Drcn)

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).

  • Page 894: Operation Of Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.4 Operation of DMA Controller 19.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.

  • Page 895: Transfer Mode

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DMA Transfer Mode Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)

  • Page 896: Example Of Setting Of Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.5 Example of Setting of DMA Controller 19.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below.  Consecutive transmission of CSI00 (256 bytes)  DMA channel 0 is used for DMA transfer.
  • Page 897 RL78/I1A CHAPTER 19 DMA CONTROLLER Figure 19-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 10H DRA0 = FB00H DBC0 = 0100H DMC0 = 46H Setting for CSI transfer DST0 = 1 DMA is started.

  • Page 898: Consecutive Capturing Of A/D Conversion Results

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.  Consecutive capturing of A/D conversion results.  DMA channel 1 is used for DMA transfer.
  • Page 899 RL78/I1A CHAPTER 19 DMA CONTROLLER Figure 19-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs.

  • Page 900: Uart Consecutive Reception + Ack Transmission

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below.  Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.

  • Page 901: Holding Dma Transfer Pending By Dwaitn Bit

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.

  • Page 902: Forced Termination By Software

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
  • Page 903 RL78/I1A CHAPTER 19 DMA CONTROLLER Figure 19-11. Forced Termination of DMA Transfer (2/2) Example 3  Procedure for forcibly terminating the DMA  Procedure for forcibly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used...

  • Page 904: Cautions On Using Dma Controller

    RL78/I1A CHAPTER 19 DMA CONTROLLER 19.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, DMA channel 0 takes priority over DMA channel 1.
  • Page 905 RL78/I1A CHAPTER 19 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.  CALL !addr16  CALL $!addr20  CALL !!addr20  CALL  CALLT [addr5] ...
  • Page 906 RL78/I1A CHAPTER 19 DMA CONTROLLER (7) Operation if instructions for accessing the data flash area If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait will be inserted to the next instruction.

  • Page 907: Chapter 20 Interrupt Functions

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS CHAPTER 20 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product.
  • Page 908 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-1. Interrupt Source List (1/3) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address Note 3    Maskable INTWDTI Watchdog timer interval Internal 0004H (75% of overflow time+1/2f  ...
  • Page 909 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-1. Interrupt Source List (2/3) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address    Maskable INTTM03 End of timer channel 3 count or Internal 0032H capture (at 16-bit/lower 8-bit timer operation) ...
  • Page 910 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-1. Interrupt Source List (3/3) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address    Maskable INTTMKB0 End of timer KB0 count Internal 0056H    INTTMKB1 End of timer KB1 count 0058H ...
  • Page 911 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (B) External maskable interrupt (INTPn, INTCMPm) Internal bus...
  • Page 912 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt Vector table request address generator Interrupt request flag Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1...

  • Page 913: Registers Controlling Interrupt Functions

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3 Registers Controlling Interrupt Functions The following types of registers are used to control the interrupt functions.  Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)  Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) ...
  • Page 914 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-2. Flags Corresponding to Interrupt Request Sources (2/3) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register    INTST1 STIF1 IF1L STMK1 MK1L STPR01, STPR11 PR01L, PR11L ...
  • Page 915 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-2. Flags Corresponding to Interrupt Request Sources (3/3) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register    INTTM05 TMIF05 IF2L TMMK05 MK2L TMPR005, TMPR105 PR02L, PR12L ...
  • Page 916 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-2. Image of Interrupt Controller for External Interrupts INTP20 to INTP23, Comparator Interrupts INTCMP3 to INTCMP5 Interrupt mask flag register 0 (INTMK0) INTMK06 INTMK05 INTMK04 INTMK03 INTMK02 INTMK01 INTMK00 INTP20 INTP21 INTP22 Interrupt controller...

  • Page 917: Interrupt Request Flag Registers (If0L, If0H, If1L, If1H, If2L, If2H)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 918 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (38-pin) (2/2) Address: FFFD1H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF2H FLIF PIF21 MDIF TMKCIF0...

  • Page 919: Interrupt Mask Flag Registers (Mk0L, Mk0H, Mk1L, Mk1H, Mk2L, Mk2H)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H registers can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 920: Pr10H, Pr11L, Pr11H, Pr12L, Pr12H)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
  • Page 921 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-5. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (38-pin) (2/2) Address: FFFEBH After reset: FFH Symbol <7> <6> <5> <4> <2> <1> <0>...

  • Page 922: Edge Enable Registers (Egn0, Egn1, Egn2)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.4 External interrupt rising edge enable registers (EGP0, EGP1, EGP2), external interrupt falling edge enable registers (EGN0, EGN1, EGN2) These registers specify the valid edge for INTP0 to INTP11. The EGP0 to EGP2, and EGN0 to EGN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 923 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-3. Interrupt Request Signal Corresponding to EGPn and EGNn Bits Detection Enable Bit Edge Detection Interrupt Request 38-pin 30-pin 20-pin Port Signal    EGP0 EGN0 P137 INTP0    EGP3 EGN3 INTP3 ...

  • Page 924: Comparator Rising Edge Enable Register 0 (Cmpegp0), Comparator Falling Edge Enable Register 0 (Cmpegn0)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.5 Comparator rising edge enable register 0 (CMPEGP0), comparator falling edge enable register 0 (CMPEGN0) These registers are used to set the valid edges of comparator n detection interrupt signal (INTCMPn) and external interrupts (INTP20, INTP21).

  • Page 925: Interrupt Mask Flag Register 0 (Intmk0)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.6 Interrupt mask flag register 0 (INTMK0) The interrupt mask flag register 0 (INTMK0) is used to mask the interrupt request signals of INTP20 to INTP23, and INTCMP3 to INTCMP5. The INTMK0 register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 926: Interrupt Monitor Flag Register 0 (Intmf0)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.7 Interrupt monitor flag register 0 (INTMF0) The interrupt mask flag register 0 (INTMF0) is used to monitor the generation status of the interrupt request signals of INTP20 to INTP23. Generating the interrupt request signals of INTP20 to INTP23 set the corresponding flag of the INTMF0 register to 1.

  • Page 927: Program Status Word (Psw)

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.3.8 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.

  • Page 928: Interrupt Servicing Operations

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.4 Interrupt Servicing Operations 20.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 929 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-11. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending ××PR No (Low priority) (××PR ≥ (ISP1, ISP0) Interrupt request held pending Higher priority...
  • Page 930 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-12. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing jump to interrupt CPU processing Instruction Instruction Instruction program servicing xxIF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 20-13.

  • Page 931: Software Interrupt Request Acknowledgment

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
  • Page 932 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request...
  • Page 933 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-14. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz...
  • Page 934 RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-14. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx...

  • Page 935: Interrupt Request Hold

    RL78/I1A CHAPTER 20 INTERRUPT FUNCTIONS 20.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 936: Chapter 21 Standby Function

    RL78/I1A CHAPTER 21 STANDBY FUNCTION CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.

  • Page 937: Registers Controlling Standby Function

    RL78/I1A CHAPTER 21 STANDBY FUNCTION 21.2 Registers Controlling Standby Function The registers which control the standby function are described below.  Subsystem clock supply mode control register (OSMC)  Oscillation stabilization time counter status register (OSTC)  Oscillation stabilization time select register (OSTS) Remark For details of registers described above, see CHAPTER 5 CLOCK GENERATOR.
  • Page 938 RL78/I1A CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
  • Page 939 RL78/I1A CHAPTER 21 STANDBY FUNCTION Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode. Operation disabled: Operation is stopped before switching to the HALT mode. High-speed on-chip oscillator clock Low-speed on-chip oscillator clock X1 clock External main system clock...
  • Page 940 RL78/I1A CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External Subsystem...
  • Page 941 RL78/I1A CHAPTER 21 STANDBY FUNCTION Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode. Operation disabled: Operation is stopped before switching to the HALT mode. High-speed on-chip oscillator clock Low-speed on-chip oscillator clock X1 clock External main system clock...
  • Page 942 RL78/I1A CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 943 RL78/I1A CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 944: Stop Mode

    RL78/I1A CHAPTER 21 STANDBY FUNCTION 21.3.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock.
  • Page 945 RL78/I1A CHAPTER 21 STANDBY FUNCTION Table 21-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on...
  • Page 946 RL78/I1A CHAPTER 21 STANDBY FUNCTION Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode. Operation disabled: Operation is stopped before switching to the STOP mode. High-speed on-chip oscillator clock Low-speed on-chip oscillator clock X1 clock External main system clock...
  • Page 947 RL78/I1A CHAPTER 21 STANDBY FUNCTION Figure 21-3. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt request STOP instruction Note 1 Standby release signal Note 2 STOP mode release time...
  • Page 948 RL78/I1A CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address.

  • Page 949: Snooze Mode

    RL78/I1A CHAPTER 21 STANDBY FUNCTION 21.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSI00, UART0, UART4, or the A/D converter. In addition, this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. Note that the PLL output cannot be used during the case described above.
  • Page 950 RL78/I1A CHAPTER 21 STANDBY FUNCTION Table 21-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSI00/UART0 Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed On-chip Oscillator Clock (f...
  • Page 951 RL78/I1A CHAPTER 21 STANDBY FUNCTION Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode. Operation disabled: Operation is stopped before switching to the STOP mode. High-speed on-chip oscillator clock Low-speed on-chip oscillator clock X1 clock External main system clock...
  • Page 952 RL78/I1A CHAPTER 21 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 21-5. When the Interrupt Request Signal is Generated in the SNOOZE Mode STOP Trigger instruction detection Interrupt request Standby release...

  • Page 953: Chapter 22 Reset Function

    RL78/I1A CHAPTER 22 RESET FUNCTION CHAPTER 22 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit...
  • Page 954 RL78/I1A CHAPTER 22 RESET FUNCTION R01UH0169EJ0320 Rev.3.20 Sep 29, 2017...

  • Page 955: Timing Of Reset Operation

    RL78/I1A CHAPTER 22 RESET FUNCTION 22.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
  • Page 956 RL78/I1A CHAPTER 22 RESET FUNCTION Notes 1. Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use. 0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.

  • Page 957: States Of Operation During Reset Periods

    RL78/I1A CHAPTER 22 RESET FUNCTION 22.2 States of Operation During Reset Periods Table 22-1 shows the states of operation during reset periods. Table 22-2 shows the states of the hardware after receiving a reset signal. Table 22-1. Operation Statuses During Reset Period...
  • Page 958 RL78/I1A CHAPTER 22 RESET FUNCTION Note P40 becomes the following state.  P40: High-impedance during the external reset period or reset period by the POR. High level during other types of reset (connected to the internal pull-up resistor). Remark f...

  • Page 959: Register For Confirming Reset Source

    RL78/I1A CHAPTER 22 RESET FUNCTION 22.3 Register for Confirming Reset Source 22.3.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request.
  • Page 960 RL78/I1A CHAPTER 22 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 22-3. Table 22-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Reset by Reset by...
  • Page 961 RL78/I1A CHAPTER 22 RESET FUNCTION Figure 22-5. Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and store Read RESF register the value of the RESF register in any RAM. TRAP of RESF...

  • Page 962: Chapter 23 Power-On-Reset Circuit

    RL78/I1A CHAPTER 23 POWER-ON-RESET CIRCUIT CHAPTER 23 POWER-ON-RESET CIRCUIT 23.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions.  Generates internal reset signal at power on. The reset signal is released when the supply voltage (V ) exceeds the detection voltage (V Note that the reset state must be retained until the operating voltage becomes in the range defined in 32.4 or 33.4...

  • Page 963: Configuration Of Power-On-Reset Circuit

    RL78/I1A CHAPTER 23 POWER-ON-RESET CIRCUIT 23.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 23-1. Figure 23-1. Block Diagram of Power-on-reset Circuit Internal reset signal − Reference voltage source 23.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below.
  • Page 964 RL78/I1A CHAPTER 23 POWER-ON-RESET CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (1) When the externally input reset signal on the RESET pin is used Supply voltage (V Note 5 Note 5 Lower limit voltage for guaranteed operation = 1.51 V (TYP.)
  • Page 965 RL78/I1A CHAPTER 23 POWER-ON-RESET CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD interrupt & reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V Note 3...
  • Page 966 RL78/I1A CHAPTER 23 POWER-ON-RESET CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit voltage for guaranteed operation = 1.51 V ( TYP.)

  • Page 967: Chapter 24 Voltage Detector

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR CHAPTER 24 VOLTAGE DETECTOR 24.1 Functions of Voltage Detector The operation mode and detection voltages (V ) for the voltage detector is set by using the option byte LVDH LVDL (000C1H). The voltage detector (LVD) has the following functions.

  • Page 968: Configuration Of Voltage Detector

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 24-1. Figure 24-1. Block Diagram of Voltage Detector N-ch Internal reset signal LVDH LVDL INTLVI Reference Option byte (000C1H)

  • Page 969: Voltage Detection Register (Lvim)

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 970: Voltage Detection Level Register (Lvis)

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation input sets this register to 00H/01H/81H Figure 24-3.
  • Page 971 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Table 24-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (1/2) Address: 000C1H/010C1H Note VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0  LVD setting (interrupt & reset mode) Detection Voltage Option Byte Setting Value...
  • Page 972 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Table 24-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (2/2) Address: 000C1H/010C1H Note VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0  LVD off setting (use of external reset input via RESET pin)

  • Page 973: Operation Of Voltage Detector

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.4 Operation of Voltage Detector 24.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V ) by using the option byte 000C1H.
  • Page 974 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Figure 24-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.) Time Cleared...

  • Page 975: When Used As Interrupt Mode

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V ) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt mode is set.
  • Page 976 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Figure 24-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Note 2 Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.)

  • Page 977: When Used As Interrupt And Reset Mode

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.4.3 When used as interrupt and reset mode Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V LVDH LVDL by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt & reset mode is set.
  • Page 978 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Figure 24-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of V...
  • Page 979 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 24-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode.
  • Page 980 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Figure 24-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of V is V < V after releasing the mask, LVIH a reset is generated because of LVIMD = 1 (reset mode).
  • Page 981 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 24-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode.
  • Page 982 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400  s or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization.

  • Page 983: Cautions For Voltage Detector

    RL78/I1A CHAPTER 24 VOLTAGE DETECTOR 24.5 Cautions for Voltage Detector (1) Voltage fluctuation when power is supplied In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 984 RL78/I1A CHAPTER 24 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (V ) < LVD detection voltage (V ) until the time LVD reset has been generated.

  • Page 985: Chapter 25 Safety Functions

    This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in the RL78/I1A that can be used according to the application or purpose of use.  High-speed CRC: The CPU can be stopped and a high-speed check executed on its entire code flash memory area during the initialization routine.

  • Page 986: Registers Used By Safety Functions

    The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in the RL78/I1A can be used to check the entire code flash memory area during the initialization routine.

  • Page 987: Flash Memory Crc Operation Result Register

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS Figure 25-1. Format of Flash Memory CRC Control Register (CRC0CTL) Address: F02F0H After reset: 00H Symbol <7> CRC0CTL CRC0EN FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC0EN Control of CRC ALU operation Stop the operation. Start the operation according to HALT instruction execution.
  • Page 988 RL78/I1A CHAPTER 25 SAFETY FUNCTIONS <Operation flow> Figure 25-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) ; Store the expected CRC operation result Start ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ; CRC operation range setting ;...

  • Page 989: Crc Operation Function (General-Purpose Crc)

    CPU is operating. In the RL78/I1A, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program).

  • Page 990: Crc Data Register (Crcd)

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.2.2 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.

  • Page 991: Ram Parity Error Detection Function

    The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/I1A’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read.

  • Page 992: Ram Guard Function

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS Figure 25-8. Flowchart of RAM Parity Check Start of check Note RPERF = 1 RPERDIS = 1 Disable parity error reset. Check RAM. Check RAM. Read RAM. RPEF = 1 Parity error Parity error generation...

  • Page 993: Sfr Guard Function

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
  • Page 994 RL78/I1A CHAPTER 25 SAFETY FUNCTIONS Figure 25-11. Format of Invalid Memory Access Detection Control Register 1 (IAWCTL1) Address: F05C4H After reset: 00H Symbol IAWCTL1 GDPORT1 GDINT1 GDCG1 GDPORT1 Control registers of port function guard Disabled. Control registers of port function can be read or written to.

  • Page 995: Invalid Memory Access Detection Function

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.

  • Page 996: Invalid Memory Access Detection Control Register 0 (Iawctl0)

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.6.1 Invalid memory access detection control register 0 (IAWCTL0) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function.

  • Page 997: Frequency Detection Function

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (f ) and measuring the pulse width of the input signal to channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.

  • Page 998: Timer Input Select Register 0 (Tis0)

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.7.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channel 5 of timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction.

  • Page 999: A/D Test Function

    RL78/I1A CHAPTER 25 SAFETY FUNCTIONS 25.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage.
  • Page 1000 RL78/I1A CHAPTER 25 SAFETY FUNCTIONS Figure 25-16. Configuration of A/D Test Function ADISS ADS4 to ADS0 ANI0/AV REFP ANI1/AV REFM ANIxx ADTES1, ADTES0 ANIxx Temperature Note sensor Internal reference Note voltage (1.45 V) Positive reference voltage of AD converter ADREFP1...

Table of Contents