Denon AVR-X3000 Service Manual page 174

A3V56S30FTP-G6 Block Diagram
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
Chapter 2 Pin Description and Configuration
Note:This figure shows the A3V56S30FTP
The A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15
LAN8720A (HDMI:U2802)
Type Designation Code
A 3Ｖ 56 Ｓ４０F ＴＰ－G6
Revision 1.1
Speed Grade
G： Green
VDD1A
19
Package Type TP：TSOP (II)
LAN8720A/LAN8720Ai
TXN
20
Process Generation
Function Reserved for Future Use
TXP
21
Organization 2
SDR Synchronous DRAM
RXN
22
Density 56：256M bits
Interface V：LVTTL
RXP
23
Memory Style (DRAM)
Zentel DRAM
RBIAS
24
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
Figure 2.1 24-QFN Pin Assignments (TOP VIEW)
Note: When a lower case "n" is used at the beginning of the signal name, it indicates that the signal
is active low. For example, nRST indicates that the reset signal is active low.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the
buffer types is provided in
256M Single Data Rate Synchronous DRAM
75： 133MHz@CL=3
7： 143MHz@CL=3
6： 166MHz@CL=3
SMSC
24 PIN QFN
(TOP VIEW)
n
3：x8, 4：x16
VSS
Page 3 / 39
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Section 2.2.
A3V56S30FTP
A3V56S40FTP
MDIO
12
CRS_DV/MODE2
11
RXER/PHYAD0
10
VDDIO
9
RXD0/MODE0
8
RXD1/MODE1
7
Mar., 2010