Denon AVR-X3000 Service Manual page 170

VSS
Figure 1 : Logic Diagram
H27U1G8F2BTR-BC (DIGITAL:IC394)
Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device
1.2 PIN DESCRIPTION
H27U1G8F2BTR-BC Pin Function
Pin Name
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
IO0 ~ IO7
Rev 1.1 / Sep. 2009
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
ALE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE).
CHIP ENABLE
CE
This input controls the selection of the device.
WRITE ENABLE
WE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
RE
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
WP The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
READY BUSY
R/B
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
Vcc
The Vcc supplies the power for all the operations (Read, Write, Erase).
Vss GROUND
NC NO CONNECTION
NOTE :
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during
program and erase operations.
NC
Table 1 : Signal Names
1
A
NC NC
B
NC
C
D
E
F
G
H
J
K
L
NC NC
M
NC NC
1 Gbit (128 M x 8 bit) NAND Flash
Description
Table 2 : Pin Description
170
No Connection
2 3 4 5 6 7 8
ALE Vss
WP CE
WE RB
CLE
NC NC NC NC
RE
NC NC NC NC NC NC
NC NC NC NC NC NC
NC NC NC I/O5 I/O7 PRE
I/O8 I/O1 I/O10 I/O12 I/O14 Vcc
I/O9 Vcc
I/O3 I/O6 I/O15
I/O0
Vss
Vss I/O2 I/O11 I/O4 I/O13
H27U1G8F2B Series
9 10
NC NC
NC NC
1
NC NC
NC NC
5