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Cypress S6E2CC Series Manual

32-bit microcontroller fm4 family flash programming specifications
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S6E2CC/C5/C4/C3/C2/C1 Series
32-bit Microcontroller
FM4 Family
Flash Programming Specifications
Document Number: 002-04913 Rev. *D
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com

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  • Page 1 S6E2CC/C5/C4/C3/C2/C1 Series 32-bit Microcontroller FM4 Family Flash Programming Specifications Document Number: 002-04913 Rev. *D Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
  • Page 2 Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.
  • Page 3 This chapter section describes the overview and operations of the flash security. CHAPTER 3 Serial Programming Connection This chapter explains the basic configuration for serial write to flash memory by using the Cypress Serial Programmer. Sample Programs and Development Environment Cypress offers sample programs free of charge for operating the peripheral functions of the FM4 family.
  • Page 4 How to Use This Document Searching for a Function The following methods can be used to search for the explanation of a desired function in this document: Search from the table of the contents The table of the contents lists the document contents in the order of description. Search from the register The address where each register is located is not described in the text.

  • Page 5: Table Of Contents

    Contents MainFlash Memory ................................ 6 Overview ................................7 Configuration ................................. 8 Operating Description ............................13 Registers ................................42 Flash Security ................................59 Overview ................................60 Operation Explanation ............................60 Serial Programming Connection ..........................61 Serial Programmer .............................. 62 Revision History ................................... 71 Document Revision History ............................

  • Page 6: Mainflash Memory

    1. MainFlash Memory This series is equipped with 1064 KBytes to 2088 KBytes of MainFlash memory. This chapter gives an overview of, and explains the structure, operation, and registers of the MainFlash memory. This series has built-in MainFlash memory with a capacity of 1064 KBytes to 2088 KBytes that supports data erasing by all sectors of each macro, data erasing by unit of sector, and data writing by the CPU.

  • Page 7: Overview

    MainFlash Memory 1.1 Overview This series is equipped with 1064 KBytes to 2088 KBytes of built-in MainFlash memory. The built-in MainFlash memory can be erased data of sector-by-sector, all-sector of each macro batch erased data, and programmed data in units of half words (16 bits) by the Cortex-M4 CPU. This flash memory also has built-in ECC (Error Correction Code) functionality.

  • Page 8: Configuration

    MainFlash Memory 1.2 Configuration This series consists of 1064 KBytes to 2088 KBytes MainFlash memory area, a security code area, a High-Speed CR trimming data area, a HTM code area, and a general purpose data area. The MainFlash memory consists of Flash Macro #0 and Flash Macro #1.
  • Page 9 MainFlash Memory Figure 1-1 Memory Map of MainFlash Memory 1024 KB + 40 KB 0x0041_0000 0x0041_0000 SA3(#1) (8KB) 0x0040_E000 Flash SA2(#1) (8KB) Flash memory 0x0040_C000 Macro #1 40KB SA1(#1) (8KB) 0x0040_6000 0x0040_A000 SA0(#1) (8KB) General Purpose data 0x0040_8000 Flash 0x0040_4000 SA3(#0) (8KB) Macro #0 0x0040_6000...
  • Page 10 MainFlash Memory Figure 1-2 Memory Map of MainFlash Memory 1536 KB + 40 KB 0x0041_0000 0x0041_0000 SA3(#1) (8KB) 0x0040_E000 Flash Flash memory SA2(#1) (8KB) 0x0040_C000 Macro #1 40KB SA1(#1) (8KB) 0x0040_6000 0x0040_A000 SA0(#1) (8KB) General Purpose data 0x0040_8000 Flash 0x0040_4000 SA3(#0) (8KB) Macro #0 0x0040_6000...
  • Page 11 MainFlash Memory Figure 1-3 Memory Map of MainFlash Memory 2048 KB + 40 KB 0x0041_0000 0x0041_0000 SA3(#1) (8KB) 0x0040_E000 Flash Flash memory SA2(#1) (8KB) 0x0040_C000 Macro #1 40KB SA1(#1) (8KB) 0x0040_6000 0x0040_A000 SA0(#1) (8KB) General Purpose data 0x0040_8000 Flash 0x0040_4000 SA3(#0) (8KB) Macro #0 0x0040_6000...
  • Page 12 MainFlash Memory Figure 1-4 Address of Security/CR Trimming Data/HTM/General Purpose Data 0x0040_6000 0x0040_4010 General purpose data 4 area 0x0040_400C General purpose data 3 area 0x0040_4008 General purpose data 2 area 0x0040_4004 General purpose data 1 area 0x0040_4000 0x0040_2010 HTM code area 0x0040_200C 0x0040_2004 CR trimming area...

  • Page 13: Operating Description

    MainFlash Memory 1.3 Operating Description This section explains the MainFlash memory operation. 1.3.1 . MainFlash Memory Access Modes 1.3.2 . Automatic Algorithm 1.3.3 . Explanation of MainFlash Memory Operation 1.3.4 . Writing to MainFlash Memory in Products Equipped with ECC 1.3.5 .
  • Page 14 MainFlash Memory 1.3.1 MainFlash Memory Access Modes The following two access modes are available for accessing MainFlash memory from the CPU. CPU ROM mode CPU programming mode These modes can be selected by the flash access size bits (FASZR:ASZ). CPU ROM Mode This mode only allows reading of flash memory data.
  • Page 15 MainFlash Memory 1.3.2 Automatic Algorithm When CPU programming mode is used, writing to and erasing MainFlash memory is performed by activating the automatic algorithm. This section explains the automatic algorithm. 1.3.2.1. Command Sequence 1.3.2.2. Command Operating Explanations 1.3.2.3. Automatic Algorithm Run States S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev.
  • Page 16 MainFlash Memory 1.3.2.1 Command Sequence The automatic algorithm is activated by sequentially writing half-word (16-bit) data to the MainFlash memory one to six times in a row. This is called a command. Table 1-4 shows the command sequences. Table 1-4 Command sequence chart 1st Write 2nd Write 3rd Write...
  • Page 17 MainFlash Memory 1.3.2.2 Command Operating Explanations This section explains the command operating. Read/Reset Command The flash memory can be read and reset by sending the read/reset command to the target sector in sequence. When a read/reset command is issued, the flash memory maintains the read state until another command is issued. When the execution of the automatic algorithm exceeds the time limit, the flash memory is returned to the read/reset state by issuing the read/reset command.
  • Page 18 MainFlash Memory Sector Erase Suspended Command By issuing the sector erase suspended command during sector erase or during command timeout, sector erase can be suspended. In the sector erase suspended state, the read operation of memory cells of the sector not to erase is made possible.
  • Page 19 MainFlash Memory Status of Each Bit and MainFlash Memory Table 1-5 shows the correspondence between each bit of the hardware sequence flags and the status of the flash memory. Table 1-5 List of Hardware Sequence Flag States State DPOL TOGG TLOV SETI TOGG2...
  • Page 20 MainFlash Memory While write is in progress: Reads out the opposite value (inverse data) of bit7 of data written at the last command sequence (PD). This does not access the address that was specified for reading the hardware sequence flags. Note: −...
  • Page 21 MainFlash Memory During sector erase suspended When this bit is read out by specifying an address in the sector specified as sector erase: Reads out "0". When this bit is read out by specifying an address in the sector other than specified as sector erase: Reads out the value of bit5 of a specified address.
  • Page 22 MainFlash Memory [bit2] TOGG2: Toggle flag bit In the sector erase suspended state, a sector which is not the erase target can be read. However, the erase target sector cannot be read. This toggle bit flag can detect whether the corresponding sector is the erase target sector during the sector erase suspend by checking the toggle operation of the read data.
  • Page 23 MainFlash Memory 1.3.3 Explanation of MainFlash Memory Operation The operation of the MainFlash memory is explained for each command. 1.3.3.1. Read/Reset Operation 1.3.3.2. Write Operation 1.3.3.3. Flash Erase Operation 1.3.3.4. Sector Erase Operation 1.3.3.5. Sector Erase Suspended Operation 1.3.3.6. Sector Erase Restart Operation 1.3.3.1 Read/Reset Operation This section explains the read/reset operation.
  • Page 24 MainFlash Memory Figure 1-7 Example Write Operation Start of writing Set the ASZ bit of Flash access size register (FASZR) to "0b01" Read Flash access size register (FASZR) (Dummy) Write command sequence 1. Addr:000X_XAA8 Data:XXAA 2. Addr:000X_X554 Data:XX55 3. Addr:000X_XAA8 Data:XXA0 4.
  • Page 25 MainFlash Memory − Because ECC bits are added in this series, writes are always required to be performed in units of 32 bits by using two 16-bit writes. See Section "1.3.4 Writing to MainFlash Memory in Products Equipped with ECC" for details on the procedure.
  • Page 26 MainFlash Memory Figure 1-8 Example Sector Erase Procedure Start of erase Set the ASZ bit of Flash access size register (FASZR) to "0b01" Read Flash access size register (FASZR) (Dummy) Sector erase command sequence 1. Addr:000X_XAA8 Data:XXAA 2. Addr:000X_X554 Data:XX55 3.
  • Page 27 MainFlash Memory The time required to erase a sector is "(sector erase time + sector write time (preprogramming)) × number of sectors". Once the sector erase operation has finished, the flash memory returns to read/reset mode. Notes: − See Section "1.3.2 Automatic Algorithm"...
  • Page 28 MainFlash Memory 1.3.3.6 Sector Erase Restart Operation This section explains the operation for restarting sector erase during sector erase suspended. When the sector erase restart command is issued to an arbitrary address while sector erase is suspended, sector erase can be restarted. When the sector erase restart command is issued, the sector erase operation during sector erase suspended is restarted.
  • Page 29 MainFlash Memory 1.3.4 Writing to MainFlash Memory in Products Equipped with ECC This section explains the writing to MainFlash memory in products equipped with ECC. Because ECC (Error Correction Codes) are attached to each word in this series, writes need to be performed in blocks of words.
  • Page 30 MainFlash Memory 1.3.5 MainFlash Accelerator This section explains the MainFlash accelerator. This series is equipped with Flash accelerator for instruction code to achieve 0 wait at high speed operation (MAX: 200 MHz). The Flash accelerator has the following functions: 1. Prefetch Buffer Addresses will be prefetched to save the instructions in the prefetch buffer.
  • Page 31 MainFlash Memory Figure 1-9 Flash Accelerator Operating Flow (FRWTR.RWT=”0b10”) Prefetch enable Prefetch miss & Prefetch hit buffer miss 0 cycle. Prefetch 3, or 4 cycles. Buffer read Prefetch miss & buffer hit Buffer miss 1 cycle. 4 or 5 cycles. Trace Buffer Buffer hit...
  • Page 32 MainFlash Memory Figure 1-10 Flash Accelerator Operating Flow (FRWTR.RWT=”0b11”) After a reset, RWT bits in FRWTR register becomes "0b11" to enter flash accelerator mode and operate the prefetch buffer function but the trace buffer function has still been stopped. In order to activate this function, "1" must be written to BE bit in FBFCR (Flash Buffer Control Register).
  • Page 33 MainFlash Memory 1.3.6 Dual flash mode This section explains the Dual flash mode. 1.3.6.1. Configuration (Dual flash mode) 1.3.6.2. Re-Map function 1.3.6.3. Access to the DualFlash area 1.3.6.4. Setting Procedure Depending on the product, there are some restrictions on this mode. Table 1-6 In Dual Flash Mode, the Restrictions of Each Product Memory Capacity 1024 KB + 40 KB...
  • Page 34 MainFlash Memory Figure 1-11 Memory Map of MainFlash Memory 1024 KB + 40 KB in Dual Flash Mode 0x0041_0000 0x0040_8000 Flash memory 0x0040_6000 Flash General Purpose data 0x0040_8000 0x0040_4000 SA3(#0) (8KB) Macro #0 0x0040_6000 CR trimming data / HTM 0x0040_2000 Security code 0x0040_0000 0x0010_0000...
  • Page 35 MainFlash Memory Figure 1-12 Memory Map of MainFlash Memory 1536 KB + 40 KB in Dual Flash Mode 0x0041_0000 0x0040_8000 Flash memory 0x0040_6000 Flash General Purpose data 0x0040_8000 0x0040_4000 SA3(#0) (8KB) Macro #0 0x0040_6000 CR trimming data / HTM 0x0040_2000 Security code 0x0040_0000 0x0010_0000...
  • Page 36 MainFlash Memory Figure 1-13 Memory Map of MainFlash Memory 2048 KB + 40 KB in Dual Flash Mode 0x0041_0000 0x0040_8000 Flash memory 0x0040_6000 Flash General Purpose data 0x0040_8000 0x0040_4000 SA3(#0) (8KB) Macro #0 0x2020_0000 0x0040_6000 CR trimming data / HTM 0x0040_2000 SA23(#1) (64KB) 0x201F_0000...
  • Page 37 MainFlash Memory 1.3.6.2 Re-Map function When Re-Map function is enabled (DFCTRLR : RME="1"), Flash Macro #1 is assigned to the MainFlash area. In addition, Flash Macro #0 is assigned to the DualFlash area. Figure 1-14 Figure 1-15 show the address and sector structure of the MainFlash memory as well as the address of security/CR trimming data/HTM/general purpose data while Re-Map function is enabled.
  • Page 38 MainFlash Memory Figure 1-15 Address of Security/CR Trimming Data/HTM/General Purpose Data While Re-Map Function 0x200F_E000 0x200F_C010 General purpose data 4 area 0x200F_C00C General purpose data 3 area 0x200F_C008 General purpose data 2 area 0x200F_C004 General purpose data 1 area 0x200F_C000 0x200F_A010 HTM code area 0x200F_A00C...
  • Page 39 MainFlash Memory 1.3.6.3 Access to the DualFlash area The following two access modes are available for accessing the DualFlash area from the CPU. CPU ROM mode CPU programming mode These modes can be selected by the dual flash access size bits (DFASZR:DASZ). CPU ROM Mode This mode only allows reading of flash memory data.
  • Page 40 MainFlash Memory 1.3.6.4 Setting Procedure This section explains the setting procedure for the DualFlash mode. In addition, writing to the DFCTRLR register is not possible when the DualFlash mode is enabled. In order to perform writing to the DFCTRLR register again, issue a reset command. 1.
  • Page 41 MainFlash Memory 1.3.8 Cautions When Using MainFlash Memory This section explains the cautions when using MainFlash memory. If this device is reset during the write, the data that is written cannot be guaranteed. Moreover, It is necessary to prevent an unexpected reset like Watchdog Timer from occurring during the writing and deleting. If the CPU programming mode is configured (ASZ=”0b01”) in the ASZ[1:0] bits of the flash access size register (FASZR), do not execute any programs in the flash memory except the DualFlash area.

  • Page 42: Registers

    MainFlash Memory 1.4 Registers This section explains the registers. List of Registers Abbreviated Register Name Reference Register Name FASZR Flash Access Size Register 1.4.1 FRWTR Flash Read Wait Register 1.4.2 FSTR Flash Status Register 1.4.3 FSYNDN Flash Sync Down Register 1.4.4 FBFCR Flash Buffer Control Register...

  • Page 43: Frwtr Flash Read Wait Register

    MainFlash Memory 1.4.2 FRWTR (Flash Read Wait Register) This section explains the FRWTR. This register is effective when ASZ="0b10" (32-bit read mode). It configures the access method for flash memory except DualFlash area. Field Reserved Attribute Initial Value [bit7:2] Reserved bits The read values are undefined.

  • Page 44: Fstr Flash Status Register

    MainFlash Memory 1.4.3 FSTR (Flash Status Register) This section explains the FSTR. This is a status register of flash memory except DualFlash area. Field Reserved Attribute Initial Value [bit7:3] Reserved bits The read values are undefined. Ignored on write. [bit2] ERR: Flash ECC Error This bit is set to "1"...

  • Page 45: Fsyndn Flash Sync Down Register

    MainFlash Memory 1.4.4 FSYNDN (Flash Sync Down Register) This section explains the FSYNDN. The wait cycle is inserted in the read access to the flash memory at the CPU ROM mode. Current consumption can be reduced by decreasing the access clock frequency of the flash memory. Field Reserved Attribute...

  • Page 46: Fbfcr Flash Buffer Control Register

    MainFlash Memory 1.4.5 FBFCR (Flash Buffer Control Register) This section explains the FBFCR. In flash accelerator mode (RWT = “0b10”/RWT = “0b11” in FRWTR register), allowing operating FLASH Accelerator trace buffer function by this register will further improve the performance. Field Reserved Attribute...

  • Page 47: Ficr Flash Interrupt Register

    MainFlash Memory 1.4.6 FICR (Flash Interrupt Control Register) This section explains FICR. This register is used to enable the interrupt of Flash memory except DualFlash area. Field Reserved ERRIE HNGIE RDYIE Attribute Initial value [bit7:3] Reserved bits The read values are undefined. Ignored on write. [bit2] ERRIE : Flash ECC Error Interrupt Enable This bit enables ECC error correction interrupt.

  • Page 48: Fisr Flash Interrupt Status Register

    MainFlash Memory 1.4.7 FISR (Flash Interrupt Status Register) This section explains FISR. This register indicates the interrupt state of Flash memory except DualFlash area. Field Reserved ERRIF HNGIF RDYIF Attribute Initial value [bit7:3] Reserved bits The read values are undefined. Ignored on write. [bit2] ERRIF : Flash ECC Error Interrupt Flag When the generation of ECC error correction of Flash read data is detected, this bit is set to "1".

  • Page 49: Ficlr Flash Interrupt Clear Register

    MainFlash Memory 1.4.8 FICLR (Flash Interrupt Clear Register) This section explains FICLR. This register is used to clear the interrupt state of Flash memory except DualFlash area. Field Reserved ERRIC HNGIC RDYIC Attribute Initial value [bit7:3] Reserved bits The read values are undefined. Ignored on write. [bit2] ERRIC : Flash ECC Error Interrupt Clear This bit clears the ERR interrupt flag.

  • Page 50: Dfctrlr Dual Flash Mode Control Register

    MainFlash Memory 1.4.9 DFCTRLR (Dual Flash mode Control Register) This section explains DFCTRLR. This register is used to control the dual flash mode. Depending on the product, there are some restrictions on this mode. See Section "1.3.6 Dual flash mode" for details. Field WKEY Reserved...

  • Page 51: Crtrmm Cr Trimming Data Mirror Register

    MainFlash Memory 1.4.10 CRTRMM (CR Trimming Data Mirror Register) This section explains the CRTRMM. This is the mirror register of the CR trimming data. A value of this register can be used in the user mode and the serial writer mode. Field Reserved TTRMM...

  • Page 52: Fgpdm1 Flash General Purpose Data Mirror Register1

    MainFlash Memory 1.4.11 FGPDM1 (Flash General Purpose Data Mirror Register1) This section explains the FGPDM1. This is the mirror register of the general purpose data1. Field GPD1 Attribute Initial value [bit31:0] GPD1 : General Purpose Data1 After reset is released, store the bit[31:0] in an address of “0x0040_4000” (general purpose data1) of the flash memory area into this register.

  • Page 53: Fgpdm2 Flash General Purpose Data Mirror Register2

    MainFlash Memory 1.4.12 FGPDM2 (Flash General Purpose Data Mirror Register2) This section explains the FGPDM2. This is the mirror register of the general purpose data2. Field GPD2 Attribute Initial value [bit31:0] GPD2 : General Purpose Data2 After reset is released, store the bit[31:0] in an address of “0x0040_4004” (general purpose data2) of the flash memory area into this register.

  • Page 54: Fgpdm3 Flash General Purpose Data Mirror Register3

    MainFlash Memory 1.4.13 FGPDM3 (Flash General Purpose Data Mirror Register3) This section explains the FGPDM3. This is the mirror register of the general purpose data3. Field GPD3 Attribute Initial value [bit31:0] GPD3 : General Purpose Data3 After reset is released, store the bit[31:0] in an address of “0x0040_4008” (general purpose data3) of the flash memory area into this register.

  • Page 55: Fgpdm4 Flash General Purpose Data Mirror Register4

    MainFlash Memory 1.4.14 FGPDM4 (Flash General Purpose Data Mirror Register4) This section explains the FGPDM4. This is the mirror register of the general purpose data4. Field GPD4 Attribute Initial value [bit31:0] GPD4 : General Purpose Data4 After reset is released, store the bit[31:0] in an address of “0x0040_400C” (general purpose data4) of the flash memory area into this register.

  • Page 56: Dfaszr Dual Flash Access Size Register

    MainFlash Memory 1.4.16 DFASZR (Dual Flash Access Size Register) This section explains the DFASZR. In the dual flash mode (DFCTRLR:DFE=”1”), specifies the access size of DualFlash area. Field Reserved DASZ Attribute Initial Value [bit7:2] Reserved bits The read values are undefined. Ignored on write. [bit1:0] DASZ: Dual Flash Access Size Specifies the access size of the flash memory.

  • Page 57: Dfrwtr Dual Flash Read Wait Register

    MainFlash Memory 1.4.17 DFRWTR (Dual Flash Read Wait Register) This section explains the DFRWTR. In the dual flash mode (DFCTRLR:DFE=”1”), this register is effective when ASZ="0b10" (32-bit read mode). It configures the access method for the DualFlash area. Field Reserved DRWT Attribute Initial Value...

  • Page 58: Dfstr Flash Status Register

    MainFlash Memory 1.4.18 DFSTR (Flash Status Register) This section explains the DFSTR. In the dual flash mode (DFCTRLR:DFE=”1”), this is a status register of the DualFlash area. Field Reserved DFERR DFHNG DFRDY Attribute Initial Value [bit7:3] Reserved bits The read values are undefined. Ignored on write. [bit2] DFERR: Dual Flash ECC Error This bit is set to "1"...

  • Page 59: Flash Security

    2. Flash Security The flash security function protects contents of the MainFlash memory. This section describes the overview and operations of the flash security. 2.1 . Overview 2.2 . Operation Explanation S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D...

  • Page 60: Overview

    Flash Security 2.1 Overview This section explains the overview of the flash security. If the protection code of 0x0001 is written in the security code area of MainFlash memory, access to the MainFlash memory is restricted. Once the flash memory is protected, performing the flash erase operation only can unlock the function otherwise read/write access to the MainFlash memory from any external pins is not possible.

  • Page 61: Serial Programming Connection

    3. Serial Programming Connection This series supports serial onboard write (Cypress standard) to flash memory. This chapter explains the basic configuration for serial write to flash memory by using the Cypress Serial Programmer. 3.1 . Serial Programmer S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D...

  • Page 62: Serial Programmer

    Serial Programming Connection 3.1 Serial Programmer Cypress Serial Programmer (software) is an onboard programming tool for all microcontrollers with built-in flash memory. Two types of Serial Programmer are available according to the PC interface (RS-232C or USB) used. Choose the type according to your environment.
  • Page 63 Table 3-1 System Configuration of FLASH MCU Programmer Name Specifications Software FLASH MCU Programmer (In case you request the data, contact to Cypress sales representatives.) RS-232C cable Sold on the market. S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D...
  • Page 64 Serial Programming Connection Connection Example of RS-232C I/F The following shows a connection example of RS-232C I/F. When Crystal oscillator is used as the source oscillation clock Figure 3-2 shows a connection example of FS-232C I/F when a crystal oscillator is used as a source oscillation clock. When crystal oscillator is used, the communication will start with a baud rate of 115200[bps].
  • Page 65 Serial Programming Connection When external clock is used as the source oscillation clock Figure 3-3 shows a connection example of FS-232C I/F when an external clock is used as a source oscillation clock. When external clock is used, the communication will start with a baud rate of 115200[bps]. Table 3-2 shows available frequencies and communication baud rates at start-up.
  • Page 66 Serial Programming Connection When built-in high-speed CR oscillator is used as a source oscillation clock Figure 3-4 shows a connection example of FLASH MCU Programmer when a built-in high-speed CR oscillator is used as a source oscillation clock. When neither crystal oscillator nor external clock is connected to X0/X1 pins, the built-in high-speed CR oscillator is connected for communication.
  • Page 67 (In case you request the data, contact to Cypress sales representatives.) USB cable Sold on the market. For connection examples, see the manual (help section) of Cypress USB DIRECT Programmer. S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D...
  • Page 68 Serial Programming Connection Figure 3-6 Connection Example of USB I/F (Own Power Supply is Used.)) User system ● 4MHz or Serial write: “0” 48MHz 10 kΩ ● Serial write: “1” ● ● ● ● Serial write at USB Device communication 10 kΩ...
  • Page 69 Serial Programming Connection Figure 3-7 Connection Example of USB I/F (Bus Power Supply is Used.) User system 4MHz or Serial write:"0" 48MHz 10kΩ ● ● Serial write:"1" ● ● ● Serial write at USB communication Device 10 kΩ mode ● P22/SOT0_0 ●...
  • Page 70 Serial Programming Connection 3.1.2 Pins Used This section explains the used pins. Table 3-4 Pins Used for Serial Write Pins Function Supplement Performing an external reset or turning on the power after setting MD0=H and MD1=L MD0, MD1 Mode pin enters the serial write mode.

  • Page 71: Revision History

    Description of Change Change 09/30/2014 AKIH Initial release 04/25/2016 AKIH Migrated to Cypress format 06/09/2017 YSAT Adapted Cypress new logo 10/24/2017 NOSU Add a note about address notation in command sequences. Add an use case of external clock with FLASH MCU Programmer Add a note that CR trimming data will be lost when erase operation is executed to security enabled flash memory.

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