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How to Use S6J3200 Quad Flash, Traveo™ Family
This application note describes an example of system configuration and setting for using of DDR HSSPI (GDC side)
in the S6J3200 series.
Contents
1
Introduction ............................................................... 1
2
Overview .................................................................. 1
2.1
General Steps .................................................. 1
2.2
Evaluation Board Setting ................................. 2
3
DDRHSSPI Operation in Direct Mode ...................... 4
Programmer's Flowchart .................................. 4
3.1
3.2
Common Use Case in Direct Mode ................. 6
4
in Command Sequencer Mode ............................... 11
4.1
Flowchart ....................................................... 11
4.2
Example Configuration of Sampling Point ...... 13
4.3
Calibration ...................................................... 16
5
Sample Program ..................................................... 18
5.1
Erase ............................................................. 18
1
Introduction
This application note describes an example of system configuration and setting for using of DDR HSSPI (GDC side)
in the S6J3200 series.
2
Overview
2.1
General Steps
Figure 1 shows the general steps a programmer shall follow while using the DDRHSSPI.
www.cypress.com
Associated Part Family:
Figure 1. Programmer's Flowchart: General Steps
Document No. 002-04454 Rev. *B
Series Name
Product Number
S6J3200
S6J323B/3C/4B/4C/5B/5C/6B/6C
S6J327B/7C28B/8C
S6J32A9/2AA/2B9/2BA/2C9/2CA/2D9/2DA
6
Reference Documents ............................................ 20
6.1
Write .............................................................. 21
6.2
Read .............................................................. 23
A
Appendix ................................................................ 25
A.1
Sampling Coordination .................................. 25
A.2
SDATASMPTCNT/LFT/RGH ......................... 25
A.3
Flowchart in an Error Occurrence .................. 27
A.4
OK Area Calculation ...................................... 28
A.5
Abbreviations ................................................. 28
7
Document History ................................................... 29
AN204454
1
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Table of Contents
Related Manuals for Cypress Traveo S6J3200 Series
Summary of Contents for Cypress Traveo S6J3200 Series
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Page 1: Table Of Contents
This application note describes an example of system configuration and setting for using of DDR HSSPI (GDC side) in the S6J3200 series. Overview General Steps Figure 1 shows the general steps a programmer shall follow while using the DDRHSSPI. Figure 1. Programmer’s Flowchart: General Steps www.cypress.com Document No. 002-04454 Rev. *B... -
Page 2: Evaluation Board Setting
Bit1 of DIP-SW13 (BUF_1) is ON (QUAD_EN: ON Quad SPI Flash) Then, when you use S6T3J200261A208A2 and external QSPI Serial Flash ROM, please change jumper pins as below. Figure 2. Jumper Configuration for 208 Pin Evaluation Board www.cypress.com Document No. 002-04454 Rev. *B... - Page 3 How to Use S6J3200 Quad Flash, Traveo™ Family Figure 3. Evaluation Board Then, when you use S6T3J200261A216A2 and external QSPI Serial Flash ROM, please change jumper pins as below. Figure 4. Jumper Configuration for 216 Pin Evaluation Board www.cypress.com Document No. 002-04454 Rev. *B...
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Page 4: Ddrhsspi Operation In Direct Mode
More detail, please see section 4.1 of chapter 50 in S6J3200 Series Platform Hardware Manual. Programmer’s Flowchart Figure 5 shows gives the general steps which the SW shall follow while using the DDRHSSPI in Direct Mode. Figure 5. Programmer’s Flowchart: DDRHSSPI in Direct Mode of Operation www.cypress.com Document No. 002-04454 Rev. *B... - Page 5 DDRHSSPI (by resetting DDRHSSPIn_MCTRL.MEN bit to "0"). The software can check the status bit DDRHSSPIn_TXF.TSSRS to see if the current transfer has finished. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 6: Common Use Case In Direct Mode
Enable to use Quad I/O. Also FL-S mode enable to use Single and Dual Enable to use Single and Dual I/O QUAD FL-P (Non volatile) Figure 6 shows gives the Write Register follow. Figure 6. Programmer’s Flowchart: Write Register www.cypress.com Document No. 002-04454 Rev. *B... - Page 7 BE command can be accepted by the device, Write Enable (WREN) command must be issued and decoded by the device. Figure 7 shows gives the Bulk Erase follow. Figure 7. Programmer’s Flowchart: Bulk Erase www.cypress.com Document No. 002-04454 Rev. *B...
- Page 8 QUAD bit. To receive the data, Transfer protocol in DDRHSSPIn_DMTRP register is changed TX and RX mode. Figure 9 shows gives the Write Register follow. Figure 9. Programmer’s Flowchart: Write Register www.cypress.com Document No. 002-04454 Rev. *B...
- Page 9 Lock current state of BP2-0 bits in Status Register, 1 = Block Protecton and OTP locked TBPROT and FREEZE Volatile TBPARM in 0 = Block Protecton and OTP un-locked Configuration Register and OTP regions www.cypress.com Document No. 002-04454 Rev. *B...
- Page 10 Protects selected range of sectors (Block) from Block Protection Non- 0 shipped from Program or Erase Volatile if Cypress CR1[3]=0 1 = Device accepts Write Registers (WRR), program or erase commands Write Enable 0 = Device ignores Write Registers (WRR), program...
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Page 11: Ddrhsspi Operation In Command Sequencer Mode
The next step is to configure the transfer protocol (i.e. whether the DDRHSSPI serial transfers use the Quad or Octal Protocol in the DDRHSSPIn_CSCFG.MBM). The DDRHSSPIn_CSCFG.DDRMODE bits hall be set same as DDRHSSPIn_DMFIFOCFG.DDRM bit. www.cypress.com Document No. 002-04454 Rev. *B... - Page 12 With this, DDRHSSPI has been configured for accessing the memory-mapped devices. Switch the DDRHSSPI to Command Sequencer Mode, so that it starts generating the Read Command Sequences on the Serial Interface, by mapping the System Bus accesses to the memory-mapped locations. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 13: Example Configuration Of Sampling Point
If compare match about both values, you hold 0 in array variable (e.g. ddr_smpl_mapx[i]) which you make. If compare miss about both values, you hold 1 in array variable (e.g. ddr_smpl_mapx[i]) which you make. www.cypress.com Document No. 002-04454 Rev. *B... - Page 14 You check DDRHSSPIn_DLP SAMPLESTATUS register in DDR mode. You hold the result in array variable (e.g. ddr_smpl_mapx[i]) which you make. Then, increase the DDRHSSPIn_SDATA SAMPLEPTLFT/CNT/RGH value and compare again. Finally, we get the data such as following table. www.cypress.com Document No. 002-04454 Rev. *B...
- Page 15 MPLST ddr_sm pl_map 7[i] … 0 … 1 (DLPS MPLST If you finished checking all DDRHSSPIn_SDATA SAMPLEPTLFT/CNT/RGH, please go to 5. If not, please go to 3. You configure each center value to DDRHSSPIn_SDATASAMPLEPTLFT/CNT/RGH. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 16: Calibration
When you use external QSPI Serial Flash ROM, you can use DLP capability in DDR. Please calibrates when DLPERR interrupt occurs for DDR (Dual Data Rate) with DLP capability. Figure 13. Calibration and Memory Access for DDR with DLP Capability www.cypress.com Document No. 002-04454 Rev. *B... - Page 17 U s i n g N o n - D L P C a p a b i l i t y Please calibrates routinely for using Non-DLP capability. Figure 14. Calibration and Memory Access Using Non-DLP Capability www.cypress.com Document No. 002-04454 Rev. *B...
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Page 18: Sample Program
This program can be erasing about external Flash by SDR Legacy. 5 . 1 . 1 F l ow c h a r t Figure 15 shows sample program flowchart below. Figure 15. Flowchart for Sample Program for Erase www.cypress.com Document No. 002-04454 Rev. *B... - Page 19 Transfer command 01h (Write Register), then transfer 00h(Status Register-1) and 02h(Configuration Register) to set Quad bit in external Flash. Transfer 1bytes (06h) Transfer command 06h(WriteEnable) for No.5. Transfer 1bytes (C7h) Transfer command C7h(BulkErase). Note: Please confirm bit0:WIP in Status Register about end of writing. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 20: Reference Documents
S6J3200 Series 32-BIT MICROCONTROLLER Spansion Traveo Family DATA SHEET (Hereafter referred to as the "S6J3200 Series Data Sheet.") Flash Memory Manuals ® S25FL128S and S25FL256S MirrorBit Flash Non-Volatile Memory DATA SHEET (Hereafter referred to as the "S25FL128S and S25FL256S Data Sheet.") www.cypress.com Document No. 002-04454 Rev. *B... -
Page 21: Write
Sample program is configured about Direct Mode as below Table 7. Initialization in Direct Mode for SDR Quad Write Register Detail MCTRL CSEN=0b, MEN=0b DMTRP DDRM=0b, TRP=1010b PCC0 SSELDEASRT=11111b, CDRS=1111b, SS2CD =01b DMCFG SSDC=1b DMPSEL PSEL=00b DMFIFOCFG TXCTRL=1b, FWIDTH=00b MCTRL CSEN=0b, MEN=1b www.cypress.com Document No. 002-04454 Rev. *B... - Page 22 TxFIFO5 =0x00001210 [Data 10h by SDR Quad] TxFIFO6 =0x00001232 [Data 32h by SDR Quad] TxFIFO7 =0x00001254 [Data 54h by SDR Quad] TxFIFO8 =0x00001276 [Data 76h by SDR Quad] Note: Please confirm bit0:WIP in Status Register about end of writing. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 23: Read
Sample program is configured about Direct Mode as below. Table 8. Initialization in Direct Mode for SDR Quad Read Register Detail MCTRL CSEN=0b, MEN=0b DMTRP DDRM=0b, TRP=1010b PCC0 SSELDEASRT=11111b, CDRS=1111b, SS2CD =01b DMCFG SSDC=1b DMPSEL PSEL=00b DMFIFOCFG TXCTRL=1b, FWIDTH=00b MCTRL CSEN=0b, MEN=1b www.cypress.com Document No. 002-04454 Rev. *B... - Page 24 TxFIFO3 =0x00001200 [Address=00h (0xXXXX00XX) by SDR Quad] TxFIFO4 =0x00001200 [Address=00h (0xXXXXXX00) by SDR Quad] TxFIFO5 =0x000012AF [Mode bit =AFh] TxFIFO6 =0x00000010 [Dummy or sclk] TxFIFO7 =0x00000010 [Dummy or sclk] Note: Please confirm bit0:WIP in Status Register about end of writing. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 25: Appendix
(ex: When you set SDATASMPTCNT = 30, SDATASMPTLFT = 28 and SDATASMPTRGH = 32. ) More information, please see 4.2 Example Configuration of Sampling Point. The processing time is about 1.5ms by 80MHz in Flash Clock. Also, we recommend configuring in CPU startup. www.cypress.com Document No. 002-04454 Rev. *B... - Page 26 Change the SDATASMPTCNT/LFT/RGH Value When the error is occurred in error check using DLP capability, you need to change the value of SDATASMPTCNT/LFT/RGH. For example, DLPSMPLSTxL in DLPSAMPLESTATUS register is “1”, SDATASMPTCNTx/LFTx/RGHx are added “1”. www.cypress.com Document No. 002-04454 Rev. *B...
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Page 27: Flowchart In An Error Occurrence
Flowchart in an Error Occurrence Figure 21 is flowchart in the error occurrence. In this figure, we assume that we want to change value of SDATASMPTCNT/LFT/RGH during VBLANK term. Figure 21. Flowchart in an Error Occurrence www.cypress.com Document No. 002-04454 Rev. *B... -
Page 28: Example Of Setup/Hold Ok Area Calculation
Figure 22 is shown example of setup/Hold OK area calculation (HSSPI CLK = 66MHz). Figure 22. Example of Setup/Hold OK Area Calculation Abbreviations This section explains abbreviations about S6J3200 Series. Table 11. Abbreviations about S6J3200 Series Abbreviations Meaning Single Data Rate Dual Data Rate Data Learning Pattern www.cypress.com Document No. 002-04454 Rev. *B... -
Page 29: Document History
Document Number: 002-04454 Revision Orig. of Submission Description of Change Change Date KHAS 07/27/2015 Initial Release 5041950 KHAS 12/08/2015 Migrated Spansion Application Note from AN708-00013-1v0-E to Cypress format 5782386 AESATMP8 06/27/2017 Updated logo and Copyright. www.cypress.com Document No. 002-04454 Rev. *B... - Page 30 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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