Cypress S29XS128R Manual

Features
 Single 1.8 V supply for read/program/erase (1.70–1.95 V)
®
 65nm MirrorBit Technology
 Address and Data Interface Options
– Address and Data Multiplexed for reduced I/O count
(ADM) S29VS-R
– Address-High, Address-Low, Data Multiplexed for minimum
I/O count (AADM) S29XS-R
 Simultaneous Read/Write operation
 32-word Write Buffer
 Bank architecture
– Eight-bank
 Four 32-KB sectors at the top or bottom of memory array
255/127 of 128-KB sectors
 Programmable linear (8/16-word) with wrap around and
continuous burst read modes
 Secured Silicon Sector region consisting of 128 words each
for factory and customer
General Description
The Cypress S29VS256/128R and S29XS256/128R are MirrorBit
burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using multiplexed data and address pins. These products can operate up to 108 MHz and use a single V
that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered
power consumption. The S29VS256/128R operates in ADM mode, while the S29XS256/128R can operate in the AADM mode.
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (t
IA)
Max. Synch. Burst Access, ns (t
Max. Asynch. Access Time, ns (t
Max OE# Access Time, ns (t
Cypress Semiconductor Corporation
Document Number: 002-00833 Rev. *L
256/128-Mbit (32/16 Mbyte), 1.8 V, 16-bit
Data Bus, Multiplexed MirrorBit
108
72.34
6.75
BACC)
) 80
ACC
) 15
OE
• 198 Champion Court
 10-year data retention (typical)
 Cycling Endurance: 100,000 cycles per sector (typical)
 RDY output indicates data available to system
 Command set compatible with JEDEC (42.4) standard
 Hardware sector protection via V
 Handshaking by monitoring RDY
 Offered Packages
– 44-ball FBGA (6.2 mm  7.7 mm  1.0 mm)
 Low V write inhibit
CC
 Write operation status bits indicate program and erase
operation completion
 Suspend and Resume commands for Program and Erase
operations
 Asynchronous program operation, independent of burst
control register settings
 V input pin to reduce factory programming time
PP
 Support for Common Flash Interface (CFI)
®
Flash products fabricated on 65nm process technology. These
Current Consumption (typical values)
Continuous Burst Read @ 108 MHz
Simultaneous Operation @ 108 MHz
Program/Erase
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (V
Word
Effective Write Buffer Programming (V
Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
,
• San Jose CA 95134-1709
S29VS256R
S29VS128R
S29XS256R
S29XS128R
®
Flash
pin
PP
of 1.7 V to 1.95 V
CC
32 mA
71 mA
30 mA
30 µA
170 µs
) Per
CC
14.1 µs
) Per
PP
9 µs
350 ms
800 ms
• 408-943-2600
Revised May 27, 2019