Hardware Revision History - IAR SYSTEMS I-jet User Manual

Debug probes for arm cores

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User manual (28 pages)

Table Of Contents

Table of Contents

In a JTAG device that fully complies to IEEE1149.1 standard, the TDI/TMS signals

should be sampled on the rising edge of TCK, and TDO should be sent on the falling

edge of TCK. I-jet takes advantage of these requirements and changes its TDI and TMS

signals on the falling edge of TCK and samples the TDO on the rising edge of TCK.

However, to accommodate target boards with long JTAG chains and fast JTAG clocks,

I-jet allows TDO to be as late as 50 ns after the rising edge of TCK.

Note: In the adaptive mode of operation, I-jet samples the TDO on the rising edge of

RTCK rather than TCK.

This table shows the timing specifications of the JTAG port measured at the end of its

MIPI-20 cable without connection to target (VTref set to 3.3 V). The only load on the

measured signals is the oscilloscope 3.9 pF probe.

Parameter

Min

15.6 ns

tckl

15.6 ns

tckh

sod

3 ns before TCK to 50 ns

sid

after TCK

tdo

tckl

Table 1: I-jet JTAG port timing specifications

1 T

is the maximum delay from the falling edge of TCK and a valid level on the I-jet

sod

output signals, TDI and TMS. The target MCU will sample these signals on the

following rising edge of TCK and so the minimum setup time for the target, relative to

the rising edge of TCK, is T

2 T

is the minimum setup time for the TDO input signal, relative to the rising edge of

sid

TCK when I-jet samples this signal. Because the target MCU changes its TDO value on

the previous falling edge of TCK, there might not be enough time at very-high JTAG

speeds for the TDO to arrive before the positive edge of TCK. To compensate for any

TDO delays, I-jet configures itself automatically to delays introduced to the TDO by the

target board and will tolerate TDO delays of up to 50 ns after the positive edge of the

TCK.