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8.2.
Digital (Back End Section) Block Diagram
SD_USB P.C.B.
P6802
SD CARD SLOT
7
DAT0
P6801
P59301
7
DAT1
8
P6801
P59301
9
9
DAT2
P6801
P59301
5
DAT3
1
P6801
P59301
4
CLK
5
P6801
P59301
3
VBUS
P59301 P6801
12
IC59303
Vout
2
/EN
3
Vin
PW_USB1_5.1V
1
4
/OC
P59302
USB PORT2
USBDP1
3
USBDN1
2
VBUS
1
IC59306
Vout
2
/EN
3
1
Vin
PW_USB1_5.1V
/OC
4
Only for BDT110GA/GN/GW/PU/PX
IC51001
(PEAKS-PRO3)
G_SD0DAT0_A
AA24
G_SD0DAT0
G_SD0DAT1_A
Y29
G_SD0DAT1
G_SD0DAT2_A
G_SD0DAT2
Y28
G_SD0DAT3_A
G_SD0DAT3
Y27
G_SD0CLK_A
G_SD0CLK
Y26
P6803
USB PORT1
1
HOST I/F
USB0PENC
V28
USB0OVC
U29
T29
USBDP1
USBDN1
T30
USB1PENC
V29
USB1PENC
USB1OVC
V30
USB1OVC
IC59020
( ETHERNET CONTROLLER)
MDIO
MDIO
B8
18
MDC
MDC
19
A8
TXC
MII_TXCLK
A6
33
TXEN
MII
MII_TXEN
G9
34
TXD0
G10
MII_TXD0
35
TXD1
Manchester Encoder
MII_TXD1
A9
36
TXD2
MII_TXD2
B9
38
TXD3
MII_TXD3
39
C9
27 RXDV
MII_RXDV
F7
28 RXC
MII_RXCLK
G8
29 RXER
MII_RXER
B6
20 RXD3
MII_RXD3
E7
21 RXD2
MII_RXD2
D7
RXD1
MII_RXD1
C7
22
RXD0
MII_RXD0
B7
23
INTRP
MDIO_INTL
C8
32
Manchester Dcoder
RST#
PHYRSTL
47
F9
XI
CK25O
15
E9
PLL
29
4B/5B Encoder
NRZ/NRZI
Scrambler
TX+
MLT3 Encoder
10/100
12
Paraller/Serial
Pulse
Transmitter
TX-
Shaper
11
Paraller/Serial
Adapative EQ
RX+
4B/5B Encoder
Base Line
10
Clock
Descrambler
Wander Correction
Recovery
RX-
Serial/Paraller
MLT3 Decoder
9
NRZI/NRZ
Auto
Negotiation
10Base-T
Receiver
Serial/Paraller
DMP-BDT110GA/GC/GN/GT/GW
DMP-BDT110PU/PX
DIGITAL BLOCK DIAGRAM
(BACK END SECTION(1/2))
JK59001
ETHERNET JACK
1
TX+
2
TX-
RX+
4
5
RX-
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