S3.4. Digital (Back End Section) Block Diagram - Panasonic DMP-BD60GN Service Manual

S3.4. Digital (Back End Section) Block Diagram

VIDEO PB SIGNAL
AUDIO PB SIGNAL
FOR BD80 ONLY
G 768 FSA B
IC54006- 5
IC51002
(CLOCK GENERATOR)
X51002
CLK0 3
(27.000MHz)
CLK1 11
CLK2 14
6 XIN
7
XOUT
SEL_HD 16
MODE1 10
MODE2 9
SD CARD SLOT
P51602
7 DAT0 SDDAT0_A
8 DAT1 SDDAT1_A
9 SDDAT2_A
DAT2
1 SDDAT3_A
DAT3
G_SDCLK_A
5
EXCEPT BD80
+3.3V
IC51301 (8bit NAND)
64M X 8bit NAND
TC- 12 ED0-7_B
FLASH MEMORY
HOST I/F
DDR_CH0_I/F
DDR SDRAM
512Mbit
IC52002
EXCEPT BD80
IC51004
(INVERTER)
IC51001
(PEAKS-PRO2)
OUT 4
X51001
A19 CK27XI
(27.000MHz)
B19 CK27XO
IN2 2
IC51601
(EEPROM)
5
SDA W30 SDA0
SCL 6
V31 SCL0
A11 A01DACCK
D20 AEXCKA
E20 CK74A
C18 VSELA
B18 ASEL0A
A18 ASEL1A
X51003
AL34 CK33XI
(33.000MHz)
AL33 CK33XO
X51004
Y31 CK24XI
(24.000MHz)
Y32 CK24XO
SDDAT0_A
AG34
SDDAT0
SDDAT1_A
AF32 SDDAT1
SDDAT2_A
AJ34 SDDAT2
SDDAT3_A
AH33 SDDAT3
G_SDCLK_A
AH34 SDCLK
QR51002,
IC51003
QR51003,
(RESET)
QR51004
E32
RESET XTRST
5 VDD 4
VOUT
DRIVE
T34 XRST
IC57001
(TIMER)
QR51001
RESET
51
XRES BP
DRIVE
DDR_CH1_I/F
DDR SDRAM DDR SDRAM
512Mbit 512Mbit
IC52001 IC52201 IC52202
TC- 1 PRMC0-11_B
VIDEO
TC- 2 PRMY0-11_B
AUDIO TC- 3 G_HDI_D0-3_B
G_HDI_IEC_B
C10
AOIIEC
G_SDA3_B
SDA3
U31
G_SCL3_B
SCL3 R33
IC57001
(TIMER)
XINTM(TBUS)
29
T33 22 XINTM_OUT
XCIN TM
V30
XCIN TP 23 XINTP_OUT
XCMPREQ T32 30 XMPREQ(TBUS)
IC51603
(HIGH SIDE SWITCH)
USB BUSP EN V34 1 EN VIN 4
USB BUSP EN W32 3 FLG VOUT 5
AA33
USBDN
USBDP AA34
IC59001
(10M/ 100M ETHERNET CONTROLLER)
RXD3
MII RXD3 K2 20
RXD2
PCI
MII RXD2 J2 21
RXD1
INTERFACE,
MII RXD1 J1 22
RXD0
TRANSMIT/
MII RXD0 J3 23
TXD0 RECEIVE
MII TXD0 G4 35
LOGIC
TXD1
MII TXD1 H5 36
INTERFACE
TXD2
MII TXD2 F4 38
TXD3
MII TXD3 G5 39
DDR SDRAM
512Mbit
S-6
IC56036 (HDMI TRANSMITTER)
TX2+
TX2-
VIDEO
TX1+
DATA PANEL LINK
4:2:2 O X
TX1-
CAPTURE/ TMDS
to S O
TX0+
DEGEN./ DIGITAL
4:4:4 C R TX0-
656 LOGIC CORE
TXC+
BLOCK
TXC-
TST
96
HCLKIN
AUDIO DATA
CAPTURE/
LOGIC
BLOCK
HDCP HDCP
KEYS
POTION
REGISTERS
AMRX
EEPRO
ENGINE
35
HSDA
CONFIGURATION DSD
116 I2C E-DDC
LOGIC BLOCK
DSCL
113 SLAVE MASTER
HSCL
Q56001,
Q56004
Q56005
HDMI_MONI
28 BUFFER BUFFER
(CEC_IN)
Q56002
Q56003
HDMI_CEC_OUT 26 SWITCHING
HDMI_P_ON 55
IC56001
(REGULATOR +5V)
VOUT 4
1 ON
VIN 5
IC51602
(REGULATOR)
VIN 1 X SW +5.8V
3 VOUT
P STANDBY
ON 2
P51603
(USB JACK)
1
2
3
100M
TX+
PARALLEL 12
DECODER,
TO SERIAL, TX-
DE-SCRAMBLER
11
TRANSMIT
10/ 100
SWITCH
LOGIC
RX+
SERIAL TO 10
ENCODER,
RX-
PARALLEL,
SCRAMBLER
9
RECEIVE
10M
10M OUTPUT WAVEFORM SHAPING
RECEIVE LOW PASS FILTER
DMP-BD60GN/GA/GC/GZ/PU,
DMP-BD80GN
Digital Block Diagram
(Back End Section)
HDMI JACK
JK56001
25 1 D2+
23 3 D2-
L56007
21 4
D1+
19 6
D1-
17 7
D0+
15 9
D0-
L56008
13 10 CLK+
11 12 CLK-
13 CEC
18 +5V
119 16 HDMISDA
120 15
HDMISCL
X SW +5.8V
H FROM
IC57001- 42 TIMER BLOCK
ETHERNET
JACK
JK59001
1 TX+
2
TX-
RX+
4
5 RX-