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11.3. Digital P.C.B. Block Diagram (1/2)
IC8202
CHIP CHANNEL RECEIVER
TS_SYNC
IF_P_M
PS8701
P8203
29
ADC_IP
8
IF_N_M
PS8701
P8203
30
ADC_IN
9
TS_DATA
SCL_M_OF
PS8701
P8203
SCL_MAST
34
14
SDA_M_OF
PS8701
P8203
33
SDA_MAST
SDA_HOST
13
SCL_HOST
RESETB
TO
TUNER P.C.B.
IC8204
CHIP CHANNEL RECEIVER
SDA_HOST
SCL_HOST
IF_N_S
PS8701
P8203
ADC_IN
30
3
RESETB
IF_P_S
PS8701
P8203
ADC_IP
29
4
SCL_S_OF
PS8701
P8203
TS_SYNC
SCL_MAST
34
11
SDA_S_OF
PS8701
P8203
SDA_MAST
33
12
TS_DATA
IC51301
(8bit NAND)
64M X 8bit NAND
FLASH MEMORY
IC51001
(HD DEC/ ENC/ CPU/ GFX
G_CH0PSYNC
8
A26
CH0PSYNC
G_CH0VAL
TS_VAL
7
C26
CH0VAL
CKG_CH0CLK
TS_CLK
9
B25
CH0CLK
G_CH0DATA
11
B26
CH0DATA
G_SDA1_B
4
G_SCL1_B
5
XFERSTB
22
G_SDA1_B
4
E26
SDA1
G_SCL1_B
5
F26
SCL1
XFERSTB
22
D26
XFERST
G_CH1PSYNC
8
C28
CH1PSYNC
G_CH1VAL
TS_VAL
7
B28
CH1VAL
CKG_CH1CLK
TS_CLK
9
A27
CH1CLK
G_CH1DATA
11
C27
CH1DATA
TC- 1 BUS_ED0-7_B
Process
/DDR3-IF/RTSC/AV Core/Graphics)
MM0CK
B12
MM0XCK
A12
MM1CK
K3
MM1XCK
K2
USB1DN
AF32
V33
AG33
V33
USB1DP
USB2DN
AP11
USB2DP
AN11
USB0DN
AF34
USB0DP
AF33
IC59001
( ETHERNET CONTROLLER)
11 MDIO
MDIO
AP31
12 MDC
MDC
AP33
22 TXC
RGMII_TXCLK
AL33
HOST I/F
23 TXEN
RGMII_TXCTL
AK31
24 TXD0
MII_TXD0
AM33
25 TXD1
MII_TXD1
AM32
26 TXD2
MII_TXD2
AM34
27 TXD3
MII_TXD3
AL33
HOST I/F
18 RXDV
RGMII_RXCTL
AK31
RGMII_RXCLK
AK33
19 RXC
MII_RXER
20 RXER
AN32
13 RXD3
MII_RXD3
AK34
14 RXD2
MII_RXD2
AJ34
RXD1
MII_RXD1
15
AJ33
MII_RXD0
AJ32
16
RXD0
21 INTRP
MDIO_INTL
AP32
XETH_RST
AG29
10 REXT
79
IC52000
MM0DQ 0-15, MM0A0-14
DDR SDRAM
1Gbit
J7
CK
K7
/CK
IC52001
J7
CK
/CK
K7
DDR SDRAM
1Gbit
MM0DQ 16-31, MM0A 0-14
IC52203
MM1DQ 0-15, MM1A 0-13
DDR SDRAM
1Gbit
J7
CK
/CK
K7
P59304
3
P59304
2
P59302
3
2
PW_5V_VBUS_2
1
JK59001
ETHERNET JACK
TX+
TXP
7
TX-
TXM
6
RX+
5
RXP
RX-
RXM
4
DMR-PWT550GL/GZ
DIGITAL BLOCK DIAGRAM(1/2)
VIDEO REC SIGNAL
VIDEO EE SIGNAL
VIDEO PB SIGNAL
AUDIO REC SIGNAL
AUDIO EE SIGNAL
AUDIO PB SIGNAL
WIRELESSUSB
MODULE
DP
DN
VBUS
8
9
2
TX+
3
TX-
RX+
4
5
RX-
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