Digital (Back End Section) Block Diagram - Panasonic DMP-BD45GA Service Manual

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6.4.

Digital (Back End Section) Block Diagram

X51001
(27MHz)
X51003
(33MHz)
P51602
SD CARD SLOT
DAT0
7
SDDAT0_B
DAT1
SDDAT1_B
8
DAT2
SDDAT2_B
9
DAT3
1
SDDAT3_B
CLK
5
G_SDCLK_B
IC51702
Vin
PW_USB5V
1
/OC
Vout
P51701
2
USB PORT
1
2
T51701
3
only for BD45PU/65GN/65PU/65PX
IC51301
(8bit NAND)
64M X 8bit NAND
TC-
12
ED0-7_B
FLASH MEMORY
IC52002
TC-
4
C0A0-12_B
DDR SDRAM
1Gbit
TC-
6
C0DQ0-15_A
TC-
5
C0A0-12_B
DDR SDRAM
1Gbit
TC-
7
C0DQ16-31_A
IC52001
IC52201
TC-
8
C0A0-12_B
DDR SDRAM
512Mbit
TC-
10
C0DQ0-15_A
TC-
9
C0A0-12_B
DDR SDRAM
512Mbit
TC-
11
C0DQ16-31_A
IC52202
IC51001
(PEAKS-PRO2)
B19 CK27XO
A19 CK27XI
AL34 CK33XI
AL33 CK33XO
AG34 SDDAT0
AF32 SDDAT1
AJ34 SDDA T2
AH33 SDDAT3
AH34 SDCLK
4
W32 SBI1
EN
3
V34 SBO1
AA33 USBDN
AA34 USBDP
HOST I/F
IC56036
(HDMI TRANSMITTER)
TC-
1
PRMC0-11_B
VIDEO
TC-
2
PRMY0-11_B
Color
Video
VSYNC
Space
VO1VSYNC
B6
83
I/F
Converter
HSYNC
VO1HSYNC
B5
84
PCLKIN
VO1CLK
A2
121
AUDIO
TC-
3
G_HD1_D0-3_B
AMRX
AO1IEC
C10
35
Audio
AMDWS
AO1LRCK
C12
36
I/F
AMDACL
AO1BCK
D11
39
AMDAM
41
AO1DACCK
A11
HCLK
Clock
96
Gen1
HSDA
SDA3
U31
116
1
I2C
Configuration
HSCL
I/F
R33
113
1
SCL3
Register
NIRQ
XIRQ8
D2
112
IC57001
(TIMER)
29
XINTM(TBUS)
XCINTM
XINTM_OUT
T33
22
XINTP_OUT
XCINTP
V30
23
XCMPREQ
XMPREQ(TBUS)
T32
30
TBUS_TXD
CSBPTM
U34
15
TBUS_RXD
CSBMTP
V32
16
TBUS_CLK
CSCLK
U33
17
51 XRES_BP
XRST
T34
XTRST
AE32
57 BP_STATE
XSRST
AC30
IC59001
(10M/100M ETHERNET CONTROLLER)
MDIO
MDIO
K1
18
MDC
MDC
J5
19
TXC
MII_TXCLK
H4
33
TXEN
MII
MII_TXEN
G2
34
TXD0
MII_TXD0
35
G4
TXD1
Manchester Encoder
MII_TXD1
H5
36
TXD2
MII_TXD2
F4
38
TXD3
MII_TXD3
G5
39
27 RXDV
MII_RXDV
H2
28 RXC
MII_RXCLK
J4
29 RXER
MII_RXER
H1
20 RXD3
MII_RXD3
K2
21 RXD2
MII_RXD2
J2
RXD1
MII_RXD1
J1
22
RXD0
MII_RXD0
J3
23
INTRP
MDIO_INTL
32
H3
Manchester Dcoder
RST#
PHYRSTL
F3
47
23
AUDIO SIGNAL
VIDEO SIGNAL
TX2P
25
TX2M
23
TX1P
21
HDCP
TMDS
TMDS
TX1M
19
Cipher/
Encoder
Transmitter
TX0P
Encrytor
17
TX0M
15
TXCP
13
AV
TXCM
Controller
11
SDA
Authentication
DDC
119
1
SCL
Key Exchange
I/F
120
1
HPD
118
Q56001,
Q56005
Q56004
HDMI_MONI
28
BUFFER
BUFFER
(CEC_IN)
Q56002
Q56003
HDMI_CEC_OUT
26
SWITCHING
IC56001
(REG.+5V)
VOUT
4
55
ON
HDMI_P_ON
1
VIN
PW_5.9V
5
4B/5B Encoder
NRZ/NRZI
Scrambler
TX+
MLT3 Encoder
10/100
Paraller/Serial
Pulse
Transmitter
TX-
Shaper
Paraller/Serial
Adapative EQ
RX+
4B/5B Encoder
Base Line
Clock
Descrambler
Wander Correction
Recovery
RX-
Serial/Paraller
MLT3 Decoder
NRZI/NRZ
Auto
Negotiation
10Base-T
Receiver
Serial/Paraller
DMP-BD45GA/GC/GN/GT/GW/PU
DMP-BD65GN/PU/PX
DIGITAL BLOCK DIAGRAM
(BACK END SECTION)
JK56001
HDMI JACK
D2+
1
3
D2-
L56007
4
D1+
D1-
6
7
D0+
9
D0-
L56008
10
CLK+
CLK-
12
16
HDMISDA
15
HDMISCL
CEC
13
19
HOTPLG
18
+5V
only for BD65GN/PU/PX
JK59001
ETHERNET JACK
12
1
TX+
11
2
TX-
RX+
10
4
9
5
RX-

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