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Rohm LAPIS Semiconductor ML620Q151B User Manual

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FEUL620Q150B-05
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
User's Manual
Rev.5
Issue Date: Oct.10, 2019

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Summary of Contents for Rohm LAPIS Semiconductor ML620Q151B

  • Page 1 FEUL620Q150B-05 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User’s Manual Rev.5 Issue Date: Oct.10, 2019...
  • Page 2 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
  • Page 3 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Preface This manual describes the operation of the hardware of the 16-bit microcontroller ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B. The following manuals are also available. Read them as necessary.  nX-U16/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U16/100 Core ...
  • Page 4 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Notation Classification Notation Description  Numeric value xxh, xxH Indicates a hexadecimal number Indicates a binary number  Unit word, W 1 word = 16 bits byte, B 1 byte = 8 bits nibble, N 1 nibble = 4 bits mega-, M kilo-, K = 1024...

  • Page 5: Table Of Contents

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents Contents Chapter 1 Overview ................................. 1-1 Features ............................... 1-1 Configuration of Functional Blocks ......................1-4 1.2.1 Block Diagram ............................1-4 Pins ................................1-7 1.3.1 Pin Layout .............................. 1-7 1.3.1.1 Pin Layout of package ........................1-7 1.3.2 List of Pins ............................
  • Page 6 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 4.3.3.1 Stop mode when the CPU runs with low-speed clock ..............4-12 4.3.3.2 Stop mode when the CPU runs with high-speed clock ..............4-16 4.3.3.3 Note on Return Operation from STOP/HALT Mode ..............4-20 4.3.4 Block control Function ........................4-21 Chapter 5 Interrupts (INTs) ..............................
  • Page 7 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 6.2.1 List of Registers ............................. 6-4 6.2.2 Frequency Control Register 0(FCON0) ....................6-5 6.2.3 Frequency Control Register 1 (FCON1) ....................6-6 6.2.4 Frequency Control Register 3 (FCON3) ....................6-7 6.2.5 Frequency Status Register (FSTAT) ...................... 6-9 Description of Operation ...........................
  • Page 8 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 9.2.3 16bit timer 9 data register L,H (TMH9DL,H) ..................9-4 9.2.4 16bit timer A data register L,H (TMHADL,H) ..................9-5 9.2.5 16bit timer B data register L,H (TMHBDL,H) ..................9-6 9.2.6 16bit timer 8 counter register L,H (TMH8CL,H) .................. 9-7 9.2.7 16bit timer 9 counter register L,H (TMH9CL,H) ..................
  • Page 9 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 11.2.26 PWM6 control register 2 (PW6CON2)....................11-38 11.2.27 PWM6 control register 3 (PW6CON3) ..................... 11-40 11.2.28 PWM6 control register 4 (PW6CON4) ..................... 11-41 11.2.29 PWM6 control register 5 (PW6CON5) ..................... 11-42 11.2.30 PWM6 control register 6 (PW6CON6) ..................... 11-43 11.2.31 PWM7 period register L, H (PW7PL, PW7PH) ................
  • Page 10 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO/ ”Slave mode” ........................ 12-12 Chapter 13 13. UART ................................13-1 13.1 Genral Description ............................. 13-1 13.1.1 Features ..............................13-1 13.1.2 Configuration ............................13-1 13.1.3 List of Pins ............................
  • Page 11 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 14.3.1.2 Restart Condition .......................... 14-11 14.3.1.3 Slave Address Transmit Mode ..................... 14-11 14.3.1.4 Data Transmit Mode ........................14-11 14.3.1.5 Data Receive Mode ........................14-11 14.3.1.6 Control Register Setting Wait State ....................14-11 14.3.1.7 Stop Condition ..........................14-11 14.3.2 Communication Operation Timing ....................
  • Page 12 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 18.1.1 Features ..............................18-1 18.1.2 Configuration ............................18-2 18.1.3 List of Pins ............................18-3 18.2 Description of Registers ..........................18-4 18.2.1 List of Registers ........................... 18-4 18.2.2 Port 3 Data Register (P3D) ........................18-5 18.2.3 Port 3 Direction Register (P3DIR) ....................... 18-7 18.2.4 Port 3 control registers 0, 1 (P3CON0, P3CON1) ................
  • Page 13 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 21.3.2 Secondary, Tertiary, and Quaternary Functions ................. 21-11 Chapter 22 22. Port 7 ................................22-1 22.1 Genral Description ............................. 22-1 22.1.1 Features ..............................22-1 22.1.2 Configuration ............................22-1 22.1.3 List of Pins ............................22-2 22.2 Description of Registers ..........................22-3 22.2.1 List of Registers ...........................
  • Page 14 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 24.2.19 SA-ADC Result Register 8H (SADR8H)................... 24-12 24.2.20 SA-ADC Result Register 9L (SADR9L) ................... 24-13 24.2.21 SA-ADC Result Register 9H (SADR9H)................... 24-13 24.2.22 SA-ADC Result Register AL (SADRAL) ..................24-14 24.2.23 SA-ADC Result Register AH (SADRAH) ..................24-14 24.2.24 SA-ADC Result Register BL (SADRBL) ..................
  • Page 15 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Contents 29. Flash Memory Rewrite Function ........................29-1 29.1 Genral Description ............................. 29-1 29.1.1 Features ..............................29-1 29.2 Description of Registers ..........................29-2 29.2.1 List of Registers ........................... 29-2 29.2.2 Flash Address Register L,H (FLASHAL,H) ..................29-3 29.2.3 Flash Data Register L,H (FLASHDL,H)....................

  • Page 16: Overview

    Chapter 1 Overview...

  • Page 17: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1. Overview 1.1 Features This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as A/D converter, timer, PWM, synchronous serial port, UART, I C bus interface, Low level detect circuit (LLD), are incorporated around 16-bit CPU nX-U16/100.
  • Page 18 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview  - 16 bits x 4ch - Continuousmode / One shot mode - Timer start-stop function by the software and an external trigger. - A pulse width can be measured using an external-trigger input. - An external event can be selected as the counter clock.
  • Page 19 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview  LLD(Low Level Detector) function - Threshold voltages: 4values (1.9V/2.55V/3.7V/4.2V) A threshold voltage is selected as Code-Option. - LLD is a ready as a supply-voltage supervisory reset. Reset or an interrupt output is selectable as Code-Option. ...

  • Page 20: Configuration Of Functional Blocks

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1.2 Configuration of Functional Blocks 1.2.1 Block Diagram Figure 1-1 shows a block diagram of ML620Q151B/ML620Q152B/ML620Q153B(TQFP48). "*" indicates the secondary, tertiary, or quartic function of each port. CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing...
  • Page 21 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Figure 1-2 shows a block diagram of ML620Q154B/ML620Q155B/ML620Q156B(TQFP52). "*" indicates the secondary, tertiary, or quartic function of each port. CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing Memory Controller (FLASH) Instruction Instruction 32/48/64Kbyte Controller On-Chip...
  • Page 22 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Figure 1-3 shows a block diagram of ML620Q157B/ML620Q158B/ML620Q159B(QFP64/TQFP64). "*" indicates the secondary, tertiary, or quartic function of each port. CPU (nX-U16/100) EPSW1～3 ELR1～3 ECSR1～3 GREG 0～15 DSR/CSR Program Timing Memory Controller (FLASH) Instruction Instruction 32/48/64Kbyte Controller On-Chip...

  • Page 23: Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1.3 Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of package Figure 1-4 shows a pin layout of ML62Q151B/ML620Q152B/ML620Q153B TQFP48 package. P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P01/EXI1/PW67EV0 P56/SCK0 P02/EXI2/RXD0 P55/TXD0/SIN0/TXD1 P03/EXI3/RXD1 P54/RXD0 P04/EXI4 P47/AIN11/T16CK1/PWM5 (TOP VIEW) P20/LED0/LSCLK/PWM4 P46/AIN10/T16CK0/SOUT0 TQFP48 P21/LED1/OUTCLK/PWM5 P45/AIN9/T1P5CK/SCK0...
  • Page 24 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Figure 1-5 shows a pin layout of ML62Q154B/ML620Q155B/ML620Q156B TQFP52 package. P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P56/SCK0 P01/EXI1/PW67EV0 P55/TXD0/SIN0/TXD1 P02/EXI2/RXD0 P03/EXI3/RXD1 P54/RXD0 P53/TXD1/PWM6 P04/EXI4 P47/AIN11/T16CK1/PWM5 P05/EXI5 (TOP VIEW) P46/AIN10/T16CK0/SOUT0 P20/LED0/LSCLK/PWM4 TQFP52 P21/LED1/OUTCLK/PWM5 P45/AIN9/T1P5CK/SCK0 P44/AIN8/T0P4CK/SIN0 P22/LED2/TMHAOUT/PWM6 P23/LED3/TMHBOUT/PWM7 P43/AIN7/TXD0/PWM4/TXD1 P42/AIN6/RXD0/SOUT0 P14/TEST0 P41/SCL/SCK0/CMP0P RESET_N...
  • Page 25 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Figure 1-6 shows a pin layout of ML62Q157B/ML620Q158B/ML620Q159B QFP64/TQFP64 package. P00/EXI0/PW45EV0 P57/SOUT0/PWM7 P01/EXI1/PW67EV0 P56/SCK0 P02/EXI2/RXD0 P55/TXD0/SIN0/TXD1 P03/EXI3/RXD1 P54/RXD0 P04/EXI4 P53/TXD1/PWM6 P52/RXD1/SOUT0 P05/EXI5 P20/LED0/LSCLK/PWM4 P51/SCL/SCK0 P21/LED1/OUTCLK/PWM5 P50/SDA/SIN0 P22/LED2/TMHAOUT/PWM6 P47/AIN11/T16CK1/PWM5 (TOP VIEW) P46/AIN10/T16CK0/SOUT0 QFP64/TQFP64 P72/RXD1/SIN0 P45/AIN9/T1P5CK/SCK0 P73/TXD1/SCK0/TXD0 P44/AIN8/T0P4CK/SIN0 P74/SOUT0...

  • Page 26: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1.3.2 List of Pins Table 1-1 shows the list of pins.  " " in the I/O column indicates the power supply pin, "I" indicates the input pin, "O" indicates the output pin, and "I/O" indicates the input/output pin.
  • Page 27 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription Input/output port / P33/ PW67EV0 input / PW67EV0          Successive approximation type AIN3 ADC input...
  • Page 28 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription UART1 PWM6     Input/output port TXD1 data PWM6 output output UART0     ...
  • Page 29 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Primary function Secondary function Tertiary function Quaternary function Description name name scription name scription name scription SSIO0 synchron UART1    Input/output port TXD1 O data SCK0 clock output input/out UART0 SSIO0  ...

  • Page 30: Pin Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1.3.3 Pin Descriptions Table 1-2 shows the pin descriptions.  " " in the I/O column indicates the power supply pin, "I" indicates the input pin, "O" indicates the output pin, and "I/O" indicates the input/output pin. Table 1-2 Pin Descriptions (1/3) Primary/ Secondary/...
  • Page 31 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Table 1-2 Pin Descriptions (2/3) Primary/ Secondary/ Pin name Description Logic Tertiary/ Quaternary UART TXD0* Secondary UART0 data output pin. Allocated to the secondary function of the P43, Positive P55 , P87 and the quaternary of the P73. Quaternary UART0 data input pin.
  • Page 32 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview Table 1-2 Pin Descriptions (3/3) Primary/ Pin name Description Logic Secondary External interrupt External maskable interrupt input pins. The interrupt is enabled and EXI0～7* Positive/ interrupt edge is selectable by the software for each bit. Allocated to the Primary Negative primary function of the P00 to P05 and P30 to P31.

  • Page 33: Handling Of Unused Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 1 Overview 1.3.4 Handling of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Termination of Unused Pins Recommended pin termination RESET_N open P14/TEST0 open TEST1_N open Connect to V P00 to P05* Connect V or V P12*...

  • Page 34: Cpu And Memory Space

    Chapter 2 CPU and Memory Space...

  • Page 35: Genral Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space CPU and Memory Space 2.1 General Description This LSI includes 16-bit CPU nX-U16/100 and the memory model is SMALL model. For details of the CPU nX-U16/100, see “nX-U16/100 Core Instruction Manual”. 2.2 Program Memory Space The program memory space is used to store program codes, table data (ROM window), or vector tables.
  • Page 36 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 0:0000H Vector table area Program code ROM window area 0:00FFH 0:0100H Program code ROM window area 0:0BBFFH 0:0BC00H Test data area 0:0BFFFH 8bit Figure 2-2 Configuration of ML620Q152B/ML620Q155B/ML620Q158B Program Memory Space (48-Kbyte) [Note] ・...
  • Page 37 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space CSR:PC Segment 0 0:0000H Vector table area Program code ROM window area 0:00FFH 0:0100H Program code ROM window area 0:0FBFFH 0:0FC00H Test data area 0:0FFFFH 8bit Figure 2-3 Configuration of ML620Q153B/ML620Q156B/ML620Q159B Program Memory Space (64-Kbyte) [Note] ・...

  • Page 38: Data Memory Space

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space 2.3 Data Memory Space The data memory space of this LSI consists of the ROM window area of Segment 0, 2KByte RAM area, SFR area, the data flash area of segment 7, and ROM reference area of segment 8 and data flash reference area of segment F. The data memory has the 8-bit length and is specified by a 4-bit Data Segment Register (DSR) and 16-bit addressing instructions.
  • Page 39 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space Segment 0 Segment 7 DSR: Data address DSR: Data address 0:0000H 7:0000H Data Flash area 7:07FFH (2K Byte) ROM Window area 0:0BC00H Test data area 0:0BFFFH 0:0C000H Unused area Unused area 0:0DFFFH 0:0E000H RAM are...
  • Page 40 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space Segment 0 Segment 7 DSR: Data address DSR: Data address 0:0000H 7:0000H Data Flash area 7:07FFH (2K Byte) ROM Window area Unused area 0:0DFFFH 0:0E000H RAM are 0:0E7FFH (2K Byte) Unused area 0:0F000H SFR area 0:0FFFFH...

  • Page 41: Instruction Length

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 2 CPU and Memory Space 2.4 Instruction Length The length of an instruction is 16 bits. 2.5 Data Type The data types supported include byte (8 bits) and word (16 bits). 2.6 Description of Registers 2.6.1 List of Registers Address Name Symbol (Byte)

  • Page 42: Reset Function

    Chapter 3 Reset Function...

  • Page 43: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 3 Reset Function Reset Function 3.1 General Description This LSI has the five reset functions. If any of the four reset conditions is satisfied, this LSI enters system reset mode.  Reset by the RESET_N pin ...

  • Page 44: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  0F00CH Reset status register RSTAT Undefined 3.2.2 Reset Status Register (RSTAT) Address: 0F00CH Access: R/W Access size: 8 bits Initial value: Undefined ―...
  • Page 45 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 3 Reset Function  RSTR (bit 6) The RSTR bit is a flag that indicates that the RESET_N pin reset is generated. This bit is set to “1” when the RESET_N pin reset is generated. RSTR Description RESET_N pin reset is not generated RESET_N pin reset is generated...

  • Page 46: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all processings and any other processing will be cancelled. The system reset mode is set by any of the following causes. •...

  • Page 47: Mcu Control Function

    Chapter 4 MCU Control Function...

  • Page 48: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function MCU Control Function 4.1 General Description The operating states of this LSI are classified into the following 4 modes including system reset mode: (1) System reset mode (2) Program run mode (3) HALT mode (4) STOP mode For the System reset mode, see Chapter 3, "Reset Function".

  • Page 49: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2 Description of Registers 4.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F008H Stop code acceptor STPACP 0F009H Standby control register SBYCON 0F068H Block control register 0 BLKCON0 0F06AH Block control register 2...

  • Page 50: Stop Code Acceptor (Stpacp)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: 00H STPACP Initial value STPACP is a write-only special function register (SFR) which enables for entering a STOP mode. When STPACP is read, “00H”...

  • Page 51: Standby Control Register (Sbycon)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H SBYCON Initial value SBYCON is a special function register (SFR) to control the operation mode of MCU. [Description of Bits] ...

  • Page 52: Block Control Register 0 (Blkcon0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0 (BLKCON0) Address: 0F068H Access: R/W Access size: 8 bits Initial value: 00H BLKCON0 DTM1 DTM0 Initial value BLKCON0 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 53: Block Control Register 2 (Blkcon2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 2 (BLKCON2) Address: 0F06AH Access: R/W Access size: 8 bits Initial value: 00H BLKCON2 DI2C0 DUA1 DUA0 DSIO0 Initial value BLKCON2 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 54: Block Control Register 3 (Blkcon3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 3 (BLKCON3) Address: 0F06BH Access: R/W Access size: 8 bits Initial value: 00H BLKCON3 DCMP Initial value BLKCON3 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 55: Block Control Register 4 (Blkcon4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 4 (BLKCON4) Address: 0F06CH Access: R/W Access size: 8 bits Initial value: 00H BLKCON4 DSAD Initial value BLKCON4 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 56: Block Control Register 6 (Blkcon6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.8 Block Control Register 6 (BLKCON6) Address: 0F06EH Access: R/W Access size: 8 bits Initial value: 00H BLKCON6 DTMB DTMA DTM9 DTM8 Initial value BLKCON6 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 57: Block Control Register 7 (Blkcon7)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.2.9 Block Control Register 7 (BLKCON7) Address: 0F06FH Access: R/W Access size: 8 bits Initial value: 00H BLKCON7 DPW7 DPW6 DPW5 DPW4 Initial value BLKCON7 is a special function register (SFR) to control each block operation. [Description of Bits] ...

  • Page 58: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.3 Description of Operation 4.3.1 Program Operating Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, or WDT overflow reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released.

  • Page 59: Stop Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode During the STOP mode, the low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the entering the STOP mode is enabled by successively writing “5nH” and “0AnH” (where n is 0 to 0FH) to the stop code acceptor (STPACP) and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered.
  • Page 60 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-3 shows the operation waveform in STOP mode when CPU operates with the low-speed clock (when the low-speed RC oscillation is selected for low-speed by the code option and the high-speed RC oscillation is selected for high-speed).
  • Page 61 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-5 shows the operation waveform in STOP mode when CPU operates with the low-speed clock (when the low-speed crystal oscillation is selected for low-speed by the code option and the high-speed RC oscillation is selected for high-speed).
  • Page 62 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-6 shows the operation waveform in STOP mode when CPU operates with the low-speed clock (when the low-speed crystal oscillation is selected for low-speed by the code option and the PLL oscillation is selected for high-speed).

  • Page 63: Stop Mode When The Cpu Runs With High-Speed Clock

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.3.3.2 Stop mode when the CPU runs with high-speed clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the entering the STOP mode enabled (by using the stop code acceptor(STPACP)), the STOP mode is entered and high-speed oscillation and low-speed oscillation stop.
  • Page 64 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-8 shows the operation waveform in STOP mode when CPU operates with the high-speed clock (when the low-speed RC oscillation is selected for low-speed by the code option and the PLL oscillation is selected for high-speed). Low-speed RC Low-speed RC ocsillation...
  • Page 65 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-9 shows the operation waveform in STOP mode when CPU operates with the high-speed clock (when the low-speed crystal oscillation is selected for low-speed by the code option and the high-speed RC oscillation is selected for high-speed).
  • Page 66 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function Figure 4-10 shows the operation waveform in STOP mode when CPU operates with the high-speed clock (when the low-speed crystal oscillation is selected for low-speed by the code option and the PLL oscillation is selected for high-speed).

  • Page 67: Note On Return Operation From Stop/Halt Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP or HALT mode depends on the condition of interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE7), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.

  • Page 68: Block Control Function

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 4 MCU Control Function 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. For each block control register, the initial value of each flag is “0”, meaning the operation of each block is enabled. When any flag is set to “1”...

  • Page 69: Interrupts (Ints)

    Chapter 5 Interrupts...

  • Page 70: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5 Interrupt 5.1 General Description This LSI has external interrupts, internal interrupts, and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, "Time Base Counter" Chapter 8, "8-bit Timer" Chapter 9, "16-bit Timer"...

  • Page 71: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2 Description of Registers 5.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F010H Interrupt enable register 0 0F011H Interrupt enable register 1 0F012H Interrupt enable register 2 0F013H Interrupt enable register 3 0F014H Interrupt enable register 4 0F015H...

  • Page 72: Interrupt Enable Register 0 (Ie0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.2 Interrupt Enable Register 0 (IE0) Address: 0F010H Access: R/W Access size: 8 bits Initial value: 00H ELLD Initial value IE0 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE0 is not reset.

  • Page 73: Interrupt Enable Register 1 (Ie1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.3 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H EP31 EP30 EP05 EP04 EP03 EP02 EP01 EP00 Initial value IE1 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE1 is not reset.
  • Page 74 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts  EP05 (bit 5) EP05 is the enable flag for the input port P05 pin interrupt (P05INT). EP05 Description Disabled (initial value) Enabled  EP30 (bit 6) EP30 is the enable flag for the input port P30 pin interrupt (P30INT). EP30 Description Disabled (initial value)

  • Page 75: Interrupt Enable Register 2 (Ie2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.4 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H EI2C0 ESAD ESIO0 Initial value IE2 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE2 is not reset.

  • Page 76: Interrupt Enable Register 3 (Ie3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.5 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H ECMP0 ETM9 ETM8 ETM1 ETM0 Initial value IE3 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE3 is not reset.

  • Page 77: Interrupt Enable Register 4 (Ie4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.6 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H EUA1 EUA0 Initial value IE4 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE4 is not reset.

  • Page 78: Interrupt Enable Register 5 (Ie5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.7 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H ETMB ETMA Initial value IE5 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE5 is not reset.

  • Page 79: Interrupt Enable Register 6 (Ie6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.8 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H ELTBC1 ELTBC0 EPW7 EPW6 EPW5 EPW4 Initial value IE6 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE6 is not reset.
  • Page 80 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts  ELTBC1 (bit 7) ELTBC1 is the enable flag for the low-speed time base counter 1 interrupt (LTBC1INT). ELTBC1 Description Disabled (initial value) Enabled FEUL620Q150B 5-11...

  • Page 81: Interrupt Enable Register 7 (Ie7)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.9 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H ELTBC2 Initial value IE7 is a special function register (SFR) used to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to "0", but the corresponding flag of IE7 is not reset.

  • Page 82: Interrupt Request Register 0 (Irq0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.10 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H IRQ0 QLLD QCKC QWDT Initial value IRQ0 is a special function register (SFR) used to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT) and the clock backup interrupt (CKCINT) are non-maskable interrupts that do not depend on MIE.

  • Page 83: Interrupt Request Register 1 (Irq1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.11 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H IRQ1 QP31 QP30 QP05 QP04 QP03 QP02 QP01 QP00 Initial value IRQ1 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ1 request flag is set to "1"...
  • Page 84 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts  QP05 (bit 5) QP05 is the request flag for the input port P05 pin interrupt (P05INT). QP05 Description No request (initial value) Request  QP30 (bit 6) QP30 is the request flag for the input port P30 pin interrupt (P30INT). QP30 Description No request (initial value)

  • Page 85: Interrupt Request Register 2 (Irq2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.12 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H IRQ2 QI2C0 QSAD QSIO0 Initial value IRQ2 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ2 request flag is set to "1"...

  • Page 86: Interrupt Request Register 3 (Irq3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.13 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H IRQ3 QCMP0 QTM9 QTM8 QTM1 QTM0 Initial value IRQ3 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ3 request flag is set to "1"...
  • Page 87 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts  QCMP0 (bit 6) QCMP0 is the request flag for the comparator 0 interrupt (CMP0INT). QCMP0 Description No request (initial value) Request [Note] • When an interrupt is generated by the write instruction to the interrupt request register (IRQ3) or to the interrupt enable register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed.

  • Page 88: Interrupt Request Register 4 (Irq4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.14 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H IRQ4 QUA1 QUA0 Initial value IRQ4 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ4 request flag is set to "1"...

  • Page 89: Interrupt Request Register 5 (Irq5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.15 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H IRQ5 QTMB QTMA Initial value IRQ5 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ5 request flag is set to "1"...

  • Page 90: Interrupt Request Register 6 (Irq6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.16 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H IRQ6 QLTBC1 QLTBC0 QPW7 QPW6 QPW5 QPW4 Initial value IRQ6 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ6 request flag is set to "1"...
  • Page 91 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts  QLTBC1 (bit 7) QLTBC1 is the request flag for the low-speed time base counter 1 interrupt (LTBC1INT). QLTBC1 Description No request (initial value) Request [Note] • When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed.

  • Page 92: Interrupt Request Register 7 (Irq7)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.17 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H IRQ7 QLTBC2 Initial value IRQ7 is a special function register (SFR) used to request an interrupt for each interrupt source. Each IRQ7 request flag is set to "1"...

  • Page 93: Interrupt Level Control Enable Register (Ilenl)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.18 Interrupt Level Control Enable Register (ILENL) Address: 0F020H Access: R/W Access size: 8/16 bits Initial value: 00H ILENL Initial value The interrupt level control enable register (ILENL) is a special function register (SFR) used to control enable/disable for the interrupt level control.

  • Page 94: Current Interrupt Request Level Register (Cill)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.19 Current Interrupt Request Level Register (CILL) Address: 0F022H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― ― CILL CILN CILM[3:0] ― ― ― Initial value CILL is a special function register (SFR), that indicates the interrupt level of the interrupt currently being processed by the processor.

  • Page 95: Interrupt Level Control Register 01 (Ilc01)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.20 Interrupt Level Control Register 01 (ILC01) Address: 0F025H Access: R/W Access size: 8 bits Initial value: 00H ILC01 ILC01[5:4] Initial value ILC01 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC01 register is disabled.

  • Page 96: Interrupt Level Control Register 10 (Ilc10)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.21 Interrupt Level Control Register 10 (ILC10) Address: 0F026H Access: R/W Access size: 8/16 bits Initial value: 00H ILC10 ILC10[7:6] ILC10[5:4] ILC10[3:2] ILC10[1:0] ESAD ILC02[1:0] Initial value ILC10 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC10 register is disabled.

  • Page 97: Interrupt Level Control Register 11 (Ilc11)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.22 Interrupt Level Control Register 11 (ILC11) Address: 0F027H Access: R/W Access size: 8 bits Initial value: 00H ILC11 ILC11[7:6] ILC11[5:4] ILC11[3:2] ILC11[1:0] ESAD ILC02[1:0] ESAD ILC02[1:0] Initial value ILC11 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC11 register is disabled.

  • Page 98: Interrupt Level Control Register 20 (Ilc20)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.23 Interrupt Level Control Register 20 (ILC20) Address: 0F028H Access: R/W Access size: 8/16 bits Initial value: 00H ILC20 ILC20[5:4] ILC20[1:0] ILC03[1:0] Initial value ILC20 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC20 register is disabled.

  • Page 99: Interrupt Level Control Register 21 (Ilc21)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.24 Interrupt Level Control Register 21 (ILC21) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H ILC21 ILC21[7:6] Initial value ILC21 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC21 register is disabled.

  • Page 100: Interrupt Level Control Register 30 (Ilc30)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.25 Interrupt Level Control Register 30 (ILC30) Address: 0F02AH Access: R/W Access size: 8/16 bits Initial value: 00H ILC30 ILC30[7:6] ILC30[5:4] ILC30[3:2] ILC30[1:0] ESAD ILC05[1:0] Initial value ILC30 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC30 register is disabled.

  • Page 101: Interrupt Level Control Register 31 (Ilc31)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.26 Interrupt Level Control Register 31 (ILC31) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H ILC31 ILC31[5:4] Initial value ILC31 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC31 register is disabled.

  • Page 102: Interrupt Level Control Register 40 (Ilc40)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.27 Interrupt Level Control Register 40 (ILC40) Address: 0F02CH Access: R/W Access size: 8/16 bits Initial value: 00H ILC40 ILC40[3:2] ILC40[1:0] ESAD ILC07[1:0] Initial value ILC40 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC40 register is disabled.

  • Page 103: Interrupt Level Control Register 51 (Ilc51)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.28 Interrupt Level Control Register 51 (ILC51) Address: 0F02FH Access: R/W Access size: 8 bits Initial value: 00H ILC51 ILC51[3:2] ILC51[1:0] ESAD ILC10[1:0] Initial value ILC51 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC51 register is disabled.

  • Page 104: Interrupt Level Control Register 60 (Ilc60)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.29 Interrupt Level Control Register 60 (ILC60) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 00H ILC60 ILC60[7:6] ILC60[5:4] ILC60[3:2] ILC60[1:0] ESAD ILC11[1:0] Initial value ILC60 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC60 register is disabled.

  • Page 105: Interrupt Level Control Register 61 (Ilc61)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.30 Interrupt Level Control Register 61 (ILC61) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H ILC61 ILC61[7:6] ILC61[3:2] ESAD Initial value ILC61 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC61 register is disabled.

  • Page 106: Interrupt Level Control Register 70 (Ilc70)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.2.31 Interrupt Level Control Register 70 (ILC70) Address: 0F032H Access: R/W Access size: 8/16 bits Initial value: 00H ILC70 ILC70[7:6] Initial value ILC70 is a special function register (SFR) used to set the interrupt level for the maskable interrupt source. When the interrupt level function is disabled by setting the ILE bit of interrupt level control enable register (ILENL) to "0", writing to the ILC70 register is disabled.

  • Page 107: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3 Description of Operation With the exceptions of the watchdog timer interrupt (WDTINT) and clock backup interrupt (CKCINT), interrupt enable/disable for 28 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE0 to 7).
  • Page 108 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts [Note] • If multiple interrupts are generated concurrently when the interrupt level control is disabled, they are processed starting from the interrupt with the highest priority level (lowest interrupt source number), and the lower- priority interrupts (higher interrupt source number) are pending.

  • Page 109: Maskable Interrupt Processing

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to "1", the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1 (2) Transfer PSW to EPSW1 (3) Set the MIE flag to "0"...

  • Page 110: Notes On Interrupt Routine (When Interrupt Level Control Disabled)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.4 Notes on Interrupt Routine (When Interrupt Level Control Disabled) If ILE of the interrupt level control enable register (ILENL) is set to disable the interrupt level control, notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable.
  • Page 111 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the "PUSH LR" instruction to save the subroutine return address in the stack. •...
  • Page 112 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts Status B: Non-maskable interrupt is being processed B-1: When a subroutine is not called • Processing immediately after the start of interrupt routine execution No specific notes. • Processing at the end of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW.

  • Page 113: Flow Chart When Interrupt Level Control Enabled

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.5 Flow Chart When Interrupt Level Control Enabled The figure below shows the flow chart of the software processing of a maskable interrupt when the interrupt level control is enabled. Save ELR1 and EPSW1 to the stack because it prevents that ELR1 and EPSW1 are destroyed by a multiplex interrupt.

  • Page 114: How To Write Interrupt Processing When Interrupt Level Control Enabled

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled When ILE of the interrupt level control enable register (ILENL) is set to enable the interrupt level control, the interrupt function should be written as below. For more details and notes on how to write the interrupt processing, refer to "CCU8 Programming Guide".
  • Page 115 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts Example of output _intr_fn_10 push push push func(); _func CILL = 0; #00h 0f022h When calling other functions from an interrupt function, the output code becomes more redundant, which results in a longer interrupt processing time. This is because CCU8 does not know which register is used by func and thus saves all possible registers that may be changed by calling the func function in the stack.

  • Page 116: Writing Interrupt Function To Enable Multiple Interrupts

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.6.2 Writing Interrupt function to enable multiple interrupts When writing an interrupt function to enable multiple interrupts, specify "2" in the category field of the INTERRUPT and SWI pragmas. Even when the specification of the category field is omitted, multiple interrupts are enabled. The built-in function __EI can be called in an interrupt function that enables multiple interrupts.

  • Page 117: Interrupt Disable State

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 5 Interrupts 5.3.7 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state. Interrupt disabled state 1:Between the interrupt shift cycle and the instruction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this interval, an interrupt is generated immediately following the execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already...

  • Page 118: Clock Generation Circuit

    Chapter 6 Clock Generation Circuit...

  • Page 119: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6 Clock Generation Circuit 6.1 General Description The clock generation circuit generates and provides the low-speed clock (LSCLK), the high-speed clock (HSCLK), the system clock (SYSTEMCLK), and the high-speed output clock (OUTCLK). LSCLK and HSCLK are time base clocks for the peripheral circuits, SYSTEMCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port.

  • Page 120: Configuration

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.1.2 Configuration Figure 6-1 shows the configuration of the clock generation circuit. Low-speed RC Low-speed P12/XT0 Osc. Circuit crystal (Approx. oscillation 32.768kHz) P13/XT1 circuit LOSCS Code-Option Low-speed clock Low-speed (LSCLK) oscillation System clock Approx.32.77kHz backup-mode Dividing...

  • Page 121: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin Name Function P12/XT0 Pin for connecting a crystal for low-speed clock. P13/XT1 Pin for connecting a crystal for low-speed clock. 6.1.4 Clock Configuration Diagram Figure 6-2 shows the clock system diagram. System clock (SYSCLK) nX-U16/100 Register access...

  • Page 122: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.2 Description of Registers 6.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F002H Frequency control register 0 FCON0 8/16 FCON01 0F003H Frequency control register 1 FCON1 0F005H Frequency control register 3 FCON3 0F00AH...

  • Page 123: Frequency Control Register 0(Fcon0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H (FCON0) Access: R/W Access size: 8/16 bit Initial value: 33H FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0 Initial value FCON0 is a special function register (SFR) used to control the high-speed clock generation circuit and to select system clock.

  • Page 124: Frequency Control Register 1 (Fcon1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H (FCON1) Access: R/W Access size: 8 bit Initial value: 03H FCON1 LPLL ENOSC SYSCLK Initial value FCON1 is a special function register (SFR) used to control the high-speed clock generation circuit and to select system clock.

  • Page 125: Frequency Control Register 3(Fcon3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.2.4 Frequency Control Register 3(FCON3) Address: 0F005H(FCON3) Access: R/W Access size: 8 bits Initial Value: 00H FCON3 LOSCB HOSCB Initial value FCON3 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. FCON3 works only when the low-speed crystal oscillation circuit is selected by Code-Option.
  • Page 126 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit  LOSCB （bit 2） The LOSCB bit is used to control the low-speed clock backup function. The LOSCB bit available only when the low-speed crystal oscillation circuit is selected by Code-Option. When the PLL oscillation stopped by some reason, the both LOSCS bit of the frequency status register (FSTAT) and LOSCB bit become "1"...

  • Page 127: Frequency Status Register (Fstat)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.2.5 Frequency Status Register (FSTAT) Address: 0F00AH Access: R Access size: 8 bits Initial value: 04H FSTAT LOSCS HOSCS Initial value FSTAT is a special function register (SFR) used to show the clock generation circuit state. [Description of Bits] ...

  • Page 128: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.3 Description of Operation 6.3.1 Low-Speed Clock The low-speed crystal oscillation circuit or low-speed RC oscillation circuit is selectable for the low-speed clock by Code-Option. For how to select by Code-Option, see Chapter 30, “Code-Option”. 6.3.1.1 Low-Speed Crystal Oscillation Circuit Figure 6-3 shows the low-speed clock generation circuit configuration.

  • Page 129: Operation Of Low-Speed Clock Generation Circuit

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.3.1.3 Operation of Low-Speed Crystal Oscillation Circuit The low-speed crystal oscillation circuit is activated by code-option after the occurrence of power ON reset. Just after the power-on, the oscillation stop is detected for Approx. 16ms because the low-speed crystal has not started oscillating.
  • Page 130 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit When the program operation mode is restarted by reset input after the power supply is started, if the low-speed crystal oscillation continues during the oscillation stop detection period, the clock backup interrupt request will not be generated and the low-speed clock backup mode will not be entered.
  • Page 131 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit Reset release 16-bit timer Counting Set the timer clock to LSCLK and measure several counts or more. (Verify that LSCLK is supplied to peripheral circuits) Timer interrupt Generation When the crystal oscillation is stopped at reset release, LOSCS=1 is set. After the first CKCINT, the LSCLK is supplied with the backup clock.

  • Page 132: High-Speed Clock

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock For the high-speed clock generation circuit, the high-speed RC oscillation mode or the PLL (Phase Locked Loop) oscillation mode can be selected by the OSCM1, OSCM0 bits of the frequency control register 0 (FCON0). 6.3.2.1 High-Speed Built-in RC Oscillation Circuit Figure 6-6 shows the block diagram of high-speed built-in RC oscillation circuit.

  • Page 133: Operation Of High-Speed Clock

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.3.2.3 Operation of High-Speed Clock The high-speed clock generation circuit is activated in the RC oscillation mode (Approx.2.097MHz) by power-on reset generation. As a result of the occurrence of power-on reset, the circuit goes into system reset mode and then shifts to program operating mode and CPU starts after the elapse of the high-speed oscillation start time (T ) and the oscillation stabilization time (Count: 32,768) of the high-speed RC oscillation clock (OSCLK) and at the same time, a high-speed...
  • Page 134 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit High-speed oscillation Enable ENOSC : High-speed oscillation start time : High-speed oscillation start time High-speed PLL oscillation PLL oscillation oscillation High-speed oscillation 4096 High-speed oscillation 4096 counts 16 counts High-speed clock PLL oscillation waveform PLL oscillation waveform HSCLK Built-in RC oscillation...

  • Page 135: Switching Of System Clock

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-11 shows the flow chart of the system clock switching processing (HSCLKLSCLK), and Figure 6-12 shows the flow chart of the system clock switching processing (LSCLKHSCLK).

  • Page 136: Specifying Port Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.4 Specifying Port Registers To enable the clock output function, each related port register bit needs to be set. See Chapter 17, "Port 2" and Chapter 18, "Port 3" for detail about the port registers. 6.4.1 Functioning P21(OUTCLK) as the high-speed clock output Set P21MD1 bit (bit1 of P2MOD1 register) to “0”...

  • Page 137: Functioning P20 (Lsclk) As The Low-Speed Clock Output

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning P20 (LSCLK) as the low-speed clock output Set P20MD1 bit (bit0 of P2MOD1 register) to “0” and P20MD0 bit (bit0 of P2MOD0 register) to “1” for specifying the low-speed clock output as the secondary function of P20. Register name P2MOD1 register (Address: 0F22DH) P23MD1...

  • Page 138: Functioning P36 (Lsclk) As The Low-Speed Clock Output

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 6 Clock Generation Circuit 6.4.3 Functioning P36 (LSCLK) as the low-speed clock output Set P36MD1 bit (bit6 of P3MOD1 register) to “0” and Set P36MD0 bit (bit6 of P3MOD0 register) to “1”for specifying the low-speed clock output as the secondary function of P36. Register name P3MOD1 register (Address: 0F23BH) Bit name...

  • Page 139: Time Base Counter

    Chapter 7 Time Base Counter...

  • Page 140: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter Time Base Counter 7.1 General Description This LSI includes a low-speed time base counter (LTBC) that generate base clocks for peripheral circuits and periodical interrupts. For the input clock, see Chapter 6, “Clock Generation Circuit”. For interrupt permission, interrupt request flags, etc.

  • Page 141: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Low-speed time base counter  0F060H LTBR register Low-speed time base counter 0F062H LTBADJL 8/16 frequency adjustment register L LTBADJ Low-speed time base counter...

  • Page 142: Low-Speed Time Base Counter (Ltbr)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F060H Access: R/W Access size: 8 bits Initial value: 00H LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ Initial value LTBR is a special function register (SFR) to read the T128HZ-T1HZ signals of the low-speed time base counter. The T128HZ-T1HZ signals are set to “0”...

  • Page 143: Low-Speed Time Base Counter Frequency Adjustment Registers (Ltbadjl, Ltbadjh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter 7.2.3 Low-Speed Time Base Counter Frequency Adjustment Registers (LTBADJL, LTBADJH) Address: 0F062H(LTBADJL), 0F063H(LTBADJH) Access: R/W Access size: 8/16 bits Initial value: 0000H LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 Initial value ...
  • Page 144 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter The adjustment values (LADJ10 to LADJ0) to be set in LTBADJH and LTBADJL can be obtained by using the following equations: Adjustment value = Frequency adjustment ratio  2097152 (decimal) = Frequency adjustment ratio  200000h (hexadecimal) Example 1: When adjusting +15.0ppm (gaining time) Adjustment value = +15.0ppm ...

  • Page 145: Low-Speed Time Base Counter Interrupt Select Registers (Ltbint0, Ltbint1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Interrupt select Registers (LTBINT0, LTBINT1) Address: 0F064H(LTBINT0), 0F065H(LTBINT1) Access: R/W Access size: 8/16 bits Initial value: 0630H   LTBINT0 LTI1S2 LTI1S1 LTI1S0 LTI0S2 LTI0S1 LTI0S0  ...

  • Page 146: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter 7.3 Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The 3 interrupts of LTBC are requested by the falling edge of the signals which are selected by low-speed time base counter interrupt select register (LTBINT0, LTBINT1) (T128HZ, T16HZ and T2HZ are selected as initial value).
  • Page 147 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 7 Time Base Counter Figure 7-4 shows the time base counter interrupt timing (When T128HZ, T16HZ and T2HZ are selected by the low-speed time base counter interrupt select register (LTBINT0, LTBINT1)) and reset timing by writing to LTBR. LTBR Write T256HZ T128HZ...

  • Page 148: 8Bit Timer

    Chapter 8 8bit Timer...

  • Page 149: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8bit Timer 8.1 General Description This LSI includes two channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 8.1.1 Features  The timer interrupt (TMnINT, n=0 to 1) is generated when the values of timer counter register (TMnC) and timer data register (TMnD) coincide.

  • Page 150: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2 Description of Registers 8.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value Timer 0 data register 0F300H TM0D 8/16 0FFH TM01D 0F301H Timer 1 data register TM1D 0FFH Timer 0 counter register 0F310H TM0C...

  • Page 151: Timer 0 Data Register (Tm0D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.2 Timer 0 Data Register (TM0D) Address: 0F300H Access: R/W Access size: 8/16 bits Initial value: 0FFH TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value. [Note] •...

  • Page 152: Timer 1 Data Register (Tm1D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.3 Timer 1 Data Register (TM1D) Address: 0F301H Access: R/W Access size: 8 bits Initial value: 0FFH TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value TM1D is a special function register (SFR) to set the value to be compared with the timer 1 counter register (TM1C) value. [Note] •...

  • Page 153: Timer 0 Counter Register (Tm0C)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.4 Timer 0 Counter Register (TM0C) Address: 0F310H Access: R/W Access size: 8/16 bits Initial value: 00H TM0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 Initial value TM0C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM0C is performed, TM0C is set to “00H”.

  • Page 154: Timer 1 Counter Register (Tm1C)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.5 Timer 1 Counter Register (TM1C) Address: 0F311H Access: R/W Access size: 8 bits Initial value: 00H TM1C T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 Initial value TM1C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM1C is performed, TM1C is set to “00H”.

  • Page 155: Timer 0 Control Register (Tm0Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.6 Timer 0 Control Register (TM0CON) Address: 0F320H Access: R/W Access size: 8/16 bits Initial value: 00H ― ― TM0CON T0OST T01M16 T0DIV2 T0DIV1 T0DIV0 T0CS0 ― ― Initial value TM0CON is a special function register (SFR) to control timer 0. Write the TM0CON after clearing the TM0C by writing any data when the timer stops(when the T0STAT bit of TMSTAT0 register is “0”).
  • Page 156 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer  T0OST (bit 7) The T0OST bit is used for selecting a timer mode of timer 0. When the T0OST bit is set to “1”, timer 0 is selected as a one-shot mode. T0OST Description Continuous mode (initial value)

  • Page 157: Timer 1 Control Register (Tm1Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.7 Timer 1 Control Register (TM1CON) Address: 0F321H Access: R/W Access size: 8 bits Initial value: 00H ― ― ― TM1CON T1OST T1DIV2 T1DIV1 T1DIV0 T1CS0 ― ― ― Initial value TM1CON is a special function register (SFR) to control timer 1. Write the TM1CON after clearing the TM1C by writing any data when the timer stops(when the T1STAT bit of TMSTAT0 register is “0”).

  • Page 158: Timer Start Register 0 (Tmstr0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.8 Timer Start Register 0 (TMSTR0) Address: 0F330H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTR0 T1RUN T0RUN ― ― ― ― ― ― Initial value TMSTR0 is a special function register (SFR) to control starting the count-up of timer 0 and timer 1.

  • Page 159: Timer Stop Register 0 (Tmstp0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.9 Timer Stop Register 0 (TMSTP0) Address: 0F332H Access: W Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTP0 T1STP T0STP ― ― ― ― ― ― Initial value TMSTP0 is a special function register (SFR) to control stopping the count-up of timer 0 and timer 1.

  • Page 160: Timer Status Register 0 (Tmstat0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.2.10 Timer Status Register 0 (TMSTAT0) Address: 0F334H Access: R Access size: 8 bits Initial value: 00H ― ― ― ― ― ― TMSTAT0 T1STAT T0STAT ― ― ― ― ― ― Initial value TMSTAT0 is a special function register (SFR) that shows the status of timer 0 and timer 1.

  • Page 161: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer 8.3 Description of operation The timer n counter register (TMnC) is set to an operateing state (TnSTAT is set to “1”) on the falling edge of the timer clock (TnCK) that is selected by the timer n control register (TMnCON) when the TnRUN bit of timer start register 0 (TMSTR0) is set to “1”.
  • Page 162 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 8 8bit Timer Figure 8-3 shows the one-shot mode operation timing diagram TnCK TnRUN TnSTP TnSTAT Write TMnC TMnC TMnD TMnINT (n=0～1) Figure 8-3 One-Shot Mode Operation Timing Diagram of Timer 0 to 1 [Note] TnSTAT bit is automatically cleared when the data of TMnC and the timer n data register (TMnD) matches. FEUL620Q150B 8-14...

  • Page 163: 16Bit Timer

    Chapter 9 16bit Timer...

  • Page 164: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9 16bit Timer 9.1 General Description This LSI includes four channels of 16-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 9.1.1 Features  The timer interrupt (TMHnINT) is generated when the values of timer counter register (TMHnCH,TMHnCL n=8,9,A,B) and timer data register (TMHnDH,TMHnDL) coincide.

  • Page 165: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2 Description of Registers 9.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F340H 16bit timer 8 data register L TMH8DL 8/16 0FFH TMH8D 0F341H 16bit timer 8 data register H TMH8DH 0FFH 0F342H...

  • Page 166: 16Bit Timer 8 Data Register L,H (Tmh8Dl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.2 16bit timer 8 data register L,H (TMH8DL,H) Address: 0F340H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMH8DL TH8D7 TH8D6 TH8D5 TH8D4 TH8D3 TH8D2 TH8D1 TH8D0 Initial value Address: 0F341H Access: R/W Access size: 8 bits Initial value: 0FFH TMH8DH...

  • Page 167: 16Bit Timer 9 Data Register L,H (Tmh9Dl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.3 16bit timer 9 data register L,H (TMH9DL,H) Address: 0F342H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMH9DL TH9D7 TH9D6 TH9D5 TH9D4 TH9D3 TH9D2 TH9D1 TH9D0 Initial value Address: 0F343H Access: R/W Access size: 8 bits Initial value: 0FFH TMH9DH...

  • Page 168: 16Bit Timer A Data Register L,H (Tmhadl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.4 16bit timer A data register L,H (TMHADL,H) Address: 0F344H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMHADL THAD7 THAD6 THAD5 THAD4 THAD3 THAD2 THAD1 THAD0 Initial value Address: 0F345H Access: R/W Access size: 8 bits Initial value: 0FFH TMHADH...

  • Page 169: 16Bit Timer B Data Register L,H (Tmhbdl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.5 16bit timer B data register L,H (TMHBDL,H) Address: 0F346H Access: R/W Access size: 8/16 bits Initial value: 0FFH TMHBDL THBD7 THBD6 THBD5 THBD4 THBD3 THBD2 THBD1 THBD0 Initial value Address: 0F347H Access: R/W Access size: 8 bits Initial value: 0FFH TMHBDH...

  • Page 170: 16Bit Timer 8 Counter Register L,H (Tmh8Cl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.6 16bit timer 8 counter register L,H (TMH8CL,H) Address: 0F350H Access: R/W Access size: 8/16 bits Initial value: 00H TMH8CL TH8C7 TH8C6 TH8C5 TH8C4 TH8C3 TH8C2 TH8C1 TH8C0 Initial value Address: 0F351H Access: R/W Access size: 8 bits Initial value: 00H TMH8CH...

  • Page 171: 16Bit Timer 9 Counter Register L,H (Tmh9Cl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.7 16bit timer 9 counter register L,H (TMH9CL,H) Address: 0F352H Access: R/W Access size: 8/16 bits Initial value: 00H TMH9CL TH9C7 TH9C6 TH9C5 TH9C4 TH9C3 TH9C2 TH9C1 TH9C0 Initial value Address: 0F353H Access: R/W Access size: 8 bits Initial value: 00H TMH9CH...

  • Page 172: 16Bit Timer A Counter Register L,H (Tmhacl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.8 16bit timer A counter register L,H (TMHACL,H) Address: 0F354H Access: R/W Access size: 8/16 bits Initial value: 00H TMHACL THAC7 THAC6 THAC5 THAC4 THAC3 THAC2 THAC1 THAC0 Initial value Address: 0F355H Access: R/W Access size: 8 bits Initial value: 00H TMHACH...

  • Page 173: 16Bit Timer B Counter Register L,H (Tmhbcl,H)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.9 16bit timer B counter register L,H (TMHBCL,H) Address: 0F356H Access: R/W Access size: 8/16 bits Initial value: 00H TMHBCL THBC7 THBC6 THBC5 THBC4 THBC3 THBC2 THBC1 THBC0 Initial value Address: 0F357H Access: R/W Access size: 8 bits Initial value: 00H TMHBCH...

  • Page 174: 16Bit Timer 8 Control Register L,H (Tmh8Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.10 16bit timer 8 control register (TMH8CON) Address: 0F360H Access: R/W Access size: 8 bits Initial value: 00H － － TMH8CON TH8OST TH8DIV2 TH8DIV1 TH8DIV0 TH8CS1 TH8CS0 － － Initial value TMH8CON is a special function (SFR) to control the 16bit timer 8. Write the TMH8CON after clearing the TMH8CL,H by writing any data when the timer 8 stops (when the TH8STAT bit of TMHSTAT0 register is “0”).
  • Page 175 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.11 16bit timer 9 control register (TMH9CON) Address: 0F362H Access: R/W Access size: 8 bits Initial value: 00H － － TMH9CON TH9OST TH9DIV2 TH9DIV1 TH9DIV0 TH9CS1 TH9CS0 － － Initial value TMH9CON is a special function (SFR) to control the 16bit timer 9. Write the TMH9CON after clearing the TMH9CL,H by writing any data when the timer 9 stops(when the TH9STAT bit of TMHSTAT0 register is “0”).

  • Page 176: 16Bit Timer A Control Register L,H (Tmhacon)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.12 16bit timer A control register (TMHACON) Address: 0F364H Access: R/W Access size: 8 bits Initial value: 00H － TMHACON THAOST THANEG THADIV2 THADIV1 THADIV0 THACS1 THACS0 － Initial value TMHACON is a special function (SFR) to control the 16bit timer A. Write the TMHACON after clearing the TMHACL,H by writing any data when the timer A stops(when the THASTAT bit of TMHSTAT0 register is “0”).

  • Page 177: 16Bit Timer B Control Register L,H (Tmhbcon)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.13 16bit timer B control register (TMHBCON) Address: 0F366H Access: R/W Access size: 8 bits Initial value: 00H － TMHBCON THBOST THBNEG THBDIV2 THBDIV1 THBDIV0 THBCS1 THBCS0 － Initial value TMHBCON is a special function (SFR) to control the 16bit timer B. Write the TMHBCON after clearing the TMHBCL,H by writing any data when the timer B stops(when the THBSTAT bit of TMHSTAT0 register is “0”).

  • Page 178: 16Bit Timer Start Register 0 (Tmhstr0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.14 16bit timer start register 0 (TMHSTR0) Address: 0F370H Access: W Access size: 8 bits Initial value: 00H － － － － TMHSTR0 THBRUN THARUN TH9RUN TH8RUN － － － － Initial value TMHSTR0 is a special function (SFR) to control starting count of 16bit timer 8, 9, A and B.

  • Page 179: 16Bit Timer Stop Register 0 (Tmhstp0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.15 16bit timer stop register 0 (TMHSTP0) Address: 0F372H Access: W Access size: 8 bits Initial value: 00H － － － － TMHSTP0 THBSTP THASTP TH9STP TH8STP － － － － Initial value TMHSTP0 is a special function (SFR) to control stopping count of 16bit timer 8, 9, A and B.

  • Page 180: 16Bit Timer Status Register 0 (Tmhstat0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.2.16 16bit timer status register 0 (TMHSTAT0) Address: 0F374H Access: R Access size: 8 bits Initial value: 00H － － － － TMHSTAT0 THBSTAT THASTAT TH9STAT TH8STAT － － － － Initial value TMHSTAT0 is a special function (SFR) that shows status of 16bit timer 8, 9, A and B.

  • Page 181: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer 9.3 Description of operation The 16bit timer n (n=8,9,A,B) counter register (TMHnC) is set to an operating state (THnSTAT is set to “1”) on the first falling edge of the timer clock (THnCK) that is selected by the 16bit timer n control register (TMHnCON) and start counting from second falling edge of the timer clock (THnCK) when the THnRUN bit of the 16bit timer start register 0 (TMHSTR0) is set to 1.
  • Page 182 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 9 16bit Timer Figure 9-3 shows the one-shot mode operation timing diagram of the 16bit timer 8, 9, A and B. THnCK THnRUN THnSTP THnSTAT Write TMHnC TMHnCH,L XXXX 0000 0001 0002 0087 0088 0001 0000 TMHnDH,L 0088 TMHnINT...

  • Page 183: Watchdog Timer

    Chapter 10 Watchdog Timer...

  • Page 184: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10 Watchdog Timer 10.1 General Description This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the watchdog timer requests a WDT interrupt (non-maskable interrupt).

  • Page 185: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10.2 Description of Registers 10.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value  Watchdog timer control register 0F00EH WDTCON  0F00FH Watchdog timer mode register WDTMOD FEUL620Q150B 10-2...

  • Page 186: Watchdog Timer Control Register (Wdtcon)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H WDTCON WDP/d0 Initial value WDTCON is a special function register (SFR) to control the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0.

  • Page 187: Watchdog Timer Mode Register (Wdtmod)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 02H       WDTMOD WDT1 WDT0       Initial value WDTMOD is a special function register (SFR) to set the overflow period of theWDT counter.

  • Page 188: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10.3 Description of operation The WDT counter starts counting by using T256HZ signal of the low-speed clock oscillation after the system reset has been released and the low-speed clock (LSCLK) oscillation start. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when WDP is "1".
  • Page 189 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer Figure 10-2 shows an example of watchdog timer operation. Program Low-Speed Occurrence of Clock Start abnormality Oscillation starts WDTMOD RESET_N WDTMOD  Setting Setting System reset       Data: WDTCON Write Internal pointer (WDP)
  • Page 190 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 10 Watchdog Timer 10.3.1 Handling example when not using the watch dog timer WDT counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (LSCLK) starts oscillating. If the WDT counter gets overflow, the WDT non-maskable interrupt occurs and then a system reset occurs.

  • Page 191: Pwm

    Chapter 11 PWM...

  • Page 192: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11 PWM 11.1 General Description This LSI includes four channels of 16-bit PWM (Pulse Width Modulation). The PWM4 output (PWM4) is assigned to P20(Port 2), P34(Port 3), P43(Port 4), P64(Port 6) and P87(Port 8) as the tertiary function.

  • Page 193: Configuration

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.1.2 Configuration Figure 11-1 shows the configuration of PWM 4 and PWM5. PnNEG P20/PWM4 PnFLG Write PWnCH P34/PWM4 PWnINT Write PWnCL Output control circuit P43/PWM4 P00/PW45EV0 P64/PWM4 P87/PWM4 Duty Period P32/PW45EV0 Port control match match circuit P30/PW45EV1...
  • Page 194 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM P20/PWM4 P34/PWM4 P43/PWM4 P64/PWM4 P87/PWM4 PmNEG P21/PWM5 P35/PWM5 P47/PWM5 P65/PWM5 P83/PWM5 PnNEG PnFLG PmFLG PWnINT Write PWnCH Write PWnCL Output control circuit Output control circuit Emergency stop control P00/PW45EV0 circuit Period Duty delay1 delay2 Port control P32/PW45EV0 match...
  • Page 195 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM Figure 11-2 shows the configuration of PWM 6 and PWM7. PnNEG P22/PWM6 PnFLG Write PWnCH P53/PWM6 PWnINT Write PWnCL Output control circuit P60/PWM6 P01/PW67EV0 P66/PWM6 P70/PWM6 Duty Period P33/PW67EV0 Port control match match circuit P31/PW67EV1 P23/PWM7 Comparator...
  • Page 196 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM P22/PWM6 P53/PWM6 P60/PWM6 P66/PWM6 P70/PWM6 PmNEG P23/PWM7 P57/PWM7 P61/PWM7 P71/PWM7 PnNEG PnFLG PmFLG PWnINT Write PWnCH Write PWnCL Output control circuit Output control circuit Emergency stop control P01/PW67EV0 circuit Period Duty delay1 delay2 Port control P33/PW67EV0 match match...

  • Page 197: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.1.3 List of Pins Pin name Function P44/T0P4CK Used for an external clock input for PWM4. P45/T1P5CK Used for an external clock input for PWM5. P46/ T16CK0 Used for an external clock input for PWM6. P47/ T16CK1 Used for an external clock input for PWM7.

  • Page 198: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2 Description of Registers 11.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F4A0H PWM4 period register L PW4PL 8/16 0FFH PW4P 0F4A1H PWM4 period register H PW4PH 0FFH 0F4A2H PWM4 duty register L PW4DL 8/16...
  • Page 199 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F4D6H PWM7 control register 0 PW7CON0 8/16 PW7CON0W 0F4D7H PWM7 control register 1 PW7CON1 － 0F4D8H PWM7 control register 2 PW7CON2 0F4DAH PWM7 control register 4 PW7CON4 8/16 PW7CON4W...

  • Page 200: Pwm4 Period Register L, H (Pw4Pl, Pw4Ph)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.2 PWM4 period register L, H (PW4PL, PW4PH) Address: 0F4A0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW4PL P4P7 P4P6 P4P5 P4P4 P4P3 P4P2 P4P1 P4P0 Initial value Address: 0F4A1H Access: R/W Access size: 8 bits Initial value: 0FFH PW4PH...

  • Page 201: Pwm4 Duty Register L, H (Pw4Dl, Pw4Dh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.3 PWM4 duty register L, H (PW4DL, PW4DH) Address: 0F4A2H Access: R/W Access size: 8/16 bits Initial value: 00H PW4DL P4D7 P4D6 P4D5 P4D4 P4D3 P4D2 P4D1 P4D0 Initial value Address: 0F4A3H Access: R/W Access size: 8 bits Initial value: 00H PW4DH...

  • Page 202: Pwm4 Counter Register L, H (Pw4Cl, Pw4Ch)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.4 PWM4 counter register L, H (PW4CL, PW4CH) Address: 0F4A4H Access: R/W Access size: 8/16 bits Initial value: 00H PW4CL P4C7 P4C6 P4C5 P4C4 P4C3 P4C2 P4C1 P4C0 Initial value Address: 0F4A5H Access: R/W Access size: 8 bits Initial value: 00H PW4CH...

  • Page 203: Pwm4 Control Register 0 (Pw4Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.5 PWM4 control register 0 (PW4CON0) Address: 0F4A6H Access: R/W Access size: 8/16 bits Initial value: 00H PW4CON0 P4CLIG P4STPSEL P4INI P4NEG P4IS1 P4IS0 P4CS1 P4CS0 Initial value PW4CON0 is a special function register (SFR) to control the PWM4. Rewrite PW4CON0 while the PWM4 is stopped (P4STAT of the PW4CON1 register is "0").
  • Page 204 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P4STPSEL (bit 6) The P4STPSEL bit is used to select the PWM4 output level while the PWM4 output is being temporarilly suspended, which holds the level or gets it back to an initial level. The initial level is determined by P4INI bit and the level is reversed when P4NEG bit is “1”.

  • Page 205: Pwm4 Control Register 1 (Pw4Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.6 PWM4 control register 1 (PW4CON1) Address: 0F4A7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW4CON1 P4STAT P4FLG P4RUN － － － － － Initial value PW4CON1 is a special function register (SFR) to control PWM4. [Description of Bits] ...

  • Page 206: Pwm4 Control Register 2 (Pw4Con2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.7 PWM4 control register 2 (PW4CON2) Address: 0F4A8H Access: R/W Access size: 8/16 bits Initial value: 00H － PW4CON2 P45MD P4MD P4TGSEL P4STM1 P4STM0 P4TGE1 P4TGE0 － Initial value PW4CON2 is a special function register (SFR) to control PWM4. Rewrite PW4CON2 while the PWM4 is stopped (P4STAT of the PW4CON1 register is "0") and disabled the count start/stop by the external input (P4TGE1 and P4TGE0 of PW4CON2 are "0").
  • Page 207 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P4 MD (bit 6) The P4MD bit is used to select one shot mode or continuous mode of PWM4. Setting “1” to the P4MD bit selects the one shot mode. In the coupled mode (P45MD=1), this setting is also applied to the PWM5. P4MD Description Continuous mode of PWM4 (Initial value)

  • Page 208: Pwm4 Control Register 3 (Pw4Con3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.8 PWM4 control register 3 (PW4CON3) Address: 0F4A9H Access: R/W Access size: 8 bits Initial value: 10H － － － － PW4CON3 P4SDST P4DTMD P4SDE1 P4SDE0 － － － － Initial value PW4CON3 is a special function register (SFR) to control PWM4. Rewrite PW4CON3 while the PWM4 is stopped (P4STAT of the PW4CON1 register is "0") and disabled the count start/stop by the external input (P4TGE1 and P4TGE0 of PW4CON2 are "0").

  • Page 209: Pwm4 Control Register 4 (Pw4Con4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.9 PWM4 control register 4 (PW4CON4) Address: 0F4AAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW4CON4 P4T1SEL0 P4T0SEL0 － － － － － － Initial value PW4CON4 is a special function register (SFR) to control PWM4.

  • Page 210: Pwm4 Control Register 5 (Pw4Con5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.10 PWM4 control register 5 (PW4CON5) Address: 0F4ABH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW4CON5 P4T1S1 P4T1S0 P4T0S1 P4T0S0 － － － － Initial value PW4CON5 is a special function register (SFR) to control PWM4. Rewrite PW4CON5 while the PWM4 is stopped (P4STAT of the PW4CON1 register is "0") and disabled the count start/stop by the external input (P4TGE1 and P4TGE0 of PW4CON2 are "0").

  • Page 211: Pwm4 Control Register 6 (Pw4Con6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.11 PWM4 control register 6 (PW4CON6) Address: 0F4ACH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW4CON6 P4DIV2 P4DIV1 P4DIV0 － － － － － Initial value PW4CON6 is a special function register (SFR) to control PWM4. Rewrite PW4CON6 while the PWM4 is stopped (P4STAT of the PW4CON1 register is "0").

  • Page 212: Pwm5 Period Register L, H (Pw5Pl, Pw5Ph)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.12 PWM5 period register L, H (PW5PL, PW5PH) Address: 0F4B0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW5PL P5P7 P5P6 P5P5 P5P4 P5P3 P5P2 P5P1 P5P0 Initial value Address: 0F4B1H Access: R/W Access size: 8 bits Initial value: 0FFH PW5PH...

  • Page 213: Pwm5 Duty Register L, H (Pw5Dl, Pw5Dh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.13 PWM5 duty register L, H (PW5DL, PW5DH) Address: 0F4B2H Access: R/W Access size: 8/16 bits Initial value: 00H PW5DL P5D7 P5D6 P5D5 P5D4 P5D3 P5D2 P5D1 P5D0 Initial value Address: 0F4B3H Access: R/W Access size: 8 bits Initial value: 00H PW5DH...

  • Page 214: Pwm5 Counter Register L, H (Pw5Cl, Pw5Ch)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.14 PWM5 counter register L, H (PW5CL, PW5CH) Address: 0F4B4H Access: R/W Access size: 8/16 bits Initial value: 00H PW5CL P5C7 P5C6 P5C5 P5C4 P5C3 P5C2 P5C1 P5C0 Initial value Address: 0F4B5H Access: R/W Access size: 8 bits Initial value: 00H PW5CH...

  • Page 215: Pwm5 Control Register 0 (Pw5Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.15 PWM5 control register 0 (PW5CON0) Address: 0F4B6H Access: R/W Access size: 8/16 bits Initial value: 00H PW5CON0 P5CLIG P5STPSEL P5INI P5NEG P5IS1 P5IS0 P5CS1 P5CS0 Initial value PW5CON0 is a special function register (SFR) to control the PWM5. Rewrite PW5CON0 while the PWM5 is stopped (P5STAT of the PW5CON1 register is "0").
  • Page 216 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P5STPSEL (bit 6) The P5STPSEL bit is used to select the PWM5 output level while the PWM5 output is being temporarilly suspended, which holds the level or gets it back to an initial level. The initial level is determined by P5INI bit and the level is reversed when P5NEG bit is “1”.

  • Page 217: Pwm5 Control Register 1 (Pw5Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.16 PWM5 control register 1 (PW5CON1) Address: 0F4B7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW5CON1 P5STAT P5FLG P5RUN － － － － － Initial value PW5CON1 is a special function register (SFR) to control PWM5. [Description of Bits] ...

  • Page 218: Pwm5 Control Register 2 (Pw5Con2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.17 PWM5 control register 2 (PW5CON2) Address: 0F4B8H Access: R/W Access size: 8 bits Initial value: 00H － － PW5CON2 P5MD P5TGSEL P5STM1 P5STM0 P5TGE1 P5TGE0 － － Initial value PW5CON2 is a special function register (SFR) to control PWM5. Rewrite PW5CON2 while the PWM5 is stopped (P5STAT of the PW5CON1 register is "0") and disabled the count start/stop by the external input (P5TGE1 and P5TGE0 of PW5CON2 are "0").
  • Page 219 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P5MD (bit 6) The P5MD bit is used to select one shot mode or continouous mode of PWM5. Setting “1” to the P5MD bit selects the one shot mode. In the coupled mode (P45MD=1), this bit is ignored and the setting of P4MD bit is applied. P5MD Description Continuous mode of PWM5 (Initial value)

  • Page 220: Pwm5 Control Register 4 (Pw5Con4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.18 PWM5 control register 4 (PW5CON4) Address: 0F4BAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW5CON4 P5T1SEL0 P5T0SEL0 － － － － － － Initial value PW5CON4 is a special function register (SFR) to control PWM5.

  • Page 221: Pwm5 Control Register 5 (Pw5Con5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.19 PWM5 control register 5 (PW5CON5) Address: 0F4BBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW5CON5 P5T1S1 P5T1S0 P5T0S1 P5T0S0 － － － － Initial value PW5CON5 is a special function register (SFR) to control PWM5. Rewrite PW5CON5 while the PWM5 is stopped (P5STAT of the PW5CON1 register is "0") and disabled the count start/stop by the external input (P5TGE1 and P5TGE0 of PW5CON2 are "0").

  • Page 222: Pwm5 Control Register 6 (Pw5Con6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.20 PWM5 control register 6 (PW5CON6) Address: 0F4BCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW5CON6 P5DIV2 P5DIV1 P5DIV0 － － － － － Initial value PW5CON6 is a special function register (SFR) to control PWM5. Rewrite PW5CON6 while the PWM5 is stopped (P5STAT of the PW5CON1 register is "0").

  • Page 223: Pwm6 Period Register L, H (Pw6Pl, Pw6Ph)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.21 PWM6 period register L, H (PW6PL, PW6PH) Address: 0F4C0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW6PL P6P7 P6P6 P6P5 P6P4 P6P3 P6P2 P6P1 P6P0 Initial value Address: 0F4C1H Access: R/W Access size: 8 bits Initial value: 0FFH PW6PH...

  • Page 224: Pwm6 Duty Register L, H (Pw6Dl, Pw6Dh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.22 PWM6 duty register L, H (PW6DL, PW6DH) Address: 0F4C2H Access: R/W Access size: 8/16 bits Initial value: 00H PW6DL P6D7 P6D6 P6D5 P6D4 P6D3 P6D2 P6D1 P6D0 Initial value Address: 0F4C3H Access: R/W Access size: 8 bits Initial value: 00H PW6DH...

  • Page 225: Pwm6 Counter Register L, H (Pw6Cl, Pw6Ch)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.23 PWM6 counter register L, H (PW6CL, PW6CH) Address: 0F4C4H Access: R/W Access size: 8/16 bits Initial value: 00H PW6CL P6C7 P6C6 P6C5 P6C4 P6C3 P6C2 P6C1 P6C0 Initial value Address: 0F4C5H Access: R/W Access size: 8 bits Initial value: 00H PW6CH...

  • Page 226: Pwm6 Control Register 0 (Pw6Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.24 PWM6 control register 0 (PW6CON0) Address: 0F4C6H Access: R/W Access size: 8/16 bits Initial value: 00H PW6CON0 P6CLIG P6STPSEL P6INI P6NEG P6IS1 P6IS0 P6CS1 P6CS0 Initial value PW6CON0 is a special function register (SFR) to control the PWM6. Rewrite PW6CON0 while the PWM6 is stopped (P6STAT of the PW6CON1 register is "0").
  • Page 227 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P6STPSEL (bit 6) The P6STPSEL bit is used to select the PWM6 output level while the PWM6 output is being temporarilly suspended, which holds the level or gets it back to an initial level. The initial level is determined by P6INI bit and the level is reversed when P6NEG bit is “1”.

  • Page 228: Pwm6 Control Register 1 (Pw6Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.25 PWM6 control register 1 (PW6CON1) Address: 0F4C7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW6CON1 P6STAT P6FLG P6RUN － － － － － Initial value PW6CON1 is a special function register (SFR) to control PWM6. [Description of Bits] ...

  • Page 229: Pwm6 Control Register 2 (Pw6Con2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.26 PWM6 control register 2 (PW6CON2) Address: 0F4C8H Access: R/W Access size: 8/16 bits Initial value: 00H － PW6CON2 P67MD P6MD P6TGSEL P6STM1 P6STM0 P6TGE1 P6TGE0 － Initial value PW6CON2 is a special function register (SFR) to control PWM6. Rewrite PW6CON2 while the PWM6 is stopped (P6STAT of the PW6CON1 register is "0") and disabled the count start/stop by the external input (P6TGE1 and P6TGE0 of PW6CON2 are "0").
  • Page 230 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P6MD (bit 6) The P6MD bit is used to select one shot mode or continuous mode of PWM6. Setting “1” to the P6MD bit selects the one shot mode. In the coupled mode (P67MD=1), this setting is also applied to the PWM7. P6MD Description Continuous mode of PWM6 (Initial value)

  • Page 231: Pwm6 Control Register 3 (Pw6Con3)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.27 PWM6 control register 3 (PW6CON3) Address: 0F4C9H Access: R/W Access size: 8 bits Initial value: 10H － － － － PW6CON3 P6SDST P6DTMD P6SDE1 P6SDE0 － － － － Initial value PW6CON3 is a special function register (SFR) to control PWM6. Rewrite PW6CON3 while the PWM6 is stopped (P6STAT of the PW6CON1 register is "0") and disabled the count start/stop by the external input (P6TGE1 and P6TGE0 of PW6CON2 are "0").

  • Page 232: Pwm6 Control Register 4 (Pw6Con4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.28 PWM6 control register 4 (PW6CON4) Address: 0F4CAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW6CON4 P6T1SEL0 P6T0SEL0 － － － － － － Initial value PW6CON4 is a special function register (SFR) to control PWM6.

  • Page 233: Pwm6 Control Register 5 (Pw6Con5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.29 PWM6 control register 5 (PW6CON5) Address: 0F4CBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW6CON5 P6T1S1 P6T1S0 P6T0S1 P6T0S0 － － － － Initial value PW6CON5 is a special function register (SFR) to control PWM6. Rewrite PW6CON5 while the PWM6 is stopped (P6STAT of the PW6CON1 register is "0") and disabled the count start/stop by the external input (P6TGE1 and P6TGE0 of PW6CON2 are "0").

  • Page 234: Pwm6 Control Register 6 (Pw6Con6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.30 PWM6 control register 6 (PW6CON6) Address: 0F4CCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW6CON6 P6DIV2 P6DIV1 P6DIV0 － － － － － Initial value PW6CON6 is a special function register (SFR) to control PWM6. Rewrite PW6CON6 while the PWM6 is stopped (P6STAT of the PW6CON1 register is "0").

  • Page 235: Pwm7 Period Register L, H (Pw7Pl, Pw7Ph)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.31 PWM7 period register L, H (PW7PL, PW7PH) Address: 0F4D0H Access: R/W Access size: 8/16 bits Initial value: 0FFH PW7PL P7P7 P7P6 P7P5 P7P4 P7P3 P7P2 P7P1 P7P0 Initial value Address: 0F4D1H Access: R/W Access size: 8 bits Initial value: 0FFH PW7PH...

  • Page 236: Pwm7 Duty Register L, H(Pw7Dl, Pw7Dh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.32 PWM7 duty register L, H(PW7DL, PW7DH) Address: 0F4D2H Access: R/W Access size: 8/16 bits Initial value: 00H PW7DL P7D7 P7D6 P7D5 P7D4 P7D3 P7D2 P7D1 P7D0 Initial value Address: 0F4D3H Access: R/W Access size: 8 bits Initial value: 00H PW7DH P7D15...

  • Page 237: Pwm7 Counter Register L, H (Pw7Cl, Pw7Ch)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.33 PWM7 counter register L, H(PW4CL, PW4CH) Address: 0F4D4H Access: R/W Access size: 8/16 bits Initial value: 00H PW7CL P7C7 P7C6 P7C5 P7C4 P7C3 P7C2 P7C1 P7C0 Initial value Address: 0F4D5H Access: R/W Access size: 8 bits Initial value: 00H PW7CH P7C15...

  • Page 238: Pwm7 Control Register 0 (Pw7Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.34 PWM7 control register 0 (PW7CON0) Address: 0F4D6H Access: R/W Access size: 8/16 bits Initial value: 00H PW7CON0 P7CLIG P7STPSEL P7INI P7NEG P7IS1 P7IS0 P7CS1 P7CS0 Initial value PW7CON0 is a special function register (SFR) to control the PWM7. Rewrite PW7CON0 while the PWM7 is stopped (P7STAT of the PW7CON1 register is "0").
  • Page 239 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P7STPSEL (bit 6) The P7STPSEL bit is used to select the PWM7 output level while the PWM7 output is being temporarilly suspended, which holds the level or gets it back to an initial level. The initial level is determined by P7INI bit and the level is reversed when P7NEG bit is “1”.

  • Page 240: Pwm7 Control Register 1 (Pw7Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.35 PWM7 control register 1 (PW7CON1) Address: 0F4D7H Access: R/W Access size: 8 bits Initial value: 40H － － － － － PW7CON1 P7STAT P7FLG P7RUN － － － － － Initial value PW7CON1 is a special function register (SFR) to control PWM7. [Description of Bits] ...

  • Page 241: Pwm7 Control Register 2 (Pw7Con2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.36 PWM7 control register 2 (PW7CON2) Address: 0F4D8H Access: R/W Access size: 8 bits Initial value: 00H － － PW7CON2 P7MD P7TGSEL P7STM1 P7STM0 P7TGE1 P7TGE0 － － Initial value PW7CON2 is a special function register (SFR) to control PWM7. Rewrite PW7CON2 while the PWM7 is stopped (P7STAT of the PW7CON1 register is "0") and disabled the count start/stop by the external input (P7TGE1 and P7TGE0 of PW7CON2 are "0").
  • Page 242 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM  P7MD (bit 6) The P7MD bit is used to select one shot mode or continuous mode of PWM7. Setting “1” to the P7MD bit selects the one shot mode. In the coupled mode (P67MD=1), this bit is ignored and the setting of P6MD bit is applied. P7MD Description Continuous mode of PWM7 (Initial value)

  • Page 243: Pwm7 Control Register 4 (Pw7Con4)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.37 PWM7 control register 4 (PW7CON4) Address: 0F4DAH Access: R/W Access size: 8/16 bits Initial value: 00H － － － － － － PW7CON4 P7T1SEL0 P7T0SEL0 － － － － － － Initial value PW7CON4 is a special function register (SFR) to control PWM7.

  • Page 244: Pwm7 Control Register 5 (Pw7Con5)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.38 PWM7 control register 5 (PW7CON5) Address: 0F4DBH Access: R/W Access size: 8 bits Initial value: 00H － － － － PW7CON5 P7T1S1 P7T1S0 P7T0S1 P7T0S0 － － － － Initial value PW7CON5 is a special function register (SFR) to control PWM7. Rewrite PW7CON5 while the PWM7 is stopped (P7STAT of the PW7CON1 register is "0") and disabled the count start/stop by the external input (P7TGE1 and P7TGE0 of PW7CON2 are "0").

  • Page 245: Pwm7 Control Register 6 (Pw7Con6)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.2.39 PWM7 control register 6 (PW7CON6) Address: 0F4DCH Access: R/W Access size: 8 bits Initial value: 00H － － － － － PW7CON6 P7DIV2 P7DIV1 P7DIV0 － － － － － Initial value PW7CON6 is a special function register (SFR) to control PWM7. Rewrite PW7CON6 while the PWM7 is stopped (P7STAT of the PW7CON1 register is "0").

  • Page 246: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3 Description of Operation The operation of PWMm and PWMn ({m, n}={4, 5}, {6, 7}) are categorized into six modes which are shown in the table 11-5. Table 11-5 PWM Operation Mode PmnMD PmMD/ PmDTMD Operation mode Description...
  • Page 247 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM The control mode of PWMn (n=4, 5, 6, 7) is categorized into 10 modes which are shown in the table 11-6. Table 11-6 PWM Control Mode PnSTM1 PnSTM0 PnTGE1 PnTGE0 Control mode Description － －...

  • Page 248: Pwm Single Mode / Continuous Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.1 PWM Single mode / Continuous mode When the PmnMD (mn=45, 67) bit of the PWMm (m=4, 6) control register 2 (PWmCON2) is set to “0” and the PnMD bit of the PWMn (n=4, 5, 6, 7) control register 2 (PWnCON2) is set to “0”, PWMn operates in single mode/continuous mode. For the details about start/ stop/clear operation and the update timing of the period/duty, see the section “11.3.5 PWM Control by the Software”...
  • Page 249 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWMn clock. This causes an error of up to 1 clock pulse to the time the first PWMn interrupt is issued. The PWMn interrupt period from the second time is fixed. Figure 11-3 shows the operation timing of PWM4 on the condition of single mode and continuous mode.

  • Page 250: Pwm Single Mode / One Shot Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.2 PWM Single mode / One shot mode When the PmnMD (mn=45, 67) bit of the PWMm (m=4, 6) control register 2 (PWmCON2) is set to “0” and the PnMD bit of the PWMn (n=4, 5, 6, 7) control register 2 (PWnCON2) is set to “1”, PWMn operates in single mode/one shot mode. For the details about start/ stop/clear operation and the update timing of the period/duty, see the section “11.3.5 PWM Control by the Software”...
  • Page 251 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWMn clock. This causes an error of up to 1 clock pulse to the time the first PWMn interrupt is issued. Figure 11-4 shows the operation timing of PWM4 on the condition of single mode and one shot mode.

  • Page 252: Pwm Coupled Mode / Continuous Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.3 PWM Coupled mode / Continuous mode When the PmnMD bit of the PWMm control register 2 (PWmCON2) is set to “1” and the PmMD bit of PWmCON2 is set to “0”, PWMm, PWMn ({m, n}={4, 5}, {6, 7}) operates in coupled mode/continuous mode. For the details about start/ stop/clear operation and the update timing of the period/duty, see the section “11.3.5 PWM Control by the Software”...
  • Page 253 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PmRUN bit is set to “1”, counting starts in synchronization with the PWMm clock. This causes an error of up to 1 clock pulse to the time the first PWMm interrupt is issued. The PWMm interrupt period from the second time is fixed. Figure 11-5 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with no dead-time specified and continuous mode.

  • Page 254: With Dead-Time Specified

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.3.2 with dead-time specified When the PmDTMD bit of the PWMm control register 3 (PWmCON3) is set to “1”, setting the dead-time gets enabled and it generates forcibly the timing that de-activates both PWMm and PWMn at the same time. Specify the value of dead-time into PWMm duty (PWnDH, PWnDL) registers.
  • Page 255 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PmRUN bit is set to “1”, counting starts in synchronization with the PWMm clock. This causes an error of up to 1 clock pulse to the time the first PWMm interrupt is issued. The PWMm interrupt period from the second time is fixed.

  • Page 256: Pwm Coupled Mode / One Shot Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.4 PWM Coupled mode / One shot mode When the PmnMD bit of the PWMm control register 2 (PWmCON2) is set to “1” and the PmMD bit of PWmCON2 is set to “1”, PWMm, PWMn ({m, n}={4, 5}, {6, 7}) operates in coupled mode/one shot mode. For the details about start/ stop/clear operation and the update timing of the period/duty, see the section “11.3.5 PWM Control by the Software”...
  • Page 257 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PmRUN bit is set to “1”, counting starts in synchronization with the PWMm clock. This causes an error of up to 1 clock pulse to the time the first PWMm interrupt is issued. The PWMm interrupt period from the second time is fixed. Figure 11-7 shows the operation timing of PWM4 and PWM5 on the condition of coupled mode with no dead-time specified and one shot mode.

  • Page 258: With Dead-Time Specified

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.4.2 with dead-time specified When the PmDTMD bit of the PWMm control register 3 (PWmCON3) is set to “1”, setting the dead-time gets enabled and it generates forcibly the timing that de-activates both PWMm and PWMn at the same time. Specifiy the value of dead-time into PWMn duty (PWnDH, PWnDL) registers.
  • Page 259 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM After the PmRUN bit is set to “1”, counting starts in synchronization with the PWMm clock. This causes an error of up to 1 clock pulse to the time the first PWMm interrupt is issued. The PWMm interrupt period from the second time is fixed.

  • Page 260: Pwm Control By The Software

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.5 PWM Control by the software 11.3.5.1 start/stop/clear operation The PWMn (n=4, 5, 6, 7) counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWMn clock (PnCK) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1” and starts incrementing the count value on the 2nd falling edge.

  • Page 261: Pwm Control By The External Input

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.6 PWM Control by the external input 11.3.6.1 start/stop/clear operation PWMn (n=4, 5, 6, 7) enables start control, stop control and counter clear control by using the external input which is selected by the PnTGSEL bit of PWMn control register 2 (PWnCON2) and PnT1SEL0, PnT0SEL0 bits of PWMn control register 4 (PWnCON4).

  • Page 262: Period And Duty Update

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.6.2 period and duty update When the PWMn counter is cleared by the external input, the value of PWMn duty register (PWnDH, PWnDL) is transferred to the PWMn duty buffer (PWnDBUF) at the timing of the counter clear, and the value of the PWMn period register (PWnPH, PWnPL) is transferred to the PWMn period buffer (PWnPBUF) at the timing of the counter clear.

  • Page 263: Pwm Control Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.7 PWM Control Mode 11.3.7.1 Software Start Mode By setting the PnSTM1 and PnSTM0 bits of the PWMn (n=4, 5, 6, 7) control register 2 (PWnCON2) to "0", the PWMn counters operate only under the control of the PnRUN bits. For the operation timing, see the section 11.3.1 to 11.3.5.
  • Page 264 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM PnRUN External input The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows selection of the "H/L"...

  • Page 265: External Input Start Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.7.3 External Input Start Mode With the setting of PnSTM1="1" and PnSTM0="0" of the PWMn control register 2 (PWnCON2), the PWM counter enables control by the edge of the external input. Note that the PnRUN bit is set to "1" in advance. If the PnRUN bit is "0", PWMn will not operates even when the edge input occurs on the selected external input.
  • Page 266 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM PnRUN External input The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output Count up PWnCH/L 0000 Count up 0000 0000 Count up 0000 Count up Counting stopped Counting stopped External input External input start...

  • Page 267: Software Start Or External Input Clear Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.7.4 Software Start or External Input Clear Mode With the setting of PnSTM1="1" and PnSTM0="1" on the PWMn control register 2 (PWnCON2), the PWM counter operates being controlled by the PnRUN bit. When there is no edge input on the external input selected by the PnTGSEL bit of the PWMn control register 2 (PWnCON2), the counter operates in the same way as the software start.
  • Page 268 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM PnRUN External input The PnINI bit allows selection of the "H/L" level for the PWM initial value. PWMn output The PnSTPSEL bit allows selection of whether or not to output the initial value while being paused When the initial value is output, the PnINI bit allows selection of the "H/L"...
  • Page 269 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM [Note] When the external input clear control is done at a timing when PWMn period register (PWnPH, PWnPL) or PWMn duty register (PWnDH, PWnDL) is changed while the PWM count is being stopped, transfer to the PWMn duty buffer (PWnDBUF) or PWMn period buffer (PWnPBUF) may delay for one PWM clock.

  • Page 270: Pwm Emergency Stop Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.3.8 PWM Emergency Stop Operation Setting the PmSDE1 and PmSDE0 bits of the PWMm control register 3 (PWmCON3) enables the emergency stop function with the external input that is selected by PmTGSEL. Note that the emergency stop function is valid only in the cooperation mode (PmnMD=“1”).
  • Page 271 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM External input P4RUN P4SDST PW4INT P4FLG/P5FLG PW4CH/L 0000 0000 Count up 0000 Count up 0000 Count up 0000 0000 stop & clear stop & clear Emergency Emergency The PnINI bit allows selection of stop stop the "H/L"...

  • Page 272: Specifying Port Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.4 Specifying Port Registers To output the PWM waveform, the applicable bit of each related port register needs to be set. For detail about the port registers, see chapter of the related port. [Note] PWM output is a high-impedance state until an output state is set by the port n control register 0, 1 (PnCON0, PnCON1) (n=2, 3, 4, 5, 6, 7, 8).

  • Page 273: Functioning P43 Pin (Pwm4) As Pwm Output

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.4.2 Functioning P43 Pin (PWM4) as PWM Output Set the P43MD1 bit (bit 3 of P4MOD1 register) to "1" and the P43MD0 bit (bit 3 of P4MOD0 register) to "0" for specifying the PWM4 as the tertiary function of P43. Register name P4MOD1 register (address: 0F249H) P47MD1...

  • Page 274: Functioning P35 Pin (Pwm5) As Pwm Output

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.4.3 Functioning P35 Pin (PWM5) as PWM Output Set the P35MD1 bit (bit 5 of P3MOD1 register) to "1" and the P35MD0 bit (bit 5 of P3MOD0 register) to "0" for specifying the PWM5 as the tertiary function of P35. Register name P3MOD1 register (address: 0F23BH) P36MD1...

  • Page 275: Functioning P47 Pin (Pwm5) As Pwm Output

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 11 PWM 11.4.4 Functioning P47 Pin (PWM5) as PWM Output Set the P47MD1 bit (bit 7 of P4MOD1 register) to "1" and the P47MD0 bit (bit 7 of P4MOD0 register) to "0" for specifying the PWM5 as the tertiary function of P47. Register name P4MOD1 register (address: 0F249H) P47MD1...
  • Page 276 Chapter 12 Synchronous Serial Port...

  • Page 277: Synchronous Serial Port (Ssio)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12 Synchronous Serial Port (SSIO) 12.1 General Description This LSI includes one channel of 8/16 bit synchronous serial port (SSIO). It can also be used to control the device incorporated with the SPI interface by using one port as the chip enable pin. For the input clock, see Chapter 6, “Clock Generation Circuit”.

  • Page 278: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.1.3 List of Pins Pin name Function Received data input. P40/SIN0 Used for the tertiary function of the P40 pins. Synchronous clock input/output. P41/SCK0 Used for the tertiary function of the P41 pins Transmitted data output.

  • Page 279: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2 Description of Registers 12.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F700H Serial port transmit/receive buffer L SIO0BUFL 8/16 SIO0BUF 0F701H Serial port transmit/receive buffer H SIO0BUFH －...

  • Page 280: Serial Port Transmit/Receive Buffers (Sio0Bufl, Sio0Bufh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL and SIO0BUFH) Address: 0F700H Access: R/W Access size: 8 /16 bits Initial value: 00H SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 Initial value Address: 0F701H Access: R/W Access size: 8 bits...

  • Page 281: Serial Port Control Register (Sio0Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.3 Serial Port Control Register (SIO0CON) Address: 0F702H Access: R/W Access size: 8 bits Initial value: 00H — — — — — — — SIO0CON S0EN — — — — — —...

  • Page 282: Serial Port Mode Register 0 (Sio0Mod0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.4 Serial Port Mode Register 0 (SIO0MOD0) Address: 0F704H Access: R/W Access size: 8/16 bits Initial value: 00H — — — — SIO0MOD0 S0LG S0MD1 S0MD0 S0DIR — — — — Initial value SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port.

  • Page 283: Serial Port Mode Register 1 (Sio0Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.2.5 Serial Port Mode Register 1 (SIO0MOD1) Address: 0F705H Access: R/W Access size: 8 bits Initial value: 00H — — — SIO0MOD1 S0CKT S0CK3 S0CK2 S0CK1 S0CK0 — — — Initial value SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port.

  • Page 284: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3 Description of Operation 12.3.1 Transmit Operation When “1” is written to the S0MD1 bit and "0" is written to the S0MD0 bit of the serial port mode register 0 (SIO0MOD0), this LSI is set to the transmit mode. When transmitted data is written to the serial port transmit/receive buffer (SIO0BUFL, SIO0BUFH) and the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission starts.

  • Page 285: Receive Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial port mode register 0 (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts.

  • Page 286: Transmit/Receive Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and "1" is written to the S0MD0 bit of the serial port mode register 0 (SIO0MOD0), this LSI is set to the transmit/receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission/reception starts.

  • Page 287: Specifying Port Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.4 Specifying port registers To enable the SSIO function, the applicable bit of each related port register needs to be set. See Chapter 19, "Port 4", Chapter 20, "Port 5", Chapter 22, "Port 7" and Chapter 23, "Port 8" for detail about the port registers. 12.4.1 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO/ “Master mode”...

  • Page 288: Functioning P42 (Sout0: Output), P41 (Sck0: Input/Output), And P40 (Sin0: Input) As The Ssio/ "Slave Mode

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 12 Synchronous Serial Port (SSIO) 12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO/ ”Slave mode” Set the P42MD1 to P40MD1 bits (P4MOD1 register bits 2 to 0) to “1” and the P42MD0 to P40MD0 bits (P4MOD0 register bits 2 to 0) to “0”...

  • Page 289: Uart

    Chapter 13 UART...

  • Page 290: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13 UART 13.1 General Description This LSI includes one channel of UART (Universal Asynchronous Receiver Transmitter), a full-duplex communication start-stop synchronous serial interface. This one full-duplex communication channel can be used as two independent half-duplex communication channels.

  • Page 291: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.1.3 List of Pins Pin name Function UART0 data input pin P02/RXD0 Used as the primary function of the P02 pin. UART0 data input pin P42/RXD0 Used as the secondary function of the P42 pin. UART0/1 data output pin P43/TXD0/TXD1 Used as the secondary or quartic function of the P43 pin.

  • Page 292: Uart0 Transmit/Receive Buffer (Ua0Buf)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F710H Access: R/W Access size: 8 bits Initial value: 00H UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 Initial value UA0BUF is a special function register (SFR) used to store the receive data in the full-duplex communication or the transmit/receive data in the half-duplex communication.

  • Page 293: Uart1 Transmit/Receive Buffer (Ua1Buf)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.3 UART1 Transmit/Receive Buffer (UA1BUF) Address: 0F718H Access: R/W Access size: 8 bits Initial value: 00H UA1BUF U1B7 U1B6 U1B5 U1B4 U1B3 U1B2 U1B1 U1B0 Initial value UA1BUF is a special function register (SFR) used to store the transmit data in the full-duplex communication or the transmit/receive data in the half-duplex communication.

  • Page 294: Uart0 Control Register (Ua0Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.4 UART0 Control Register (UA0CON) Address: 0F711H Access: R/W Access size: 8 bits Initial value: 00H UA0CON U0EN Initial value UA0CON is a special function register (SFR) used to control start/stop communication of the UART. [Description of bits] ...

  • Page 295: Uart1 Control Register (Ua1Con)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.5 UART1 Control Register (UA1CON) Address: 0F719H Access: R/W Access size: 8 bits Initial value: 00H UA1CON U1EN Initial value UA1CON is a special function register (SFR) used to control start/stop communication of the UART. UA1CON is used in half-duplex communication mode.

  • Page 296: Uart0 Mode Register 0 (Ua0Mod0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.6 UART0 Mode Register 0 (UA0MOD0) Address: 0F712H Access: R/W Access size: 8/16 bits Initial value: 00H UA0MOD0 U01HD U0RSS U0RSEL1 U0RSEL0 U0CK1 U0CK0 U0IO Initial value UA0MOD0 is a special function register (SFR) used to set the transfer mode of the UART. [Description of bits] ...
  • Page 297 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART  U01HD (bit 7) The U01HD bit is used to select full-duplex communication mode (1 channel) or half-duplex communication mode (2 channels). When U01HD is set to "0", the combination of UART0 and UART1 functions operates as full-duplex communication.

  • Page 298: Uart1 Mode Register 0 (Ua1Mod0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.7 UART1 Mode Register 0 (UA1MOD0) Address: 0F71AH Access: R/W Access size: 8/16 bits Initial value: 00H UA1MOD0 U1RSS U1RSEL1 U1RSEL0 U1CK1 U1CK0 U1IO Initial value UA1MOD0 is a special function register (SFR) used to set the transfer mode of the UART. UA1MOD0 register is used in half-duplex communication, and ,in full-duplex communication, UA1MOD0 register settings are invalid.

  • Page 299: Uart0 Mode Register 1 (Ua0Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.8 UART0 Mode Register 1 (UA0MOD1) Address: 0F713H Access: R/W Access size: 8 bits Initial value: 00H UA0MOD1 U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 Initial value UA0MOD1 is a special function register (SFR) used to set the transfer mode of the UART. [Description of bits] ...
  • Page 300 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART  U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR Description LSB first (initial value) MSB first [Note] Always set UA0MOD1 while communication is stopped, and do not rewrite it during communication. FEUL620Q150B 13-11...

  • Page 301: Uart1 Mode Register 1 (Ua1Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.9 UART1 Mode Register 1 (UA1MOD1) Address: 0F71BH Access: R/W Access size: 8/16 bits Initial value: 00H UA1MOD1 U1DIR U1NEG U1STP U1PT1 U1PT0 U1LG1 U1LG0 Initial value UA1MOD1 is a special function register (SFR) used to set the transfer mode of the UART. UA1MOD1 is used in half-duplex communication mode.
  • Page 302 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART  U1DIR (bit 6) The U1DIR bit is used to select LSB first or MSB first in the communication of the UART. U1DIR Description LSB first (initial value) MSB first [Note] Always set UA1MOD1 while communication is stopped, and do not rewrite it during communication. FEUL620Q150B 13-13...

  • Page 303: Uart0 Baud Rate Registers L, H (Ua0Brtl, Ua0Brth)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F714H Access: R/W Access size: 8/16 bits Initial value: 0FFH UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 Initial value Address: 0F715H Access: R/W Access size: 8 bits Initial value: 0FH UA0BRTH...

  • Page 304: Uart1 Baud Rate Registers L, H (Ua1Brtl, Ua1Brth)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH) Address: 0F71CH Access: R/W Access size: 8/16 bits Initial value: 0FFH UA1BRTL U1BR7 U1BR6 U1BR5 U1BR4 U1BR3 U1BR2 U1BR1 U1BR0 Initial value Address: 0F71DH Access: R/W Access size: 8 bits Initial value: 0FH UA1BRTH...

  • Page 305: Uart0 Status Register (Ua0Stat)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.12 UART0 Status Register (UA0STAT) Address: 0F716H Access: R/W Access size: 8 bits Initial value: 00H UA0STAT U0FUL U0PER U0OER U0FER Initial value UA0STAT is a special function register (SFR) used to indicate the UART state in receive operations. When any data is written to UA0STAT, all the bits are initialized to "0".
  • Page 306 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART  U0FUL (bit 3) U0FUL indicates the UART transmit/receive buffer state. • In the case of the full-duplex communication mode (U01HD="0") When the transmitted data is written in UA1BUF in transmit mode, this bit is set to "1" and when this transmitted data is transferred to the shift register, this bit is set to "0".

  • Page 307: Uart1 Status Register (Ua1Stat)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.2.13 UART1 Status Register (UA1STAT) Address: 0F71EH Access: R/W Access size: 8 bits Initial value: 00H UA1STAT U1FUL U1PER U1OER U1FER Initial value UA1STAT is a special function register (SFR) used to indicate the UART state in receive operations. When any data is written to UA1STAT, all the flags are initialized to "0".
  • Page 308 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART  U1FUL (bit 3) U1FUL indicates the UART transmit/receive buffer state. When the transmitted data is written in UA1BUF in transmit mode, this bit is set to "1" and when this transmitted data is transferred to the shift register, this bit is set to "0". To transmit the data consecutively, confirm the U1FUL bit becomes "0", then write the next transmitted data to the UA1BUF.

  • Page 309: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3 Description of Operation 13.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit.

  • Page 310: Baud Rate

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.2 Baud Rate Baud rates are generated by the baud rate generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate generator clock selection bits (UnCK1, UnCK0) of the UARTn mode register 0 (UAnMOD0). The count value of the baud rate generator can be set by writing it in the UARTn baud rate register H or L (UAnBRTH, UAnBRTL).

  • Page 311: Transmitted Data Direction

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.3 Transmitted Data Direction Figure 13-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. Data length: 8 bits LSB transmission LSB reception U0B7 U0B6 U0B5 U0B3 U0B2 U0B0 U0B4 U0B1 MSB transmission MSB reception Data length: 7 bits LSB reception...

  • Page 312: Transmit Operation (Full-Duplex Communication Mode)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.4 Transmit Operation (Full-Duplex Communication Mode) Figure 13-5 shows the transmission operation timing in full-duplex communication mode. The full-duplex communication mode is selected by setting the U01HD bit of UART0 mode register 0 (UA0MOD0) to "0".

  • Page 313: Transmit Operation (Half-Duplex Communication Mode)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.5 Transmit Operation (Half-Duplex Communication Mode) Figure 13-6 shows the transmission operation timing in half-duplex communication mode. The half-duplex communication mode is selected by setting the U01HD bit of UART0 mode register 0 (UA0MOD0) to "1".

  • Page 314: Receive Operation (Full-Duplex/Half-Duplex Communication Mode)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.6 Receive Operation (Full-Duplex/Half-Duplex Communication Mode) Figure 13-7 shows the operation timing for reception. Select the receive data pin using the UnRSEL bit of the UARTn mode register 0 (UAnMOD0). Reception is started by setting the U01HD bit of the UART0 mode register 0 (UA0MOD0) to "0" to select the full-duplex communication mode or setting U01HD bit to "1"...

  • Page 315: Detection Of Start Bit

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART UnEN reset enable period UnEN Stop RXDn Start Parity Start Parity Stop Internal transfer clock Shift register Parity Parity Stop Start Stop Start (Input stage) 1st data TX/RX buffer 2nd data UAnINT : Parity error UnPER : Overrun error UnOER...

  • Page 316: Sampling Timing

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.6.1 Detection of Start Bit The start bit is sampled with the baud rate generator clock (LSCLK , HSCLK, PLLCLK) which is selected by UnCK1, UnCK0 bits of UARTn mode register 0 (UAnMOD0). Therefore, the start bit detection may be delayed for one cycle of the baud rate generator clock at the maximum.
  • Page 317 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.3.6.3 Receive Margin If there is an error between the sender baud rate and the baud rate generated by the baud rate generator of this LSI, the error accumulates until the last stop bit loading in one frame, decreasing the receive margin. Figure 13-10 shows the baud rate errors and receive margin waveforms.

  • Page 318: Specifying Port Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4 Specifying Port Registers To enable the UART function, the applicable bit of each related port register needs to be set. See Chapter 15, "Port 0", Chapter 19, "Port 4", Chapter 20, "Port 5", Chapter 22, "Port 7", and Chapter 23, "Port 8" for details about the port registers.

  • Page 319: Functioning P43 (Txd1: Output) And P02 Pins (Rxd0: Input) As The Uart (Full-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.2 Functioning P43 (TXD1: Output) and P02 pins (RXD0: Input) as the UART (Full-duplex) Set the P43MD1 bit (bit 3 of P4MOD1 register) to "1" and set the P43MD0 bit (bit 3 of P4MOD0 register) to "1", to specify the UART as the quartic function of P43.
  • Page 320 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART The P02 pin is an input-only pin and does not need input/output selection by the register. The set value ($) is arbitrary for the P02C1 and P02C0 bits. Select an arbitrary input mode depending on the state of the external circuit to which the P02 pin is connected.

  • Page 321: Functioning P85 (Txd1: Output) And P86 Pins (Rxd0: Input) As The Uart (Full-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.3 Functioning P85 (TXD1: Output) and P86 pins (RXD0: Input) as the UART (Full-duplex) Set the P86MD1 to P85MD1 bits (bits 6 to 5 of P8MOD1 register) to "0", and set the P86MD0 to P85MD0 bits (bits 6 to 5 of P8MOD0 register) to "1", for specifying the UART as the secondary function of P86 and P85.

  • Page 322: Functioning P53 (Txd1: Output) And P03 Pins (Rxd1: Input) As The Uart (Half-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.4 Functioning P53 (TXD1: Output) and P03 pins (RXD1: Input) as the UART (Half-duplex) Set the P53MD1 bit (bit 3 of P5MOD1 register) to "0" and set the P53MD0 bit (bit 3 of P5MOD0 register) to "1", to specify the UART as the secondary function of P53.
  • Page 323 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART The P03 pin is an input-only pin and does not need input/output selection by the register. The set value ($) is arbitrary for the P03C1 and P03C0 bits. Select an arbitrary input mode depending on the state of the external circuit to which the P03 pin is connected.

  • Page 324: Functioning P55 (Txd0: Output) And P42 Pins (Rxd0: Input) As The Uart (Half-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.5 Functioning P55 (TXD0: Output) and P42 pins (RXD0: Input) as the UART (Half-duplex) Set the P55MD1 bit (bit 5 of P5MOD1 register) to "0" and set the P55MD0 bit (bit 5 of P5MOD0 register) to "1", to specify the UART as the secondary function of P55.
  • Page 325 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART Set the P42MD1 bit (bit 2 of P4MOD1 register) to "0" and set the P42MD0 bit (bit 2 of P4MOD0 register) to "1", to specify the UART as the secondary function of P42. Register P4MOD1 register (Address: 0F249H) name P47MD1...

  • Page 326: Functioning P43 (Txd0: Output) And P54 Pins (Rxd0: Input) As The Uart (Half-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.6 Functioning P43 (TXD0: Output) and P54 pins (RXD0: Input) as the UART (Half-duplex) Set the P43MD1 bit (bit 3 of P4MOD1 register) to "0" and set the P43MD0 bit (bit 3 of P4MOD0 register) to "1", to specify the UART as the secondary function of P43.
  • Page 327 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART Set the P54MD1 bit (bit 4 of P5MOD1 register) to "0" and set the P54MD0 bit (bit 4 of P5MOD0 register) to "1", to specify the UART as the secondary function of P54. Register name P5MOD1 register (address: 0F257H) P57MD1 P56MD1...

  • Page 328: Functioning P85 (Txd1: Output) And P72 Pins (Rxd1: Input) As The Uart (Half-Duplex)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART 13.4.7 Functioning P85 (TXD1: Output) and P72 pins (RXD1: Input) as the UART (Half-duplex) Set the P85MD1 bit (bit 5 of P8MOD1 register) to "0", and set the P85MD0 bit (bit 5 of P8MOD0 register) to "1", for specifying the UART as the secondary function of P85.
  • Page 329 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 13 UART Set the P72MD1 bit (bit 2 of P7MOD1 register) to "0" and set the P72MD0 bit (bit 2 of P7MOD0 register) to "1", to specify the UART as the secondary function of P72. Register P7MOD1 register (Address: 0F273H) name P74MD1...

  • Page 330: I C Bus Interface

    Chapter 14 I C Bus Interface...

  • Page 331: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14 I C Bus Interface 14.1 General Description This LSI includes 1 channel of I C bus interface (master). The I C bus interface data I/O pin and the I C bus interface clock I/O pin are assigned as the secondary function of the ports 4, 5, 6, and port 8.

  • Page 332: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.1.3 List of Pins Pin name Description C bus interface data input/output pin. P40/SDA Used for the secondary function of the P40 pin. C bus interface clock input/output pin. P41/SCL Used for the secondary function of the P41 pin. C bus interface data input/output pin.

  • Page 333: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2 Description of Registers 14.2.1 List of Registers Initial Address Name Symbol (Byte) Symbol (Word) Size value 0F740H C bus 0 receive register I2C0RD － － － － 0F741H Reserve 0F742H C bus 0 slave address register I2C0SA －...
  • Page 334 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.2 I C Bus 0 Receive Data Register (I2C0RD) Address: 0F740H Access: R Access size: 8 bits Initial value: 00H I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 Initial value I2C0RD is a read-only special function register (SFR) to store the received data.

  • Page 335: I 2 C Bus 0 Slave Address Register (I2C0Sa)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.3 I C Bus 0 Slave Address Register (I2C0SA) Address: 0F742H Access: R/W Access size: 8 bits Initial value: 00H I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW Initial value I2C0SA is a special function register (SFR) to set the address and the data direction bit of the slave device.

  • Page 336: I 2 C Bus 0 Transmit Data Register (I2C0Td)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.4 I C Bus 0 Transmit Data Register (I2C0TD) Address: 0F744H Access: R/W Access size: 8 bits Initial value: 00H I2C0TD0 I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 Initial value I2C0TD is a special function register (SFR) used to set the transmitted data.

  • Page 337: I 2 C Bus 0 Control Register 0 (I2C0Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.5 I C Bus 0 Control Register 0 (I2C0CON0) Address: 0F746H Access: R/W Access size: 8 bits Initial value: 00H I2C0CON0 I20ACT I20RS I20SP I20ST Initial value I2C0CON is a special function register (SFR) to control transmit and receive operations. [Description of Bits] ...

  • Page 338: I 2 C Bus 0 Mode Register L (I2C0Modl)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.6 I C Bus 0 Mode Register L (I2C0MODL) Address: 0F748H Access: R/W Access size: 8/16 bits Initial value: 00H I2C0MODL I20SYN I20DW1 I20DW0 I20MD I20EN Initial value I2C0MODL is a special function register (SFR) used to set the operation mode. [Description of Bits] ...

  • Page 339: I 2 C Bus 0 Mode Register H (I2C0Modh)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.7 I C Bus 0 Mode Register H (I2C0MODH) Address: 0F749H Access: R/W Access size: 8 bits Initial value: 02H I2C0MODH I20CD1 I20CD0 Initial value I2C0MODH is a special function register (SFR) used to set the operation mode. ...

  • Page 340: I 2 C Bus 0 Status Register (I2C0Stat)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.2.8 I C Bus 0 Status Register L (I2C0STAL) Address: 0F74AH Access: R Access size: 8 bits Initial value: 00H I2C0STAL I20ER I20ACR I20BB Initial value I2C0STAL is a read-only special function register (SFR) to indicate the state of the I C bus interface.

  • Page 341: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.3 Description of Operation 14.3.1 Communication Operation Mode Communication is started when communication mode is selected by using the I C bus 0 mode register L, H (I2C0MODL, I2C0MODH), the I C function is enabled by using the I20EN bit, a slave address and a data communication direction are C bus 0 slave address register (I2C0SA), and “1”...

  • Page 342: Communication Operation Timing

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.3.2 Communication Operation Timing Figures 14-2 to 14-4 show the operation timing and control method for each communication mode. Start Stop Restart Reception of Reception of Transmission of condition condition condition acknowledg acknowledg acknowledgment...
  • Page 343 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface Figure 14-5 shows the operation timing and control method when an acknowledgment error occurs. Acknowledge error Register I2C0SA=”xxxxxxx0B” setting I2C0CON0=”01H” I2C0CON0=”02H” Value of I2C0SA I2C0INT I20ST Value of I2C0RD I2C0SA I20ACR Figure 14-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide, the I20ER bit of the I C bus 0 status register L...

  • Page 344: Operation Waveforms

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.3.3 Operation Waveforms Figure 14-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 14-2 shows the relationship between communication speeds and clock counts of I C control clock (I2CCLK).

  • Page 345: Specifying Port Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 14 I C Bus Interface 14.4 Specifying port registers When you want to make sure the I2C bus interface function is working, please check related port registers are specified. See Chapter 19, “Port 4” , Chapter 20, “Port 5” , Chapter 21, “Port 6” and Chapter 23, “Port 8” for detail about the port registers. [Note] Proper operation cannot be guaranteed if multiple ports are set for one channel.
  • Page 346 Chapter 15 Port 0...

  • Page 347: Port 0

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15 Port 0 15.1 General Description This LSI includes the Port 0 consisting of 6-bit input port (P00 to P05) *. Port 0 functions as the external interrupt input pins, UART input pins, and PWM external input pins. See Chapter 31, “External interrupt Control Circuit”...

  • Page 348: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15.1.3 List of Pins Pin name Function P00/ Input port EXI0/ External 0 interrupt PW45EV0 PW45EV0 input P01/ Input port EXI1/ External 1 interrupt PW67EV0 PW67EV0 input P02/ Input port EXI2/ External 2 interrupt RXD0 UART0 data input (RXD0) P03/...

  • Page 349: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15.2 Description of Registers 15.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F20CH Port 0 data register Undefined 0F20EH Port 0 control register 0 P0CON0 8/16 P0CON 0F20FH Port 0 control register 1 P0CON1 FEUL620Q150B...

  • Page 350: Port 0 Data Register (P0D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15.2.2 Port 0 Data Register (P0D) Address: 0F20CH Access: R Access size: 8 bits Initial value: Undefined — — P05D P04D P03D P02D P01D P00D — — Initial value 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* * Depends on pin level when reading...

  • Page 351: Port 0 Control Registers 0, 1 (P0Con0, P0Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F20EH Access: R/W Access size: 8/16 bit Initial value: 00H — — P0CON0 P05C0 P04C0 P03C0 P02C0 P01C0 P00C0 — — Initial value Address: 0F20FH Access: R/W Access size: 8 bits...

  • Page 352: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 15 Port 0 15.3 Description of Operation 15.3.1 Input Port Function For the pins of Port 0, the setting of port 0 control registers 0, 1 (P0CON0, P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. High-impedance input mode is selected at system reset.
  • Page 353 Chapter 16 Port 1...

  • Page 354: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16 Port 1 16.1 General Description This LSI includes a 3-bit I/O port, Port 1 (P12, P13, P14). Port 1 can have a low-speed crystal oscillation pin (32.768 kHz) as a secondary function. To use it as a low-speed crystal oscillation pin, it needs setting by Code-Option.

  • Page 355: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 Pull-up Pull-down Data bus Controller P1DIR P1CON0,1 Port1 Output Controller Port1 FCON0 Input （OSCM1, OSCM0） Controller Low-speed cristalll oscillation circuit : Port 1 data register P1DIR : Port 1 direction register P1CON0 : Port 1 control register 0 P1CON1 : Port 1 control register 1 Figure 16-2 Configuration of P13 pin...

  • Page 356: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16.2 Description of Registers 16.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F21AH Port 1 data register Undefined 0F21BH Port 1 direction register P1DIR 0F21CH Port 1 control register 0 P1CON0 8/16 P1CON...

  • Page 357: Port 1 Data Register (P1D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16.2.2 Port 1 Data Register (P1D) Address: 0F21AH Access: R/W Access size: 8 bits Initial value: Undefined — — — — — P14D P13D P12D — — — — — Initial value 0/1* 0/1* * Depends on pin level when reading P1D is a special function register (SFR) used to set the values to be output to the Port 1 pins or to read the input levels of...

  • Page 358: Port 1 Direction Register (P1Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16.2.3 Port 1 Direction Register (P1DIR) Address: 0F21BH Access: R/W Access size: 8 bits Initial value: 14H — — — — — — P1DIR P14DIR P13DIR — — — — — — Initial value P1DIR is a special function register (SFR) to select the input/output mode of Port 1 (P14).

  • Page 359: Port 1 Control Registers 0,1 (P1Con0, P1Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16.2.4 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) Address: 0F21CH Access: R/W Access size: 8/16 bits Initial value: 10H — — — — — P1CON0 P14C0 P13C0 P12C0 — — — — —...
  • Page 360 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 When output mode is selected (P14DIR bit When input mode is selected (P14DIR bit = = "0") "1") P14C1 P14C0 Description P14 pin: High-impedance input P14 pin: Input with a pull-down resistor (initial value) The output setting is prohibited.

  • Page 361: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 16 Port 1 16.3 Description of Operation 16.3.1 Input Port Function For the P12 and P14 pins, one of high-impedance input mode, input mode with a pull-down resistor, and input mode with a pull-up resistor can be selected by setting the Port 1 control registers 0, 1 (P1CON0, P1CON1). At a system reset, as the initial status, P12 pin is selected to a high-impedance input mode, P14 pin is selected to input mode with a pull down resistor.
  • Page 362 Chapter 17 Port 2...

  • Page 363: Port2

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17 Port 2 17.1 General Description This LSI includes a 4-bit output-only port, Port 2 (P20 to P23). Port 2 can output the low-speed clock (LSCLK), high-speed clock (OUTCLK), PWM output (PWM4, PWM5, PWM6, PWM7), timer out (TMHAOUT, TMHBOUT) as the secondary, tertiary and quaternary function.

  • Page 364: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.1.3 List of Pins Pin name Primary function Secondary Tertiary function Quaternary function function P20/ LED0/ Output port, Low-speed clock PWM4 output (PWM4) output (LSCLK) LSCLK/ Direct LED drive* PWM4 P21/ LED1/ Output port, High-speed clock PWM5 output (PWM5) output (OUTCLK)

  • Page 365: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.2 Description of Registers 17.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F228H Port 2 data register 0F22AH Port 2 control register 0 P2CON0 8/16 P2CON 0F22BH Port 2 control register 1 P2CON1 0F22CH Port 2 mode register 0...

  • Page 366: Port 2 Data Register (P2D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.2.2 Port 2 Data Register (P2D) Address: 0F228H Access: R/W Access size: 8 bits Initial value: 00H — — — — P23D P22D P21D P20D — — — — Initial value P2D is a special function register (SFR) to set the output value of the Port 2. The value of this register is output to the Port 2 pin.

  • Page 367: Port 2 Control Registers 0, 1 (P2Con0, P2Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.2.3 Port 2 Control Registers 0, 1 (P2CON0, P2CON1) Address: 0F22AH Access: R/W Access size: 8/16 bits Initial value: 00H — — — — P2CON0 P23C0 P22C0 P21C0 P20C0 — — — — Initial value Address: 0F22BH Access: R/W...
  • Page 368 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 P23C1 P23C0 Description P23 pin: High-impedance output (initial value) P23 pin: P-channel open drain output P23 pin: N-channel open drain output P23 pin: CMOS output FEUL620Q150B 17-6...

  • Page 369: Port 2 Mode Registers 0, 1 (P2Mod0, P2Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.2.4 Port 2 Mode Register 0, 1 (P2MOD0, P2MOD1) Address: 0F22CH Access: R/W Access size: 8/16 bits Initial value: 00H — — — — P2MOD0 P23MD0 P22MD0 P21MD0 P20MD0 — — — — Initial value Address: 0F22DH Access: R/W...
  • Page 370 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2  P22MD0, P22MD1 (bit 2) The P22MD0 and P22MD1 bits are used to select the primary, secondary, tertiary, or quartic function of the P22 pin. Description P22MD1 P22MD0 General-purpose output port function/LED drive mode (initial value) Prohibited Timer A out output function (TMHAOUT) PWM output (PWM6)

  • Page 371: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 17 Port 2 17.3 Description of Operation 17.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0, 1 (P2CON0, P2CON1).
  • Page 372 Chapter 18 Port 3...
  • Page 373 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18 Port 3 18.1 General Description This LSI includes Port 3 consisting of 8-bit input/output ports (P30 to P37). Port 3 can use as an external interrupt input, successive approximation type A/D converter input and external input of PWM.

  • Page 374: Port3

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.1.2 Configuration Figure 18-1 shows the configuration of Port 3. Pull-up Data bus Pull-down Controller P3DIR P3MOD0,1 P3CON0,1 Port3 Output P30 to P37 PWM output (PWM4, PWM5) Controller LSCLK,OUTCLK PW45EV1,PW67EV1, PW45EV0,PW67EV0 AIN0 to AIN5 EXI6, EXI7 : Port 3 data register P3DIR...

  • Page 375: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.1.3 List of Pins Pin name Primary function Secondary function Tertiary function I/O port, P30/ External 6 interrupt EXI6/ PW45EV1 input, PW45EV1/ Successive approximation type AIN0 A/D converter input I/O port, P31/ External 7 interrupt EXI7/ PW67EV1 input, PW67EV1/...

  • Page 376: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.2 Description of Registers 18.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F236H Port 3 data register 0F237H Port 3 direction register P3DIR 0F238H Port 3 control register 0 P3CON0 8/16 P3CON...

  • Page 377: Port 3 Data Register (P3D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.2.2 Port 3 Data Register (P3D) Address: 0F236H Access: R/W Access size: 8 bits Initial value: 00H P37D P36D P35D P34D P33D P32D P31D P30D Initial value P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port In output mode, the value of this register is output to the Port 3 pin.
  • Page 378 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 P36D Description Output or input level of the P36 pin: "L" Output or input level of the P36 pin: "H" P37D Description Output or input level of the P37 pin: "L" Output or input level of the P37 pin: "H" [Note] When setting a value to the bit of the P3D by using bit operation instruction, input levels of the pin are written to the P3D if non- target bits are set as the input mode.

  • Page 379: Port 3 Direction Register (P3Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.2.3 Port 3 Direction Register (P3DIR) Address: 0F237H Access: R/W Access size: 8 bits Initial value: 00H P3DIR P37DIR P36DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Initial value P3DIR is a special function register (SFR) to select the input/output mode of Port 3. [Description of bits] ...

  • Page 380: Port 3 Control Registers 0, 1 (P3Con0, P3Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.2.4 Port 3 Control Registers 0, 1 (P3CON0, P3CON1) Address: 0F238H Access: R/W Access size: 8/16 bits Initial value: 00H P3CON0 P37C0 P36C0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Initial value Address: 0F239H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 381 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 When output mode is selected When input mode is selected (P32DIR bit = "0") (P32DIR bit = "1") P32C1 P32C0 Description P32 pin: High-impedance output (initial value) P32 pin: High-impedance input P32 pin: P-channel open drain output P32 pin: Input with a pull-down resistor P32 pin: N-channel open drain output P32 pin: Input with a pull-up resistor...

  • Page 382: Port 3 Mode Registers 0, 1 (P3Mod0, P3Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.2.5 Port 3 Mode Registers 0, 1 (P3MOD0, P3MOD1) Address: 0F23AH Access: R/W Access size: 8/16 bits Initial value: 00H P3MOD0 P37MD0 P36MD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Initial value Address: 0F23BH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 383 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3  P33MD1, P33MD0 (bit 3) The P33MD1 and P33MD0 bits are used to select the primary, secondary, or tertiary function of the P33 pin. P33MD1 P33MD0 Description General-purpose input/output port function (initial value) Prohibited Prohibited Prohibited...

  • Page 384: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 18 Port 3 18.3 Description of Operation 18.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0, 1 (P3CON0, P3CON1).
  • Page 385 Chapter 19 Port 4...

  • Page 386: Port4

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19 Port 4 19.1 General Description This LSI includes an 8-bit input/output port, Port 4 (P40 to P47). Port 4 can use the PWM output pins (PWM4, PWM5), UART pins (RXD0, TXD0,TXD1), synchronous serial port pins (SIN0, SCK0, SOUT0), and I C bus pins (SDA,SCL) as the secondary, tertiary, or quaternary function.

  • Page 387: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Quaternary function P40/ I/O port, CMP0M/ C bus data SSIO data Analogue comparator 0 SDA/ I/O pin input pin non-inverting input SIN0 P41/ I/O port,...

  • Page 388: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.2 Description of Registers 19.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F244H Port 4 data register 0F245H Port 4 direction register P4DIR 0F246H Port 4 control register 0 P4CON0 8/16 P4CON...

  • Page 389: Port 4 Data Register (P4D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.2.2 Port 4 Data Register (P4D) Address: 0F244H Access: R/W Access size: 8 bits Initial value: 00H P47D P46D P45D P44D P43D P42D P41D P40D Initial value P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4.
  • Page 390 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 P46D Description Output or input level of the P46 pin: "L" Output or input level of the P46 pin: "H" P47D Description Output or input level of the P47 pin: "L" Output or input level of the P47 pin: "H" [Note] When setting a value to the bit of the P4D by using bit operation instruction, input levels of the pin are written to the P4D if non- target bits are set as the input mode.

  • Page 391: Port 4 Direction Register (P4Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.2.3 Port 4 Direction Register (P4DIR) Address: 0F245H Access: R/W Access size: 8 bits Initial value: 00H P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Initial value P4DIR is a special function register (SFR) to select the input/output mode of Port 4. [Description of bits] ...

  • Page 392: Port 4 Control Registers 0, 1 (P4Con0, P4Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) Address: 0F246H Access: R/W Access size: 8/16 bits Initial value: 00H P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Initial value Address: 0F247H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 393 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 When output mode is selected When input mode is selected (P42DIR bit = "0") (P42DIR bit = "1") P42C1 P42C0 Description P42 pin: High-impedance output (initial value) P42 pin: High-impedance input P42 pin: P-channel open drain output P42 pin: Input with a pull-down resistor P42 pin: N-channel open drain output P42 pin: Input with a pull-up resistor...

  • Page 394: Port 4 Mode Registers 0, 1 (P4Mod0, P4Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F248H Access: R/W Access size: 8/16 bits Initial value: 00H P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Initial value Address: 0F249H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 395 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4  P43MD1, P43MD0 (bit 3) The P43MD1 and P43MD0 bits are used to select the primary, secondary, tertiary, or quaternary function of the P43 pin. P43MD1 P43MD0 Description General-purpose input/output mode (initial value) UART0 data output pin (TXD0) PWM4 output pin (PWM4) UART1 data output pin (TXD1)

  • Page 396: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 19 Port 4 19.3 Description of Operation 19.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0, 1 (P4CON0, P4CON1).
  • Page 397 Chapter 20 Port 5...

  • Page 398: Port5

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20 Port 5 20.1 General Description This LSI includes an 8-bit input/output port, Port 5 (P50 to P57) Port 5 can use the I C communication pins (SCL, SDA), PWM output pins (PWM6, PWM7), UART pins (RXD0, TXD0, RXD1, TXD1) and synchronous serial port pins (SIN0, SCK0, SOUT0) as the secondary, tertiary, or quaternary function.

  • Page 399: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.1.3 List of Pins Secondary Quaternary Pin name Primary function Tertiary function function function P50/ C data SSIO data SDA/ I/O port I/O (SDA) input pin SIN0 P51/ C clock SSIO clock SCL/ I/O port I/O (SCL) I/O pin...

  • Page 400: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.2 Description of Registers 20.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F252H Port 5 data register 0F253H Port 5 direction register P5DIR 0F254H Port 5 control register 0 P5CON0 8/16 P5CON...

  • Page 401: Port 5 Data Register (P5D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.2.2 Port 5 Data Register (P5D) Address: 0F252H Access: R/W Access size: 8 bits Initial value: 00H P57D P56D P55D P54D P53D P52D P51D P50D Initial value P5D is a special function register (SFR) to set the value to be output to the Port 5 pin or to read the input level of the Port 5.
  • Page 402 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 P56D Description Output or input level of the P56 pin: "L" Output or input level of the P56 pin: "H" P57D Description Output or input level of the P57 pin: "L" Output or input level of the P57 pin: "H" [Note] When setting a value to the bit of the P5D by using bit operation instruction, input levels of the pin are written to the P5D if non- target bits are set as the input mode.

  • Page 403: Port 5 Direction Register (P5Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.2.3 Port 5 Direction Register (P5DIR) Address: 0F253H Access: R/W Access size: 8 bits Initial value: 00H P5DIR P57DIR P56DIR P55DIR P54DIR P53DIR P52DIR P51DIR P50DIR Initial value P5DIR is a special function register (SFR) to select the input/output mode of Port 5. [Description of bits] ...

  • Page 404: Port 5 Control Registers 0, 1 (P5Con0, P5Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.2.4 Port 5 Control Registers 0, 1 (P5CON0, P5CON1) Address: 0F254H Access: R/W Access size: 8/16 bits Initial value: 00H P5CON0 P57C0 P56C0 P55C0 P54C0 P53C0 P52C0 P51C0 P50C0 Initial value Address: 0F255H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 405 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 When output mode is selected When input mode is selected (P52DIR bit = "0") (P52DIR bit = "1") P52C1 P52C0 Description P52 pin: High-impedance output (initial value) P52 pin: High-impedance input P52 pin: P-channel open drain output P52 pin: Input with a pull-down resistor P52 pin: N-channel open drain output P52 pin: Input with a pull-up resistor...

  • Page 406: Port 5 Mode Registers 0, 1 (P5Mod0, P5Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.2.5 Port 5 Mode Registers 0, 1 (P5MOD0, P5MOD1) Address: 0F256H Access: R/W Access size: 8/16 bits Initial value: 00H P5MOD0 P57MD0 P56MD0 P55MD0 P54MD0 P53MD0 P52MD0 P51MD0 P50MD0 Initial value Address: 0F257H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 407 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5  P53MD1, P53MD0 (bit 3) The P53MD1 and P53MD0 bits are used to select the primary, secondary, or tertiary function of the P53 pin. P53MD1 P53MD0 Description General-purpose input/output mode (initial value) UART1 data output pin (TXD1) PWM6 output pin (PWM6) Prohibited ...

  • Page 408: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 20 Port 5 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 5, either output or input is selected by setting the Port 5 direction register (P5DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 5 control registers 0, 1 (P5CON0, P5CON1).
  • Page 409 Chapter 21 Port 6...

  • Page 410: Port6

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21 Port 6 21.1 General Description This LSI includes an 8-bit input/output port, Port 6 (P60 to P67) Port 6 can use the low-speed clock (LSCLK) output, high-speed clock (OUTCLK) output, I C communication pins (SCL, SDA), PWM output pins (PWM4, PWM5, PWM6, PWM7) and timer out (TMHAOUT, TMHBOUT) as the secondary, tertiary, or quaternary function.

  • Page 411: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.1.3 List of Pins Secondary Quaternary Pin name Primary function Tertiary function function function P60/ SDA/ C data Timer A out I/O port PWM6 output TMHAOUT/ I/O (SDA) (TMHAOUT) PWM6 P61/ SCL/ C clock Timer B out I/O port PWM7 output...

  • Page 412: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.2 Description of Registers 21.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F260H Port 6 data register 0F261H Port 6 direction register P6DIR 0F262H Port 6 control register 0 P6CON0 8/16 P6CON...

  • Page 413: Port 6 Data Register (P6D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.2.2 Port 6 Data Register (P6D) Address: 0F260H Access: R/W Access size: 8 bits Initial value: 00H P67D P66D P65D P64D P63D P62D P61D P60D Initial value P6D is a special function register (SFR) to set the value to be output to the Port 6 pin or to read the input level of the Port 6. In output mode, the value of this register is output to the Port 6 pin.
  • Page 414 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 P66D Description Output or input level of the P66 pin: "L" Output or input level of the P66 pin: "H" P67D Description Output or input level of the P67 pin: "L" Output or input level of the P67 pin: "H" [Note] When setting a value to the bit of the P6D by using bit operation instruction, input levels of the pin are written to the P6D if non- target bits are set as the input mode.

  • Page 415: Port 6 Direction Register (P6Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.2.3 Port 6 Direction Register (P6DIR) Address: 0F261H Access: R/W Access size: 8 bits Initial value: 00H P6DIR P67DIR P66DIR P65DIR P64DIR P63DIR P62DIR P61DIR P60DIR Initial value P6DIR is a special function register (SFR) to select the input/output mode of Port 6. [Description of bits] ...

  • Page 416: Port 6 Control Registers 0, 1 (P6Con0, P6Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.2.4 Port 6 Control Registers 0, 1 (P6CON0, P6CON1) Address: 0F262H Access: R/W Access size: 8/16 bits Initial value: 00H P6CON0 P67C0 P66C0 P65C0 P64C0 P63C0 P62C0 P61C0 P60C0 Initial value Address: 0F263H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 417 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 When output mode is selected When input mode is selected (P62DIR bit = "0") (P62DIR bit = "1") P62C1 P62C0 Description P62 pin: High-impedance output (initial value) P62 pin: High-impedance input P62 pin: P-channel open drain output P62 pin: Input with a pull-down resistor P62 pin: N-channel open drain output P62 pin: Input with a pull-up resistor...

  • Page 418: Port 6 Mode Registers 0, 1 (P6Mod0, P6Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.2.5 Port 6 Mode Registers 0, 1 (P6MOD0, P6MOD1) Address: 0F264H Access: R/W Access size: 8/16 bits Initial value: 00H P6MOD0 P67MD0 P66MD0 P65MD0 P64MD0 P63MD0 P62MD0 P61MD0 P60MD0 Initial value Address: 0F265H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 419 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6  P63MD1, P63MD0 (bit 3) The P63MD1 and P63MD0 bits are used to select the primary function of the P63 pin. P63MD1 P63MD0 Description General-purpose input/output mode (initial value) Prohibited Prohibited Prohibited  P64MD1, P64MD0 (bit 4) The P64MD1 and P64MD0 bits are used to select the primary or tertiary function of the P64 pin.

  • Page 420: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 21 Port 6 21.3 Description of Operation 21.3.1 Input/Output Port Functions For each pin of Port 6, either output or input is selected by setting the Port 6 direction register (P6DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 6 control registers 0, 1 (P6CON0, P6CON1).
  • Page 421 Chapter 22 Port 7...

  • Page 422: Port7

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22 Port 7 22.1 General Description This LSI includes a 5-bit input/output port, Port 7 (P70 to P74) Port 7 can use the PWM output pins (PWM6, PWM7), UART pins (TXD0, RXD1, TXD1) and synchronous serial port pins (SCK0, SIN0, SOUT0) as the secondary, tertiary, or quaternary function.

  • Page 423: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.1.3 List of Pins Pin name Primary function Secondary function Tertiary function Quaternary function P70/ I/O port PWM6 output PWM6 P71/ I/O port PWM7 output PWM7 P72/ RXD1/ I/O port UART1 data input SSIO data input SIN0 P73/...

  • Page 424: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.2 Description of Registers 22.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F26EH Port 7 data register 0F26FH Port 7 direction register P7DIR 0F270H Port 7 control register 0 P7CON0 8/16 P7CON...

  • Page 425: Port 7 Data Register (P7D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.2.2 Port 7 Data Register (P7D) Address: 0F26EH Access: R/W Access size: 8 bits Initial value: 00H — — — P74D P73D P72D P71D P70D — — — Initial value P7D is a special function register (SFR) to set the value to be output to the Port 7 pin or to read the input level of the Port 7. In output mode, the value of this register is output to the Port 7 pin.

  • Page 426: Port 7 Direction Register (P7Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.2.3 Port 7 Direction Register (P7DIR) Address: 0F26FH Access: R/W Access size: 8 bits Initial value: 00H — — — P7DIR P74DIR P73DIR P72DIR P71DIR P70DIR — — — Initial value P7DIR is a special function register (SFR) to select the input/output mode of Port 7. [Description of bits] ...
  • Page 427 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.2.4 Port 7 Control Registers 0, 1 (P7CON0, P7CON1) Address: 0F270H Access: R/W Access size: 8/16 bits Initial value: 00H — — — P7CON0 P74C0 P73C0 P72C0 P71C0 P70C0 — — — Initial value Address: 0F271H Access: R/W Access size: 8 bits...
  • Page 428 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 When output mode is selected (P72DIR bit = When input mode is selected (P72DIR "0") bit = "1") P72C1 P72C0 Description P72 pin: High-impedance output (initial value) P72 pin: High-impedance input P72 pin: P-channel open drain output P72 pin: Input with a pull-down resistor P72 pin: N-channel open drain output P72 pin: Input with a pull-up resistor...

  • Page 429: Port 7 Mode Registers 0, 1 (P7Mod0, P7Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.2.5 Port 7 Mode Registers 0, 1 (P7MOD0, P7MOD1) Address: 0F272H Access: R/W Access size: 8/16 bit Initial value: 00H — — — P7MOD0 P74MD0 P73MD0 P72MD0 P71MD0 P70MD0 — — — Initial value Address: 0F273H Access: R/W Access size: 8 bits...
  • Page 430 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7  P73MD1, P73MD0 (bit 3) The P73MD1 and P73MD0 bits are used to select the primary, secondary, tertiary, or quaternary function of the P73 pin. P73MD1 P73MD0 Description General-purpose output port function (initial value) UART1 data output pin (TXD1) SSIO clock I/O pin (SCK0) UART0 data output pin (TXD0)

  • Page 431: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 22 Port 7 22.3 Description of Operation 22.3.1 Input/Output Port Functions For each pin of Port 7, either output or input is selected by setting the Port 7 direction register (P7DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 7 control registers 0, 1 (P7CON0, P7CON1).
  • Page 432 Chapter 23 Port 8...

  • Page 433: Port8

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23 Port 8 23.1 General Description This LSI includes an 8-bit input/output port, Port 8 (P80 to P87). Port 8 can use the I C communication pins (SDA, SCL), PWM output pins (PWM4, PWM5), UART pins (TXD0, RXD0, TXD1, RXD1) and synchronous serial port pins (SCK0, SIN0, SOUT0) as the secondary or tertiary function.

  • Page 434: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.1.3 List of Pins Pin name Primary function Secondary function Tertiary function P80/ C data SDA/ I/O port SSIO data input I/O (SDA) SIN0 P81/ C clock SCL/ I/O port SSIO clock I/O I/O (SCL) SCK0 P82/...

  • Page 435: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.2 Description of Registers 23.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F27CH Port 8 data register 0F27DH Port 8 direction register P8DIR 0F27EH Port 8 control register 0 P8CON0 8/16 P8CON...

  • Page 436: Port 8 Data Register (P8D)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.2.2 Port 8 Data Register (P8D) Address: 0F27CH Access: R/W Access size: 8 bits Initial value: 00H P87D P86D P85D P84D P83D P82D P81D P80D Initial value P8D is a special function register (SFR) to set the value to be output to the Port 8 pin or to read the input level of the Port 8. In output mode, the value of this register is output to the Port 8 pin.
  • Page 437 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 P86D Description Output or input level of the P86 pin: "L" Output or input level of the P86 pin: "H" P87D Description Output or input level of the P87 pin: "L" Output or input level of the P87 pin: "H" [Note] When setting a value to the bit of the P8D by using bit operation instruction, input levels of the pin are written to the P8D if non- target bits are set as the input mode.

  • Page 438: Port 8 Direction Register (P8Dir)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.2.3 Port 8 Direction Register (P8DIR) Address: 0F27DH Access: R/W Access size: 8 bits Initial value: 00H P8DIR P87DIR P86DIR P85DIR P84DIR P83DIR P82DIR P81DIR P80DIR Initial value P8DIR is a special function register (SFR) to select the input/output mode of Port 8. [Description of bits] ...

  • Page 439: Port 8 Control Registers 0, 1 (P8Con0, P8Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.2.4 Port 8 Control Registers 0, 1 (P8CON0, P8CON1) Address: 0F27EH Access: R/W Access size: 8/16 bits Initial value: 00H P8CON0 P87C0 P86C0 P85C0 P84C0 P83C0 P82C0 P81C0 P80C0 Initial value Address: 0F27FH Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 440 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 When output mode is selected When input mode is selected (P82DIR bit = "0") (P82DIR bit = "1") P82C1 P82C0 Description P82 pin: High-impedance output (initial value) P82 pin: High-impedance input P82 pin: P-channel open drain output P82 pin: Input with a pull-down resistor P82 pin: N-channel open drain output P82 pin: Input with a pull-up resistor...

  • Page 441: Port 8 Mode Registers 0, 1 (P8Mod0, P8Mod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.2.5 Port 8 Mode Registers 0, 1 (P8MOD0, P8MOD1) Address: 0F280H Access: R/W Access size: 8/16 bits Initial value: 00H P8MOD0 P87MD0 P86MD0 P85MD0 P84MD0 P83MD0 P82MD0 P81MD0 P80MD0 Initial value Address: 0F281H Access: R/W Access size: 8 bits Initial value: 00H...
  • Page 442 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8  P83MD1, P83MD0 (bit 3) The P83MD1 and P83MD0 bits are used to select the primary or tertiary function of the P83 pin. P83MD1 P83MD0 Description General-purpose output port function (initial value) Prohibited PWM5 output pin (PWM5) Prohibited ...

  • Page 443: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 23 Port 8 23.3 Description of Operation 23.3.1 Input/Output Port Functions For each pin of Port 8, either output or input is selected by setting the Port 8 direction register (P8DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 8 control registers 0, 1 (P8CON0, P8CON1).
  • Page 444 Chapter 24 Successive Approximation Type A/D Converter...

  • Page 445: Successive Approximation Type A/D Converter (Sa-Adc)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24 Successive Approximation Type A/D Converter (SA-ADC) 24.1 General Description This LSI has an internal 12-channel successive approximation type A/D converter (SA-ADC). The successive approximation type A/D converter works only when the DSAD bit of the block control register 4 (BLKCON4) is set to "0"...
  • Page 446 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.1.3 List of Pins Pin name Function Positive power supply pin for the successive approximation type A/D converter Reference power supply pin for the successive approximation type A/D converter Negative power supply pin for the successive approximation type A/D converter P30/ AIN0 Successive approximation type A/D converter input pin 0 P31/ AIN1...

  • Page 447: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2 Description of Registers 24.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) Size Initial value 0F8D0H SA-ADC result register 0L SADR0L 8/16 SADR0 0F8D1H SA-ADC result register 0H SADR0H 0F8D2H SA-ADC result register 1L...

  • Page 448: Sa-Adc Result Register 0L (Sadr0L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F8D0H Access: R Access size: 8/16 bits Initial value: 00H SADR0L SAR03 SAR02 Initial value SADR0L is a special function register (SFR) used to store SA-ADC conversion results on channel 0. SADR0L is updated after A/D conversion.

  • Page 449: Sa-Adc Result Register 1L (Sadr1L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F8D2H Access: R Access size: 8/16 bits Initial value: 00H SADR1L SAR13 SAR12 Initial value SADR1L is a special function register (SFR) used to store SA-ADC conversion results on channel 1. SADR1L is updated after A/D conversion.

  • Page 450: Sa-Adc Result Register 2L (Sadr2L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.6 SA-ADC Result Register 2L (SADR2L) Address: 0F8D4H Access: R Access size: 8/16 bits Initial value: 00H SADR2L SAR23 SAR22 Initial value SADR2L is a special function register (SFR) used to store SA-ADC conversion results on channel 2. SADR2L is updated after A/D conversion.

  • Page 451: Sa-Adc Result Register 3L (Sadr3L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.8 SA-ADC Result Register 3L (SADR3L) Address: 0F8D6H Access: R Access size: 8/16 bits Initial value: 00H SADR3L SAR33 SAR32 Initial value SADR3L is a special function register (SFR) used to store SA-ADC conversion results on channel 3. SADR3L is updated after A/D conversion.

  • Page 452: Sa-Adc Result Register 4L (Sadr4L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.10 SA-ADC Result Register 4L (SADR4L) Address: 0F8D8H Access: R Access size: 8/16 bits Initial value: 00H SADR4L SAR43 SAR42 Initial value SADR4L is a special function register (SFR) used to store SA-ADC conversion results on channel 4. SADR4L is updated after A/D conversion.

  • Page 453: Sa-Adc Result Register 5L (Sadr5L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.12 SA-ADC Result Register 5L (SADR5L) Address: 0F8DAH Access: R Access size: 8/16 bits Initial value: 00H SADR5L SAR53 SAR52 Initial value SADR5L is a special function register (SFR) used to store SA-ADC conversion results on channel 5. SADR5L is updated after A/D conversion.

  • Page 454: Sa-Adc Result Register 6L (Sadr6L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.14 SA-ADC Result Register 6L (SADR6L) Address: 0F8DCH Access: R Access size: 8/16 bits Initial value: 00H SADR6L SAR63 SAR62 Initial value SADR6L is a special function register (SFR) used to store SA-ADC conversion results on channel 6. SADR6L is updated after A/D conversion.

  • Page 455: Sa-Adc Result Register 7L (Sadr7L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.16 SA-ADC Result Register 7L (SADR7L) Address: 0F8DEH Access: R Access size: 8/16 bits Initial value: 00H SADR7L SAR73 SAR72 Initial value SADR7L is a special function register (SFR) used to store SA-ADC conversion results on channel 7. SADR7L is updated after A/D conversion.

  • Page 456: Sa-Adc Result Register 8L (Sadr8L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.18 SA-ADC Result Register 8L (SADR8L) Address: 0F8E0H Access: R Access size: 8/16 bits Initial value: 00H SADR8L SAR83 SAR82 Initial value SADR8L is a special function register (SFR) used to store SA-ADC conversion results on channel 8. SADR8L is updated after A/D conversion.

  • Page 457: Sa-Adc Result Register 9L (Sadr9L)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.20 SA-ADC Result Register 9L (SADR9L) Address: 0F8E2H Access: R Access size: 8/16 bits Initial value: 00H SADR9L SAR93 SAR92 Initial value SADR9L is a special function register (SFR) used to store SA-ADC conversion results on channel 9. SADR9L is updated after A/D conversion.

  • Page 458: Sa-Adc Result Register Al (Sadral)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.22 SA-ADC Result Register AL (SADRAL) Address: 0F8E4H Access: R Access size: 8/16 bits Initial value: 00H SADRAL SARA3 SARA2 Initial value SADRAL is a special function register (SFR) used to store SA-ADC conversion results on channel A. SADRAL is updated after A/D conversion.

  • Page 459: Sa-Adc Result Register Bl (Sadrbl)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.24 SA-ADC Result Register BL (SADRBL) Address: 0F8E6H Access: R Access size: 8/16 bits Initial value: 00H SADRBL SARB3 SARB2 Initial value SADRBL is a special function register (SFR) used to store SA-ADC conversion results on channel B. SADRBL is updated after A/D conversion.

  • Page 460: Sa-Adc Control Register 0 (Sadcon0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.26 SA-ADC Control Register 0 (SADCON0) Address: 0F8F0H Access: R/W Access size: 8/16 bits Initial value: 00H SADCON0 SACK SALP Initial value SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of bits] ...

  • Page 461: Sa-Adc Control Register 1 (Sadcon1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.27 SA-ADC Control Register 1 (SADCON1) Address: 0F8F1H Access: R/W Access size: 8 bits Initial value: 00H SADCON1 SARUN Initial value SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of bits] ...

  • Page 462: Sa-Adc Mode Register 0 (Sadmod0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.28 SA-ADC Mode Register 0 (SADMOD0) Address: 0F8F2H Access: R/W Access size: 8/16 bits Initial value: 00H SADMOD0 SACH7 SACH6 SACH5 SACH4 SACH3 SACH2 SACH1 SACH0 Initial value SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s). [Description of bits] The SACH7 to SACH0 bits are used to select channel(s) on which A/D conversion is performed.
  • Page 463 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter  SACH7 (bit 7) SACH7 Description Stops conversion on channel 7 (initial value) Performs conversion on channel 7. [Note] Do not start A/D conversion in the state in which all of the SACHB to SACH0 bits of SA-ADC mode register 0, 1 (SADMOD0,1) are "0".

  • Page 464: Sa-Adc Mode Register 1 (Sadmod1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.2.29 SA-ADC Mode Register 1 (SADMOD1) Address: 0F8F3H Access: R/W Access size: 8 bits Initial value: 00H SADMOD1 SACHB SACHA SACH9 SACH8 Initial value SADMOD1 is a special function register (SFR) used to choose A/D conversion channel(s). [Description of bits] The SACH8 to SACHB bits are used to select channel(s) on which A/D conversion is performed.

  • Page 465: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.3 Description of Operation 24.3.1 Setting of A/D Conversion Channels According to the setting of SA-ADC mode register 0, 1 (SADMOD0, SADMOD1), A/D conversion is performed as shown below and A/D conversion results are stored in the SA-ADC result register. SA-ADC SA-ADC Remarks...

  • Page 466: Operation Of The Successive Approximation Type A/D Converter

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 24 Successive Approximation Type A/D Converter 24.3.2 Operation of the Successive Approximation Type A/D Converter Operate SA-ADC in the following procedure. 1． Before starting SA-ADC, start oscillation of the high-speed clock (OSCLK) and wait until the oscillator settles. 2．...
  • Page 467 Chapter 25 Analog Comparator...

  • Page 468: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25 Analog Comparator 25.1 General Description This LSI includes 1 channel of analog comparator (comparator 0). Voltage comparison between two pins (CMP0P, CMP0M) that are input to the comparator is available. 25.1.1 Features ...

  • Page 469: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25.2 Description of Registers 25.2.1 List of Registers Address Name Symbol (Byte) Symbol Size Initial (Word) value 0F950H Comparator 0 control register 0 CMP0CON0 8/16 CMP0CON 0F951H Comparator 0 control register 1 CMP0CON1 FEUL620Q150B 25-2...

  • Page 470: Comparator 0 Control Register 0 (Cmp0Con0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25.2.2 Comparator 0 Control Register 0 (CMP0CON0) Address: 0F950H Access: R/W Access size: 8/16 bit Initial value: 00H — — — — — — CMP0D CMP0EN CMP0CON0 — — — — — — Initial value CMP0CON0 is a special function register (SFR) to control the comparator 0.

  • Page 471: Comparator 0 Control Register 1 (Cmp0Con1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25.2.3 Comparator 0 Control Register 1 (CMP0CON1) Address: 0F951H Access: R/W Access size: 8 bits Initial value: 00H — — — — — CMP0CON CMP0SM0 CMP0E1 CMP0E0 — — — — — Initial value CMP0CON1 is a special function register (SFR) to control the comparator 0 interrupt.

  • Page 472: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25.3 Description of Operation 25.3.1 Comparator Functions The comparator 0 compares the input voltages of the CMP0P and CMP0M pins to output the result to the CMP0D bit of the comparator 0 control register 0 (CMP0CON0). To use the comparator, set the port to a high-impedance output in advance.

  • Page 473: Interrupt Request

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 25 Analog Comparator 25.3.2 Interrupt Request When an interrupt edge selected by the comparator 0 control register 1 (CMP0CON1) occurs on the comparison result of the comparator 0, a comparator 0 interrupt (CMP0INT) is generated. For the comparator 0 interrupt, the edge can be selected.

  • Page 474: Lld (Low Level Detector)

    Chapter 26 LLD (Low Level Detector)

  • Page 475: General Description

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 26 LLD Circuit 26 LLD (Low Level Detector) 26.1 General Description This LSI includes a Low Level Detector (LLD). 26.1.1 Features  Four levels of threshold voltage can be selected by setting Code-Option.  The operation (reset or interrupt) to be performed when the voltage drops below the threshold can be selected by setting Code-Option.

  • Page 476: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 26 LLD Circuit 26.2 Description of Registers 26.2.1 List of Registers Address Name Symbol (Byte) Symbol Size Initial (Word) value 0F8C1H LLD circuit control register 1 LLDCON1 FEUL620Q150B 26-2...

  • Page 477: Lld Circuit Control Register 1 (Lldcon1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 26 LLD Circuit 26.2.2 LLD Circuit Control Register 1 (LLDCON1) Address: 0F8C1H Access: R/W Access size: 8 bits Initial value: 00H — — — — — — LLDCON1 LLDF ENBL — — — — — — Initial value LLDCON1 is a special function register (SFR) used to control the LLD circuit.

  • Page 478: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 26 LLD Circuit 26.3 Description of Operation 26.3.1 Threshold Voltage The value of the threshold voltage of the LLD circuit can be selected by Code-Option. For Code-Option, see Chapter 30, "Code-Option". For the characteristics of the threshold voltage, see "Appendix C Electrical Characteristics". 26.3.2 Operation of LLD Circuit Activation (ON) and deactivation (OFF) of LLD circuit are controlled by setting the ENBL bit of the LLD circuit control register 1 (LLDCON1), and the result of comparison of the power supply voltage (V...
  • Page 479 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 26 LLD Circuit Operation ↓ ↓ ↓ ENBL Hysteresis width Threshold voltage Threshold voltage reset signal Program is operating system reset Program is operating Figure 26-3 Example of Operation Timing Diagram When LLD Reset is Selected The operations in Figure 26-3 are described below.

  • Page 480: Power Supply Circuit

    Chapter 27 Power Supply Circuit...

  • Page 481: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 27 Power Supply Circuit 27 Power Supply Circuit 27.1 General Description This LSI includes a voltage regulator circuit for internal logic (VRL). The VRL outputs the operating voltage, V , of the internal logic circuit, program memory, RAM, etc. 27.1.1 Features ...

  • Page 482: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 27 Power Supply Circuit 27.2 Description of Operation After power-on, the V voltage becomes approximately 1.5 V in any operation mode. Figure 27-2 shows the operation waveforms of the power supply circuit. RESET_N pin Oscillation stabilization time Oscillation stabilization time System reset Logic power supply...

  • Page 483: On-Chip Debug Function

    Chapter 28 On-chip Debug Function...

  • Page 484: How To Connect The On-Chip Debug Emulator

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 28 On-chip Debug Function 28 On-chip Debug Function 28.1 General Description This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (uEASE) is connected to this LSI to perform the on-chip debug function. For the on-chip debug emulator (uEASE), see the “uEASE User’s Manual.”...
  • Page 485 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 28 On-chip Debug Function [Note] • Do not program to this LSI with an application program code that sets P14DIR bit of port1 direction register (P1DIR) to”0”. Because the program code is executed before µEASE accesses to this LSI, P14/TEST0 pin gets output mode and from then on, the LSI cannot enter the on-chip debug mode.

  • Page 486: Flash Memory Rewrite Function

    Chapter 29 Flash Memory Rewrite Function...

  • Page 487: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29 FLASH Memory Rewrite Function 29.1 General Description This LSI includes the boot area remap function and the function that rewrite the content of the flash memory (program memory space) using a special function register (SFR) programmatically. 29.1.1 Features ...

  • Page 488: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2 Description of Registers 29.2.1 List of Registers Address Name Symbol Symbol Size Initial (Byte) (Word) value 0F0E0H Flash address register L FLASHAL 8/16 FLASHA 0F0E1H Flash address register H FLASHAH 0F0E2H Flash data register L FLASHDL...
  • Page 489 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.2 Flash Address Register (FLASHAL, FLASHAH) Address: 0F0E0H Access: R/W Access size: 8/16 bits Initial value: 00H FLASHAL Initial value Address: 0F0E1H Access: R/W Access size: 8 bits Initial value: 00H FLASHAH FA15 FA14...
  • Page 490 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-1 Address Setting Values for Block Erase (ML620Q151B/ML620Q154B/ML620Q157B) Area for block erase* FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH Segment 0 0:4000H 0:5FFFH 0:6000H 0:7DFFH Segment 7 7:0000H 7:07FFH * The unit of block is 8 KB for the segment 0 and 2 KB for the segment 7.
  • Page 491 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-3 Address Setting Values for Block Erase (ML620Q152B/ML620Q155B/ML620Q158B) Area for block erase* FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH 0:4000H 0:5FFFH Segment 0 0:6000H 0:7FFFH 0:8000H 0:9FFFH 0:0A000H 0:0BDFFH Segment 7 7:0000H 7:07FFH...
  • Page 492 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Table 29-5 Address Setting Values for Block Erase (ML620Q153B/ML620Q156B/ML620Q159B) Area for block erase* FLASHSEG FLASHAH Segment Address 0:0000H 0:1FFFH 0:2000H 0:3FFFH 0:4000H 0:5FFFH 0:6000H 0:7FFFH Segment 0 0:8000H 0:9FFFH 0:A000H 0:BFFFH 0:C000H 0:DFFFH 0:E000H...
  • Page 493 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.3 Flash Data Register (FLASHDL, FLASHDH) Address: 0F0E2H Access: R/W Access size: 8/16 bits Initial value: 00H FLASHDL Initial value Address: 0F0E3H Access: R/W Access size: 8 bits Initial value: 00H FLASHDH FD15 FD14...

  • Page 494: Flash Control Register (Flashcon)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.4 Flash Control Register (FLASHCON) Address: 0F0E4H Access: W Access size: 8 bits Initial value: 00H — — — — — — FLASHCON FSERA FERS — — — — — — Initial value FLASHCON is a write-only special function register (SFR) to control the block erase and sector erase for the flash memory rewrite.

  • Page 495: Flash Acceptor (Flashacp)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.5 Flash Acceptor (FLASHACP) Address: 0F0E6H Access: W Access size: 8 bits Initial value: 00H FLASHACP fac7 fac6 fac5 fac4 fac3 fac2 fac1 fac0 Initial value FLASHACP is a write-only special function register (SFR) to control the block erase or sector erase for the flash memory rewrite or enable/disable the 1-word write operation.

  • Page 496: Flash Self Register (Flashslf)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.7 Flash Self Register (FLASHSLF) Address: 0F0EAH Access: R/W Access size: 8 bits Initial value: 00H — — — — — — — FLASHSLF FSELF — — — — — — —...

  • Page 497: Flash Remap Register (Remapadd)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.2.8 Flash Remap Register (REMAPADD) Address: 0F0ECH Access: R/W Access size: 8 bits Initial value: 00H REMAPADD RBTA RES2 RES1 RES0 REA15 REA14 REA13 REA12 Initial value REMAPADD is a special function register (SFR) used to specify the remap area. In REMAPADD, the following two types of remapping can be specified.

  • Page 498: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3 Description of Operation When using the flash memory rewrite function, prepare the program for flash memory rewrite in advance on a program code area with addresses that are not used for block erase/sector erase or 1-word write. The flash memory rewrite function includes the block erase function that erases by 4 K words (8 Kbytes), the sector erase function that erases by 512 words (1 Kbyte), and the 1-word write function that writes by 1 word (2 bytes).
  • Page 499 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Note on debugging flash memory rewrite code using the U16 development environment. are described below. Table 29-8 Cautions When Debugging Flash Self-Write Code State of use Cautions • Do not perform real time execution (GO execution) while break points When debugging flash are set in the flash memory rewrite sequence (from writing to the flash memory rewrite code using the...

  • Page 500: Block Erase Function

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.1 Block Erase Function This function erases the flash memory data by block (8 Kbytes). Erase operation becomes enabled by writing "01H" to the flash self register. Write "0FAH" and "0F5H" to the flash acceptor (FLASHACP) and set the block address in the flash segment register (FLASHSEG) and the flash address register H (FLASHAH).
  • Page 501 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Figure 29-2 shows a sample program of block erase. ; EA ← FLASHAH address offset FLASHAH #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #(offset FLASHACP)&0FFH ; ER4 ← FLASHACP address #(offset FLASHACP)>>8 (Set the erase start block address to R9) FSELF...

  • Page 502: Sector Erase Function

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.2 Sector Erase Function This function erases the flash memory data by sector (1 Kbytes). Erase operation becomes enabled by writing "01H" to the flash self register. Write "0FAH" and "0F5H" to the flash acceptor (FLASHACP) and set the sector address in the flash segment register (FLASHSEG) and the flash address register H (FLASHAH).
  • Page 503 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Figure 29-4 shows a sample program of sector erase. ; EA ← FLASHAH address offset FLASHAH #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #(offset FLASHACP)&0FFH ; ER4 ← FLASHACP address #(offset FLASHACP)>>8 (Set the erase start sector address to R9) FSELF...

  • Page 504: 1-Word Write Function

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.3 1-word Write Function This function writes data to the flash memory by 1 word (2 bytes). Write operation becomes enabled by writing "01H" to the flash self register. Write "0FAH" and "0F5H" to the flash acceptor (FLASHACP) and set the address in the flash segment register (FLASHSEG) and the flash address register L, H (FLASHAL,H).
  • Page 505 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function Figure 29-6 shows a sample program of 1-word write. ; EA ← FLASHAH address offset FLASHAH #0FAH ; Flash acceptor enable data #0F5H ; Flash acceptor enable data #02H ; Address increment data #00H #(offset FLASHACP)&0FFH ;...

  • Page 506: Boot Area Remap Function By Software

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.4 Boot Area Remap Function by Software This function can remap the area from 0000H to 0FFFH (4 KB) to the area of the same size (4 KB) starting from the address set in the REMAPADD register.

  • Page 507: Notes In Use

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 29 Flash Memory Rewrite Function 29.3.5 Notes in Use In case an instantaneous power failure happened or the operation is terminated forcibly by a reset during block erase or sector erase or 1-word write, retry the operation to rewrite the area of 8K/1K bytes. In case the LSI did not start up by the failures that an instantaneous or a forced power failure happened, during rewriting of block or sector containing 0:0000H in the program area, rewrite the program by using the on-chip debug emulator (uEASE).
  • Page 508 Chapter 30 Code-Option...

  • Page 509: Code-Option

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 30 Code-Option 30 Code-Option 3.1 General Description This LSI has the code-option function. The code-option function can select the low-speed oscillation clock, LLD circuit operation and the LLD threshold voltage level. 3.1.1 Features  Low-speed crystal oscillation or low-speed RC oscillation is selectable for the low-speed clock. ...

  • Page 510: Code-Option Register 0 (Codeop0)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 30 Code-Option 30.2.2 Code-Option Register 0 (CODEOP0) Address: 0F3D8H Access: R Access size: 8 bits Initial value: Undefined ― ― ― ― CODEOP0 COLOSC LLDSEL LLD1 LLD0 ― ― ― ― Initial value 0/1* 0/1* 0/1* 0/1* 0/1* 0/1*...

  • Page 511: The Setting Method Of The Code-Option Data

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 30 Code-Option 30.3 The Setting Method of the Code-Option Data 30.3.1 Code-Option Data Format ML620Q151B/ML620Q154B/ML620Q157B : The code-option data is set on address 0：07DE0H which is in writable test data area of program memory. ML620Q152B/ML620Q155B/ML620Q158B : The code-option data is set on address 0：0BDE0H which is in writable test data area of program memory.

  • Page 512: External Interrupt Control Circuit

    Chapter 31 External Interrupt Control Circuit...

  • Page 513: Features

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31 External Interrupt Control Circuit 31.1 General Description 8 port pins (P00 to P05, P30, P31) are configurable as the external interrupt. 7 port pins (P00 to P04, P30, P31) on ML620Q151B/ML620Q152B/ML620Q153B. 31.1.1 Features ...

  • Page 514: List Of Pins

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31.1.3 List of Pins Pin name Function P00/EXI0 External 0 interrupt P01/EXI1 External 1 interrupt P02/EXI2 External 2 interrupt P03/EXI3 External 3 interrupt P04/EXI4 External 4 interrupt P05/EXI5* External 5 interrupt P30/EXI6 External 6 interrupt P31/EXI7...

  • Page 515: Description Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31.2 Description of Registers 31.2.1 List of Registers Address Name Symbol Symbol Size Initial value (Byte) (Word) 0F038H External interrupt control registers 0 EXICON0 8/16 EXICON01 0F039H External interrupt control registers 1 EXICON1 0F03AH External interrupt control registers 2...

  • Page 516: External Interrupt Control Register 0, 1 (Exicon0, Exicon1)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31.2.2 External Interrupt Control Register 0, 1 (EXICON0, EXICON1) Address: 0F038H Access: R/W Access size: 8/16 bits Initial value: 00H EXICON0 P31E0 P30E0 P05E0 P04E0 P03E0 P02E0 P01E0 P00E0 — Initial value Address: 0F039H Access: R/W Access size: 8 bits...

  • Page 517: External Interrupt Control Register 2 (Exicon2)

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31.2.3 External Interrupt Control Register 2 (EXICON2) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 00H EXICON2 P31SM P30SM P05SM P04SM P03SM P02SM P01SM P00SM Initial value EXICON2 is a special function register (SFR) to select whether the Port 0 and Port 3 interrupt is with sampling or without sampling.
  • Page 518 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit  P31SM-P30SM (bits 7-6) The P31SM to P30SM bits are used to select whether the Port 3 interrupt is with or without sampling. The sampling clock is T16KHZ of the low-speed time base counter (LTBC). P30SM Description Detects the input signal edge for P30 interrupt without sampling (initial value).

  • Page 519: Description Of Operation

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit 31.3 Description of Operation 31.3.1 External Interrupt The Port 0 and Port 3 pins (P00, P01, P02, P03, P04, P05, P30, P31) can be used as P00 to P05 and P30 to P31 interrupts (P00INT to P05INT and P30INT to P31INT).
  • Page 520 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Chapter 31 External Interrupt Control Circuit T16KHZ SYSTEMCLK P3m pin, P0n pin P3mINT,P0nINT n=0 to 5 Interrupt request m=0 to 1 QP3m,QP0n (d) When Rising-Edge Interrupt Mode with Sampling is Selected Figure 31-2 External Interrupt Generation Timing When rising-edge interrupt mode with sampling is selected, the input level of P0n and P3m pins is checked at falling edges of T16KHz.
  • Page 521 Appendix A...

  • Page 522: Appendix A Contents Of Registers

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Contents of Registers Address Symbol Symbol 8/16 Initial name Byte Word value － 0F000H Data segment register － － － － 0F001H Reserve 0F002H Frequency control register 0 FCON0 8/16 FCON 0F003H Frequency control register 1 FCON1 －...
  • Page 523 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value － － － 0F02EH Reserve ILC5W 0F02FH Interrupt level control register 51 ILC51 0F030H Interrupt level control register 60 ILC60 8/16 ILC6W 0F031H Interrupt level control register 61 ILC61 0F032H Interrupt level control register 70...
  • Page 524 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value － 0F21BH Port 1 direction register P1DIR 0F21CH Port 1 control register 0 P1CON0 8/16 P1CON 0F21DH Port 1 control register 1 P1CON1 － 0F228H Port 2 data register －...
  • Page 525 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F310H Timer 0 counter register TM0C 8/16 TM01C 0F311H Timer 1 counter register TM1C 0F320H Timer 0 control register TM0CON 8/16 TM01CON 0F321H Timer 1 control register TM1CON －...
  • Page 526 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F4A8H PWM4 control register 2 PW4CON2 8/16 PW4CON 0F4A9H PWM4 control register 3 PW4CON3 0F4AAH PWM4 control register 4 PW4CON4 8/16 PW4CON 0F4ABH PWM4 control register 5 PW4CON5 ―...
  • Page 527 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F700H Serial port transmit/receive buffer L SIO0BUFL 8/16 SIO0BUF 0F701H Serial port transmit/receive buffer H SIO0BUFH － 0F702H Serial port control register SIO0CON Serial port mode register 0 0F704H SIO0MOD0 8/16...
  • Page 528 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix A Registers Address Symbol Symbol 8/16 Initial name Byte Word value 0F8DCH SA-ADC result register 6L SADR6L 8/16 SADR6 0F8DDH SA-ADC result register 6H SADR6H 0F8DEH SA-ADC result register 7L SADR7L 8/16 SADR7 SA-ADC result register 7H 0F8DFH SADR7H 0F8E0H...
  • Page 529 Appendix B...

  • Page 530: Appendix B Package Dimensions

    The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 531 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 532 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 533 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
  • Page 534 Appendix C...
  • Page 535 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics  Absolute Maximum Ratings = 0V) Parameter Symbol Condition Rating Unit 0.3 to +6.5 Power supply voltage 1 Ta = 25C 0.3 to +2.0 Power supply voltage 2 Ta = 25C 0.3 to V Reference voltage Ta = 25C...
  • Page 536 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  Flash Memory Operating Conditions = 0V) Parameter Symbol Condition Range Unit Data flash memory, At write/erase -40 to +105 C Operating temperature Flash ROM, At write/erase 0 to +40 Operating voltage At write/erase 1.8 to 5.5 Data Flash 10,000...

  • Page 537: Appendix C Electrical Characteristics

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  DC Characteristics (VOHL, IOHL) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Output voltage 1 IOH1 = 0.5mA (P20 to P23) ―...
  • Page 538 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  DC Characteristics (VIHL) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Measuring Parameter Symbol Condition Min. Typ. Max. Unit circuit Input voltage 1 (RESET_N) (P14/TEST0) 0.7 ― ― VIH1 (TEST1_N) (P00 to P05)* (P12, P13)
  • Page 539 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  DC Characteristics (LLD) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Meas Parameter Symbol Condition Min. Typ. Max. Unit uring circuit When power rising 1.85 1.98 LD1 to 0 = 0H When power falling When power rising 2.63...
  • Page 540 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  Measuring circuit 1 32.768kHz crystal ：2.2μF ：2.2μF ：12pF ：12pF 32.768kHz Crystal oscillator (DT-26 DAISHINKU Corp.)  Measuring circuit 2 (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. FEUL620Q150B...
  • Page 541 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  Measuring circuit 3 (*1) (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins.  Measuring circuit 4 (*3) (*3) Measured at the specified input pins. ...
  • Page 542 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  AC Characteristics (Oscillation Circuit) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Measur Parameter Symbol Condition Min. Typ. Max. Unit circuit Low-speed crystal oscillation ― ― start time* Ta= +25C 32.768k Low-speed RC oscillator Ta= -40 to 85C...
  • Page 543 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  AC Characteristics (External Interrupt) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit External interrupt disable Interrupt: Enabled (MIE = 1), 2.5 3.5 s ―...
  • Page 544 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics  AC Characteristics (Synchronous Serial Port) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit s ― ― High-speed oscillation stopped SCK input cycle SCYC ―...
  • Page 545 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics AC Characteristics (I C Bus Interface: Standard Mode 100kbps) =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max.   SCL clock frequency SCL hold time ...
  • Page 546 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix C Electrical Characteristics Electrical Characteristics of Successive Approximation Type A/D Converter =1.8 to 5.5V, V =0V, Ta=40 to +105C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit ― ― ― Resolution bits 2.7V  V ...
  • Page 547 Appendix D...

  • Page 548: Appendix D Application Circuit Example

    C EEPROM 0.1uF 0.1uF 0.01uF 32.768kHz crystal : DT-26 (DAISHINKU CORP.) RESET IC : BU4219 (ROHM Co., Ltd. N-ch open drain output) [Note] Design the PCB layout having the shortest wiring distance between VDDL and VSS for noise reduction purpose. FEUL620Q150B...
  • Page 549 Appendix E...

  • Page 550: Appendix E Check List

    ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix E Check List Appendix E Check List This Check List has notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood hardware features of the MCU. Check each note listed up chapter by chapter while coding the program or evaluating it using the MCU. Chapter 1 Overview •About unused pins [ ] Please confirm how to handle the unused pins(Refer to Section 1.3.4 in the user’s manual).
  • Page 551 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix E Check List Chapter 5 Interrupts •Unused interrupt vector table [ ] Please define all unused interrupt vector tables for fail safe. •Non-maskable interrupt [ ] The watchdog timer interrupt (WDTINT) and clock backup interrupt (CKCINT) are non-maskable interrupt that does not depend on MIE flag (Refer to Sections 5.2.10.
  • Page 552 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix E Check List Chapter 12 Synchronous Serial Port •Pins used [ ] Multiple ways to assign the pins(*): P40(SIN0), P41(SCK0), P42(SOUT0), P44(SIN0), P45(SCK0), P46(SOUT0), P50(SIN0), P51(SCK0), P52(SOUT0), P55(SIN0), P56(SCK0), P57(SOUT0), P72(SIN0), P73(SCK0), P74(SOUT0), P80(SIN0), P81(SCK0), P82(SOUT0), P84(SIN0), P85(SCK0), P86(SOUT0). (*) ML620Q151B/ML620Q152B/ML620Q153B/ML620Q15BA/ML620Q155B/ML620Q156B/ML620Q157B/ ML620Q158B/ ML620Q159B have a different pin configuration for each package.
  • Page 553 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Appendix E Check List Chapter 29 FLASH Memory Rewrite Function [ ] Be sure to set the NOP instruction twice or more, following the block erase start instruction. [ ] Be sure to set the NOP instruction twice or more, following the sector erase start instruction. [ ] Be sure to set the NOP instruction twice or more, following the write to Flash data register (FLASHDH) instruction.

  • Page 554: Revision History

    Revision History...
  • Page 555 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Revision of History Revision History Page Document No. Date Description Previous Current Edition Edition – – FEU620Q150B-01 Mar 15, 2017 Fromal 1 Revision Correction of the pkg name(64 pin QFP) FEU620Q150B-02 July 1, 2017 Change of the figure of pkg (64 pin QFP) Add handling with the memory area of code option.
  • Page 556 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Revision of History Page Document No. Date Description Previous Current Edition Edition Correction of errors Original: P3MOD1 register (address: 0F21DH) Corrected: P3MOD1 register (address: 0F23BH) Original: P3MOD0 register (address: 0F21CH) Corrected: P3MOD0 register (address: 0F23AH) Original: P3CON1 register (address: 0F21BH) 11-81 11-81 Corrected: P3CON1 register (address: 0F239H)
  • Page 557 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Revision of History Page Document No. Date Description Previous Current Edition Edition Correction of errors Original: P4MOD1 register (Address: 0F225H) Corrected: P4MOD1 register (Address: 0F249H) Original: P4MOD0 register (Address: 0F224H) Corrected: P4MOD0 register (Address: 0F248H) Original: P4CON1 register (Address: 0F223H) 12-11 12-11 Corrected: P4CON1 register (Address: 0F247H)
  • Page 558 ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B User's Manual Revision of History Page Document No. Date Description Previous Current Edition Edition Correction of error Original: The test data area (0:7C00h to 7FFFh) can not be erased/written. Corrected: The test data area (0:7E00h to 7FFFh) can not be erased/written. Correction of error Original:0: The test data area (0:0BC00h to 0BFFFh) 29-1...

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